1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 #include "amdgpu_ttm.h" 39 40 struct drm_exec; 41 42 struct amdgpu_bo_va; 43 struct amdgpu_job; 44 struct amdgpu_bo_list_entry; 45 struct amdgpu_bo_vm; 46 47 /* 48 * GPUVM handling 49 */ 50 51 /* Maximum number of PTEs the hardware can write with one command */ 52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 53 54 /* number of entries in page table */ 55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 56 57 #define AMDGPU_PTE_VALID (1ULL << 0) 58 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 59 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 60 61 /* RV+ */ 62 #define AMDGPU_PTE_TMZ (1ULL << 3) 63 64 /* VI only */ 65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 66 67 #define AMDGPU_PTE_READABLE (1ULL << 5) 68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 69 70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 71 72 /* TILED for VEGA10, reserved for older ASICs */ 73 #define AMDGPU_PTE_PRT (1ULL << 51) 74 75 /* PDE is handled as PTE for VEGA10 */ 76 #define AMDGPU_PDE_PTE (1ULL << 54) 77 78 #define AMDGPU_PTE_LOG (1ULL << 55) 79 80 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 81 #define AMDGPU_PTE_TF (1ULL << 56) 82 83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 84 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 85 86 /* PDE Block Fragment Size for VEGA10 */ 87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 88 89 /* Flag combination to set no-retry with TF disabled */ 90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ 91 AMDGPU_PTE_TF) 92 93 /* Flag combination to set no-retry with TF enabled */ 94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ 95 AMDGPU_PTE_PRT) 96 /* For GFX9 */ 97 #define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype) ((uint64_t)(mtype) << 57) 98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL) 99 #define AMDGPU_PTE_MTYPE_VG10(flags, mtype) \ 100 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \ 101 AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) 102 103 #define AMDGPU_MTYPE_NC 0 104 #define AMDGPU_MTYPE_CC 2 105 106 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 107 | AMDGPU_PTE_SNOOPED \ 108 | AMDGPU_PTE_EXECUTABLE \ 109 | AMDGPU_PTE_READABLE \ 110 | AMDGPU_PTE_WRITEABLE \ 111 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 112 113 /* gfx10 */ 114 #define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48) 115 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL) 116 #define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \ 117 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \ 118 AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) 119 120 /* gfx12 */ 121 #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56) 122 #define AMDGPU_PTE_PRT_FLAG(adev) \ 123 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT) 124 125 #define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54) 126 #define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL) 127 #define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \ 128 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \ 129 AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) 130 131 #define AMDGPU_PTE_DCC (1ULL << 58) 132 #define AMDGPU_PTE_BUS_ATOMICS (1ULL << 59) 133 #define AMDGPU_PTE_IS_PTE (1ULL << 63) 134 135 /* PDE Block Fragment Size for gfx v12 */ 136 #define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58) 137 #define AMDGPU_PDE_BFS_FLAG(adev, a) \ 138 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a)) 139 /* PDE is handled as PTE for gfx v12 */ 140 #define AMDGPU_PDE_PTE_GFX12 (1ULL << 63) 141 #define AMDGPU_PDE_PTE_FLAG(adev) \ 142 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE) 143 144 /* Flag combination to set no-retry on GFX 12 */ 145 #define AMDGPU_VM_NORETRY_FLAGS_GFX12 (AMDGPU_PTE_SYSTEM | AMDGPU_PTE_SNOOPED) 146 /* How to program VM fault handling */ 147 #define AMDGPU_VM_FAULT_STOP_NEVER 0 148 #define AMDGPU_VM_FAULT_STOP_FIRST 1 149 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 150 151 /* How much VRAM be reserved for page tables */ 152 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 153 154 /* 155 * max number of VMHUB 156 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 157 */ 158 #define AMDGPU_MAX_VMHUBS 13 159 #define AMDGPU_GFXHUB_START 0 160 #define AMDGPU_MMHUB0_START 8 161 #define AMDGPU_MMHUB1_START 12 162 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) 163 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) 164 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) 165 166 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) 167 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) 168 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) 169 170 /* Reserve space at top/bottom of address space for kernel use */ 171 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) 172 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \ 173 << AMDGPU_GPU_PAGE_SHIFT) \ 174 - AMDGPU_VA_RESERVED_CSA_SIZE) 175 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) 176 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ 177 - AMDGPU_VA_RESERVED_SEQ64_SIZE) 178 #define AMDGPU_VA_RESERVED_TRAP_SIZE (1ULL << 16) 179 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ 180 - AMDGPU_VA_RESERVED_TRAP_SIZE) 181 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16) 182 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \ 183 AMDGPU_VA_RESERVED_SEQ64_SIZE + \ 184 AMDGPU_VA_RESERVED_CSA_SIZE) 185 186 /* See vm_update_mode */ 187 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 188 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 189 190 /* VMPT level enumerate, and the hiberachy is: 191 * PDB3->PDB2->PDB1->PDB0->PTB 192 */ 193 enum amdgpu_vm_level { 194 AMDGPU_VM_PDB3, 195 AMDGPU_VM_PDB2, 196 AMDGPU_VM_PDB1, 197 AMDGPU_VM_PDB0, 198 AMDGPU_VM_PTB 199 }; 200 201 /* base structure for tracking BO usage in a VM */ 202 struct amdgpu_vm_bo_base { 203 /* constant after initialization */ 204 struct amdgpu_vm *vm; 205 struct amdgpu_bo *bo; 206 207 /* protected by bo being reserved */ 208 struct amdgpu_vm_bo_base *next; 209 210 /* protected by vm reservation and invalidated_lock */ 211 struct list_head vm_status; 212 213 /* if the bo is counted as shared in mem stats 214 * protected by vm BO being reserved */ 215 bool shared; 216 217 /* if the BO was moved and all mappings are invalid 218 * protected by the BO being reserved */ 219 bool moved; 220 }; 221 222 /* 223 * The following status lists contain amdgpu_vm_bo_base objects for 224 * either PD/PTs, per VM BOs or BOs with individual resv object. 225 * 226 * The state transits are: evicted -> needs_update -> idle 227 */ 228 struct amdgpu_vm_bo_status { 229 /* BOs evicted which need to move into place again */ 230 struct list_head evicted; 231 232 /* BOs whose mappings changed but PDs/PTs haven't been updated */ 233 struct list_head needs_update; 234 235 /* BOs done with the state machine and need no further action */ 236 struct list_head idle; 237 }; 238 239 /* provided by hw blocks that can write ptes, e.g., sdma */ 240 struct amdgpu_vm_pte_funcs { 241 /* number of dw to reserve per operation */ 242 unsigned copy_pte_num_dw; 243 244 /* copy pte entries from GART */ 245 void (*copy_pte)(struct amdgpu_ib *ib, 246 uint64_t pe, uint64_t src, 247 unsigned count); 248 249 /* write pte one entry at a time with addr mapping */ 250 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 251 uint64_t value, unsigned count, 252 uint32_t incr); 253 /* for linear pte/pde updates without addr mapping */ 254 void (*set_pte_pde)(struct amdgpu_ib *ib, 255 uint64_t pe, 256 uint64_t addr, unsigned count, 257 uint32_t incr, uint64_t flags); 258 }; 259 260 struct amdgpu_task_info { 261 struct drm_wedge_task_info task; 262 char process_name[TASK_COMM_LEN]; 263 pid_t tgid; 264 struct kref refcount; 265 }; 266 267 struct amdgpu_vm_fault_info { 268 /* fault address */ 269 uint64_t addr; 270 /* fault status register */ 271 uint32_t status; 272 /* which vmhub? gfxhub, mmhub, etc. */ 273 unsigned int vmhub; 274 }; 275 276 struct amdgpu_mem_stats { 277 struct drm_memory_stats drm; 278 279 /* buffers that requested this placement but are currently evicted */ 280 uint64_t evicted; 281 }; 282 283 struct amdgpu_vm { 284 /* tree of virtual addresses mapped */ 285 struct rb_root_cached va; 286 287 /* Lock to prevent eviction while we are updating page tables 288 * use vm_eviction_lock/unlock(vm) 289 */ 290 struct mutex eviction_lock; 291 bool evicting; 292 293 /* Memory statistics for this vm, protected by stats_lock */ 294 spinlock_t stats_lock; 295 struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]; 296 297 /* BO's belonging to PD/PT which are internal to the kernel. */ 298 struct amdgpu_vm_bo_status kernel; 299 300 /* 301 * BOs allocated by userspace where the dma_resv is shared with the 302 * root PD 303 */ 304 struct amdgpu_vm_bo_status always_valid; 305 306 /* 307 * The following lists contain amdgpu_vm_bo_base objects for BOs which 308 * have their own dma_resv object and not depend on the root PD. 309 * 310 * Lists are protected by the individual_lock. 311 */ 312 spinlock_t individual_lock; 313 314 /* Userspace BOs with individual resv object */ 315 struct amdgpu_vm_bo_status individual; 316 317 /* 318 * This list contains amdgpu_bo_va_mapping objects which have been freed 319 * but not updated in the PTs 320 */ 321 struct list_head freed; 322 323 /* contains the page directory */ 324 struct amdgpu_vm_bo_base root; 325 struct dma_fence *last_update; 326 327 /* Scheduler entities for page table updates */ 328 struct drm_sched_entity immediate; 329 struct drm_sched_entity delayed; 330 331 /* Last finished delayed update */ 332 atomic64_t tlb_seq; 333 struct dma_fence *last_tlb_flush; 334 atomic64_t kfd_last_flushed_seq; 335 uint64_t tlb_fence_context; 336 337 /* How many times we had to re-generate the page tables */ 338 uint64_t generation; 339 340 /* Last unlocked submission to the scheduler entities */ 341 struct dma_fence *last_unlocked; 342 343 unsigned int pasid; 344 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS]; 345 346 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 347 bool use_cpu_for_update; 348 349 /* Functions to use for VM table updates */ 350 const struct amdgpu_vm_update_funcs *update_funcs; 351 352 /* Up to 128 pending retry page faults */ 353 DECLARE_KFIFO(faults, u64, 128); 354 355 /* Points to the KFD process VM info */ 356 struct amdkfd_process_info *process_info; 357 358 /* List node in amdkfd_process_info.vm_list_head */ 359 struct list_head vm_list_node; 360 361 /* Valid while the PD is reserved or fenced */ 362 uint64_t pd_phys_addr; 363 364 /* Some basic info about the task */ 365 struct amdgpu_task_info *task_info; 366 367 /* Store positions of group of BOs */ 368 struct ttm_lru_bulk_move lru_bulk_move; 369 /* Flag to indicate if VM is used for compute */ 370 bool is_compute_context; 371 /* Flag to indicate that page tables are for NPA mappings */ 372 bool is_npa; 373 /* Flag to indicate if VM needs a TLB fence (KFD or KGD) */ 374 bool need_tlb_fence; 375 376 /* Memory partition number, -1 means any partition */ 377 int8_t mem_id; 378 379 /* cached fault info */ 380 struct amdgpu_vm_fault_info fault_info; 381 }; 382 383 struct amdgpu_vm_manager { 384 /* Handling of VMIDs */ 385 struct amdgpu_kq_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 386 unsigned int first_kfd_vmid; 387 bool concurrent_flush; 388 389 uint64_t max_pfn; 390 uint32_t max_level; 391 uint32_t num_level; 392 uint32_t block_size; 393 uint32_t fragment_size; 394 enum amdgpu_vm_level root_level; 395 /* vram base address for page table entry */ 396 u64 vram_base_offset; 397 /* vm pte handling */ 398 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 399 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 400 unsigned vm_pte_num_scheds; 401 struct amdgpu_ring *page_fault; 402 403 /* partial resident texture handling */ 404 spinlock_t prt_lock; 405 atomic_t num_prt_users; 406 407 /* controls how VM page tables are updated for Graphics and Compute. 408 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 409 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 410 */ 411 int vm_update_mode; 412 413 /* Global registration of recent page fault information */ 414 struct amdgpu_vm_fault_info fault_info; 415 unsigned int npa_vmid; 416 417 /* VMID masks for GFXHUB and MMHUB */ 418 uint32_t vmid_uq_mask_gfxhub; 419 uint32_t vmid_uq_mask_mmhub; 420 }; 421 422 struct amdgpu_bo_va_mapping; 423 424 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 425 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 426 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 427 428 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 429 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 430 431 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 432 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 433 434 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 435 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); 436 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 437 int amdgpu_vm_make_npa(struct amdgpu_device *adev, struct amdgpu_vm *vm); 438 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 439 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, 440 unsigned int num_fences); 441 int amdgpu_vm_lock_individual(struct amdgpu_vm *vm, struct drm_exec *exec, 442 unsigned int num_fences); 443 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 444 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); 445 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, 446 struct ww_acquire_ctx *ticket, 447 int (*callback)(void *p, struct amdgpu_bo *bo), 448 void *param); 449 void amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, 450 bool *need_pipe_sync, bool *emit_spm_needed, 451 bool *emit_gds_needed); 452 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 453 struct amdgpu_vm *vm, bool immediate); 454 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 455 struct amdgpu_vm *vm, 456 struct dma_fence **fence); 457 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 458 struct amdgpu_vm *vm, 459 struct ww_acquire_ctx *ticket); 460 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, 461 struct amdgpu_vm *vm, 462 uint32_t flush_type, 463 uint32_t xcc_mask); 464 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 465 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 466 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 467 bool immediate, bool unlocked, bool flush_tlb, 468 bool allow_override, struct amdgpu_sync *sync, 469 uint64_t start, uint64_t last, uint64_t flags, 470 uint64_t offset, uint64_t vram_base, 471 struct ttm_resource *res, dma_addr_t *pages_addr, 472 struct dma_fence **fence); 473 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 474 struct amdgpu_bo_va *bo_va, 475 bool clear); 476 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 477 void amdgpu_vm_bo_invalidate(struct amdgpu_bo *bo, bool evicted); 478 void amdgpu_vm_update_stats(struct amdgpu_vm_bo_base *base, 479 struct ttm_resource *new_res, int sign); 480 void amdgpu_vm_bo_update_shared(struct amdgpu_bo *bo); 481 void amdgpu_vm_bo_move(struct amdgpu_bo *bo, struct ttm_resource *new_mem, 482 bool evicted); 483 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 484 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 485 struct amdgpu_bo *bo); 486 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 487 struct amdgpu_vm *vm, 488 struct amdgpu_bo *bo); 489 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 490 struct amdgpu_bo_va *bo_va, 491 uint64_t addr, uint64_t offset, 492 uint64_t size, uint32_t flags); 493 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 494 struct amdgpu_bo_va *bo_va, 495 uint64_t addr, uint64_t offset, 496 uint64_t size, uint32_t flags); 497 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 498 struct amdgpu_bo_va *bo_va, 499 uint64_t addr); 500 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 501 struct amdgpu_vm *vm, 502 uint64_t saddr, uint64_t size); 503 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 504 uint64_t addr); 505 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 506 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 507 struct amdgpu_bo_va *bo_va); 508 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 509 uint32_t fragment_size_default, unsigned max_level, 510 unsigned max_bits); 511 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 512 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 513 struct amdgpu_job *job); 514 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 515 516 struct amdgpu_task_info * 517 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid); 518 519 struct amdgpu_task_info * 520 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm); 521 522 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info); 523 524 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 525 u32 vmid, u32 node_id, uint64_t addr, uint64_t ts, 526 bool write_fault); 527 528 struct amdgpu_vm *amdgpu_vm_lock_by_pasid(struct amdgpu_device *adev, 529 u32 pasid, struct drm_exec *exec); 530 531 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 532 533 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 534 struct amdgpu_vm *vm); 535 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 536 struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]); 537 538 #if defined(CONFIG_DEBUG_FS) 539 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 540 #endif 541 542 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); 543 544 bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo); 545 546 /** 547 * amdgpu_vm_tlb_seq - return tlb flush sequence number 548 * @vm: the amdgpu_vm structure to query 549 * 550 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 551 * to be invalidated whenever the sequence number change. 552 */ 553 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 554 { 555 unsigned long flags; 556 spinlock_t *lock; 557 558 /* 559 * Workaround to stop racing between the fence signaling and handling 560 * the cb. The lock is static after initially setting it up, just make 561 * sure that the dma_fence structure isn't freed up. 562 */ 563 rcu_read_lock(); 564 lock = dma_fence_spinlock(vm->last_tlb_flush); 565 rcu_read_unlock(); 566 567 spin_lock_irqsave(lock, flags); 568 spin_unlock_irqrestore(lock, flags); 569 570 return atomic64_read(&vm->tlb_seq); 571 } 572 573 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, 574 unsigned int pasid, 575 uint64_t addr, 576 uint32_t status, 577 unsigned int vmhub); 578 void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, 579 struct amdgpu_vm *vm, 580 struct dma_fence **fence); 581 582 void amdgpu_vm_print_task_info(struct amdgpu_device *adev, 583 struct amdgpu_task_info *task_info); 584 585 #define amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) \ 586 list_for_each_entry(mapping, &(bo_va)->valids, list) 587 #define amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) \ 588 list_for_each_entry(mapping, &(bo_va)->invalids, list) 589 590 #endif 591