1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_TTM_H__ 25 #define __AMDGPU_TTM_H__ 26 27 #include <linux/dma-direction.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/ttm/ttm_placement.h> 30 #include "amdgpu_vram_mgr.h" 31 #include "amdgpu_hmm.h" 32 #include "amdgpu_gmc.h" 33 34 #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) 35 #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) 36 #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) 37 #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) 38 #define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4) 39 #define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5) 40 #define AMDGPU_PL_NPA (TTM_PL_PRIV + 6) 41 #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 7) 42 43 44 #define AMDGPU_GTT_MAX_TRANSFER_SIZE (1ULL << 22) 45 46 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 47 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 48 49 struct hmm_range; 50 51 struct amdgpu_gtt_mgr { 52 struct ttm_resource_manager manager; 53 struct drm_mm mm; 54 spinlock_t lock; 55 }; 56 57 struct amdgpu_ttm_buffer_entity { 58 struct drm_sched_entity base; 59 struct mutex lock; 60 struct drm_mm_node gart_node; 61 u64 gart_window_offs[2]; 62 }; 63 64 enum amdgpu_resv_region_id { 65 AMDGPU_RESV_STOLEN_VGA, 66 AMDGPU_RESV_STOLEN_EXTENDED, 67 AMDGPU_RESV_STOLEN_RESERVED, 68 AMDGPU_RESV_FW, 69 AMDGPU_RESV_FW_EXTEND, 70 AMDGPU_RESV_FW_VRAM_USAGE, 71 AMDGPU_RESV_DRV_VRAM_USAGE, 72 AMDGPU_RESV_MEM_TRAIN, 73 AMDGPU_RESV_MAX 74 }; 75 76 struct amdgpu_vram_resv { 77 uint64_t offset; 78 uint64_t size; 79 struct amdgpu_bo *bo; 80 void *cpu_ptr; 81 bool needs_cpu_map; 82 }; 83 84 struct amdgpu_mman { 85 struct ttm_device bdev; 86 struct ttm_pool *ttm_pools; 87 bool initialized; 88 void __iomem *aper_base_kaddr; 89 90 /* buffer handling */ 91 const struct amdgpu_buffer_funcs *buffer_funcs; 92 struct drm_gpu_scheduler *buffer_funcs_scheds[AMDGPU_MAX_RINGS]; 93 u32 num_buffer_funcs_scheds; 94 bool buffer_funcs_enabled; 95 96 /* @default_entity: for workarounds, has no gart windows */ 97 struct amdgpu_ttm_buffer_entity default_entity; 98 struct amdgpu_ttm_buffer_entity *clear_entities; 99 atomic_t next_clear_entity; 100 u32 num_clear_entities; 101 struct amdgpu_ttm_buffer_entity move_entities[TTM_NUM_MOVE_FENCES]; 102 atomic_t next_move_entity; 103 u32 num_move_entities; 104 105 struct amdgpu_vram_mgr vram_mgr; 106 struct amdgpu_gtt_mgr gtt_mgr; 107 struct ttm_resource_manager preempt_mgr; 108 109 bool keep_stolen_vga_memory; 110 111 struct amdgpu_vram_resv resv_region[AMDGPU_RESV_MAX]; 112 113 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */ 114 struct amdgpu_bo *sdma_access_bo; 115 void *sdma_access_ptr; 116 }; 117 118 struct amdgpu_copy_mem { 119 struct ttm_buffer_object *bo; 120 struct ttm_resource *mem; 121 unsigned long offset; 122 }; 123 124 #define AMDGPU_COPY_FLAGS_TMZ (1 << 0) 125 #define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED (1 << 1) 126 #define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED (1 << 2) 127 #define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_SHIFT 3 128 #define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_MASK 0x03 129 #define AMDGPU_COPY_FLAGS_NUMBER_TYPE_SHIFT 5 130 #define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07 131 #define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT 8 132 #define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f 133 #define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT 14 134 #define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK 0x1 135 136 #define AMDGPU_COPY_FLAGS_SET(field, value) \ 137 (((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT) 138 #define AMDGPU_COPY_FLAGS_GET(value, field) \ 139 (((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAGS_##field##_MASK) 140 141 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); 142 void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); 143 int amdgpu_preempt_mgr_init(struct amdgpu_device *adev); 144 void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev); 145 void amdgpu_preempt_mgr_sysfs_fini(struct amdgpu_device *adev); 146 int amdgpu_vram_mgr_init(struct amdgpu_device *adev); 147 void amdgpu_vram_mgr_fini(struct amdgpu_device *adev); 148 149 bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem); 150 void amdgpu_gtt_mgr_mark_bo_teardown(struct ttm_buffer_object *tbo); 151 void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr); 152 153 int amdgpu_gtt_mgr_alloc_entries(struct amdgpu_gtt_mgr *mgr, 154 struct drm_mm_node *mm_node, 155 u64 num_pages, 156 enum drm_mm_insert_mode mode); 157 void amdgpu_gtt_mgr_free_entries(struct amdgpu_gtt_mgr *mgr, 158 struct drm_mm_node *mm_node); 159 uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man); 160 161 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo); 162 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, 163 struct ttm_resource *mem, 164 u64 offset, u64 size, 165 struct device *dev, 166 enum dma_data_direction dir, 167 struct sg_table **sgt); 168 void amdgpu_vram_mgr_free_sgt(struct device *dev, 169 enum dma_data_direction dir, 170 struct sg_table *sgt); 171 uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr); 172 int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr, 173 uint64_t start, uint64_t size); 174 int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr, 175 uint64_t start); 176 void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev); 177 178 bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, 179 struct ttm_resource *res); 180 181 void amdgpu_ttm_init_vram_resv(struct amdgpu_device *adev, 182 enum amdgpu_resv_region_id id, 183 uint64_t offset, uint64_t size, 184 bool needs_cpu_map); 185 int amdgpu_ttm_mark_vram_reserved(struct amdgpu_device *adev, 186 enum amdgpu_resv_region_id id); 187 void amdgpu_ttm_unmark_vram_reserved(struct amdgpu_device *adev, 188 enum amdgpu_resv_region_id id); 189 190 int amdgpu_ttm_init(struct amdgpu_device *adev); 191 void amdgpu_ttm_fini(struct amdgpu_device *adev); 192 void amdgpu_ttm_enable_buffer_funcs(struct amdgpu_device *adev); 193 void amdgpu_ttm_disable_buffer_funcs(struct amdgpu_device *adev); 194 int amdgpu_copy_buffer(struct amdgpu_device *adev, 195 struct amdgpu_ttm_buffer_entity *entity, 196 uint64_t src_offset, 197 uint64_t dst_offset, uint32_t byte_count, 198 struct dma_resv *resv, 199 struct dma_fence **fence, 200 bool vm_needs_flush, uint32_t copy_flags); 201 int amdgpu_ttm_clear_buffer(struct amdgpu_ttm_buffer_entity *entity, 202 struct amdgpu_bo *bo, 203 struct dma_resv *resv, 204 struct dma_fence **out_fence, 205 bool consider_clear_status, 206 u64 k_job_id); 207 struct amdgpu_ttm_buffer_entity *amdgpu_ttm_next_clear_entity(struct amdgpu_device *adev); 208 209 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); 210 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); 211 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); 212 213 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 214 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 215 struct amdgpu_hmm_range *range); 216 #else 217 static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 218 struct amdgpu_hmm_range *range) 219 { 220 return -EPERM; 221 } 222 #endif 223 224 /** 225 * amdgpu_compute_gart_address() - Returns GART address of an entity's window 226 * @gmc: The &struct amdgpu_gmc instance to use 227 * @entity: The &struct amdgpu_ttm_buffer_entity owning the GART window 228 * @index: The window to use (must be 0 or 1) 229 */ 230 static inline u64 amdgpu_compute_gart_address(struct amdgpu_gmc *gmc, 231 struct amdgpu_ttm_buffer_entity *entity, 232 int index) 233 { 234 return gmc->gart_start + entity->gart_window_offs[index]; 235 } 236 237 /** 238 * amdgpu_gtt_node_to_byte_offset() - Returns a byte offset of a gtt node 239 */ 240 static inline u64 amdgpu_gtt_node_to_byte_offset(const struct drm_mm_node *gtt_node) 241 { 242 return gtt_node->start * (u64)PAGE_SIZE; 243 } 244 245 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range); 246 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 247 uint64_t *user_addr); 248 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 249 uint64_t addr, uint32_t flags); 250 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 251 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 252 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 253 unsigned long end, unsigned long *userptr); 254 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 255 int *last_invalidated); 256 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); 257 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 258 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); 259 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 260 struct ttm_resource *mem); 261 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type); 262 263 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 264 265 int amdgpu_ttm_mmio_remap_alloc_sgt(struct amdgpu_device *adev, 266 struct ttm_resource *res, 267 struct device *dev, 268 enum dma_data_direction dir, 269 struct sg_table **sgt); 270 void amdgpu_ttm_mmio_remap_free_sgt(struct device *dev, 271 enum dma_data_direction dir, 272 struct sg_table *sgt); 273 274 #endif 275