1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 #include <linux/workqueue.h> 33 34 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 35 #define AMDGPU_MES_MAX_GFX_PIPES 2 36 #define AMDGPU_MES_MAX_SDMA_PIPES 2 37 38 #define AMDGPU_MES_API_VERSION_SHIFT 12 39 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 40 41 #define AMDGPU_MES_VERSION_MASK 0x00000fff 42 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 43 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 44 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 45 #define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff 46 47 enum amdgpu_mes_priority_level { 48 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 49 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 50 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 51 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 52 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 53 AMDGPU_MES_PRIORITY_NUM_LEVELS 54 }; 55 56 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 57 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 58 #define AMDGPU_MES_PROC_CTX_ARRAY_MAX 128 59 #define AMDGPU_MES_GANG_CTX_ARRAY_MAX 512 60 struct amdgpu_mes_funcs; 61 62 enum amdgpu_mes_pipe { 63 AMDGPU_MES_PIPE_0 = 0, 64 AMDGPU_MES_PIPE_1, 65 AMDGPU_MAX_MES_PIPES = 2, 66 }; 67 68 #define AMDGPU_MES_SCHED_PIPE AMDGPU_MES_PIPE_0 69 #define AMDGPU_MES_KIQ_PIPE AMDGPU_MES_PIPE_1 70 71 #define AMDGPU_MAX_MES_INST_PIPES \ 72 (AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES) 73 74 #define MES_PIPE_INST(xcc_id, pipe_id) \ 75 (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id) 76 77 struct amdgpu_mes { 78 struct amdgpu_device *adev; 79 80 struct mutex mutex_hidden; 81 82 struct ida doorbell_ida; 83 84 spinlock_t queue_id_lock; 85 86 uint32_t sched_version; 87 uint32_t kiq_version; 88 uint32_t fw_version[AMDGPU_MAX_MES_PIPES]; 89 bool enable_legacy_queue_map; 90 91 uint32_t total_max_queue; 92 uint32_t max_doorbell_slices; 93 94 /* GFX11 usermode queue oversubscription notify timer */ 95 atomic_t userq_hw_queue_count; 96 struct delayed_work userq_notify_unmap_work; 97 98 uint64_t default_process_quantum; 99 uint64_t default_gang_quantum; 100 101 struct amdgpu_ring ring[AMDGPU_MAX_MES_INST_PIPES]; 102 spinlock_t ring_lock[AMDGPU_MAX_MES_INST_PIPES]; 103 104 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 105 106 /* mes ucode */ 107 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 108 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 109 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 110 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 111 112 /* mes ucode data */ 113 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 114 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 115 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 116 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 117 118 /* eop gpu obj */ 119 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 120 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 121 122 void *mqd_backup[AMDGPU_MAX_MES_INST_PIPES]; 123 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES]; 124 125 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 126 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 127 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 128 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 129 130 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES]; 131 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 132 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES]; 133 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES]; 134 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 135 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES]; 136 137 uint32_t saved_flags; 138 139 /* initialize kiq pipe */ 140 int (*kiq_hw_init)(struct amdgpu_device *adev, 141 uint32_t xcc_id); 142 int (*kiq_hw_fini)(struct amdgpu_device *adev, 143 uint32_t xcc_id); 144 145 /* MES doorbells */ 146 uint32_t db_start_dw_offset; 147 uint32_t num_mes_dbs; 148 unsigned long *doorbell_bitmap; 149 150 /* MES event log buffer */ 151 uint32_t event_log_size; 152 struct amdgpu_bo *event_log_gpu_obj; 153 uint64_t event_log_gpu_addr; 154 void *event_log_cpu_addr; 155 156 /* MES firmware debug extension ("mes_dbgext") log buffer */ 157 uint32_t dbgext_log_size; /* per-XCC region size */ 158 uint64_t dbgext_log_options; 159 struct amdgpu_bo *dbgext_log_gpu_obj; 160 uint64_t dbgext_log_gpu_addr; 161 void *dbgext_log_cpu_addr; 162 bool dbgext_use_irq; 163 164 /* 165 * Number of per-XCC log regions packed back-to-back in the buffer above; 166 * each is dbgext_log_size bytes. 1 on single-XCC ASICs (gfx11/gfx12). 167 */ 168 uint32_t dbgext_num_xcc; 169 170 /* armed: FW attached + reader/irq running */ 171 bool dbgext_active; 172 173 struct work_struct dbgext_work; 174 struct task_struct *dbgext_reader; /* polling fallback */ 175 struct mutex dbgext_lock; /* serializes runtime start/stop */ 176 177 /* runtime-requested size (KB); 0 = follow module param */ 178 uint32_t dbgext_runtime_kb; 179 180 /* ip specific functions */ 181 const struct amdgpu_mes_funcs *funcs; 182 183 /* mes resource_1 bo*/ 184 struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES]; 185 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; 186 void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 187 188 int hung_queue_db_array_size; 189 int hung_queue_hqd_info_offset; 190 struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 191 uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 192 void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 193 194 /* cooperative dispatch */ 195 bool enable_coop_mode; 196 int master_xcc_ids[AMDGPU_MAX_MES_INST_PIPES]; 197 struct amdgpu_bo *shared_cmd_buf_obj[AMDGPU_MAX_MES_INST_PIPES]; 198 uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 199 200 bool compute_pipe_reset_enabled; 201 bool gfx_pipe_reset_enabled; 202 203 bool use_rs64mem; 204 struct amdgpu_bo *ctx_array_size_bo; 205 uint64_t ctx_array_size_gpu_addr; 206 uint32_t *ctx_array_size_cpu_ptr; 207 208 uint32_t proc_ctx_array_size; 209 unsigned long *proc_ctx_bitmap; 210 uint32_t gang_ctx_array_size; 211 uint32_t gang_ctx_array_index; 212 unsigned long *gang_ctx_bitmap; 213 }; 214 215 struct amdgpu_mes_hung_queue_hqd_info { 216 union { 217 struct { 218 u32 queue_type: 3; // queue type 219 u32 pipe_index: 4; // pipe index 220 u32 queue_index: 8; // queue index 221 u32 reserved: 17; 222 }; 223 224 u32 bit0_31; 225 }; 226 }; 227 228 struct amdgpu_mes_gang { 229 int gang_id; 230 int priority; 231 int inprocess_gang_priority; 232 int global_priority_level; 233 struct list_head list; 234 struct amdgpu_mes_process *process; 235 struct amdgpu_bo *gang_ctx_bo; 236 uint64_t gang_ctx_gpu_addr; 237 void *gang_ctx_cpu_ptr; 238 uint64_t gang_quantum; 239 struct list_head queue_list; 240 }; 241 242 struct amdgpu_mes_queue { 243 struct list_head list; 244 struct amdgpu_mes_gang *gang; 245 int queue_id; 246 uint64_t doorbell_off; 247 struct amdgpu_bo *mqd_obj; 248 void *mqd_cpu_ptr; 249 uint64_t mqd_gpu_addr; 250 uint64_t wptr_gpu_addr; 251 int queue_type; 252 int paging; 253 struct amdgpu_ring *ring; 254 }; 255 256 struct amdgpu_mes_queue_properties { 257 int queue_type; 258 uint64_t hqd_base_gpu_addr; 259 uint64_t rptr_gpu_addr; 260 uint64_t wptr_gpu_addr; 261 uint64_t wptr_mc_addr; 262 uint32_t queue_size; 263 uint64_t eop_gpu_addr; 264 uint32_t hqd_pipe_priority; 265 uint32_t hqd_queue_priority; 266 bool paging; 267 struct amdgpu_ring *ring; 268 /* out */ 269 uint64_t doorbell_off; 270 }; 271 272 struct amdgpu_mes_gang_properties { 273 uint32_t priority; 274 uint32_t gang_quantum; 275 uint32_t inprocess_gang_priority; 276 uint32_t priority_level; 277 int global_priority_level; 278 }; 279 280 struct mes_add_queue_input { 281 uint32_t xcc_id; 282 uint32_t process_id; 283 uint64_t page_table_base_addr; 284 uint64_t process_va_start; 285 uint64_t process_va_end; 286 uint64_t process_quantum; 287 uint64_t process_context_addr; 288 uint64_t gang_quantum; 289 uint64_t gang_context_addr; 290 uint32_t inprocess_gang_priority; 291 uint32_t gang_global_priority_level; 292 uint32_t doorbell_offset; 293 uint64_t mqd_addr; 294 uint64_t wptr_addr; 295 uint64_t wptr_mc_addr; 296 uint32_t queue_type; 297 uint32_t paging; 298 uint32_t gws_base; 299 uint32_t gws_size; 300 uint64_t tba_addr; 301 uint64_t tma_addr; 302 uint32_t trap_en; 303 uint32_t skip_process_ctx_clear; 304 uint32_t is_kfd_process; 305 uint32_t is_aql_queue; 306 uint32_t queue_size; 307 uint32_t exclusively_scheduled; 308 uint32_t sh_mem_config_data; 309 uint32_t vm_cntx_cntl; 310 uint32_t process_context_array_index; 311 uint32_t gang_context_array_index; 312 }; 313 314 struct mes_remove_queue_input { 315 uint32_t xcc_id; 316 uint32_t doorbell_offset; 317 uint64_t gang_context_addr; 318 uint32_t queue_type; 319 bool remove_queue_after_reset; 320 uint32_t gang_context_array_index; 321 }; 322 323 struct mes_map_legacy_queue_input { 324 uint32_t xcc_id; 325 uint32_t queue_type; 326 uint32_t doorbell_offset; 327 uint32_t pipe_id; 328 uint32_t queue_id; 329 uint64_t mqd_addr; 330 uint64_t wptr_addr; 331 }; 332 333 struct mes_unmap_legacy_queue_input { 334 uint32_t xcc_id; 335 enum amdgpu_unmap_queues_action action; 336 uint32_t queue_type; 337 uint32_t doorbell_offset; 338 uint32_t pipe_id; 339 uint32_t queue_id; 340 uint64_t trail_fence_addr; 341 uint64_t trail_fence_data; 342 }; 343 344 struct mes_suspend_gang_input { 345 uint32_t xcc_id; 346 bool suspend_all_gangs; 347 bool suspend_all_sdma_gangs; 348 uint64_t gang_context_addr; 349 uint64_t suspend_fence_addr; 350 uint32_t suspend_fence_value; 351 uint32_t doorbell_offset; 352 }; 353 354 struct mes_resume_gang_input { 355 uint32_t xcc_id; 356 bool resume_all_gangs; 357 uint64_t gang_context_addr; 358 uint32_t doorbell_offset; 359 }; 360 361 struct mes_reset_queue_input { 362 uint32_t xcc_id; 363 uint32_t queue_type; 364 uint32_t doorbell_offset; 365 bool use_mmio; 366 uint32_t me_id; 367 uint32_t pipe_id; 368 uint32_t queue_id; 369 uint64_t mqd_addr; 370 uint64_t wptr_addr; 371 uint32_t vmid; 372 bool legacy_gfx; 373 bool is_kq; 374 }; 375 376 struct mes_detect_and_reset_queue_input { 377 u32 queue_type; 378 bool detect_only; 379 u32 xcc_id; 380 }; 381 382 struct mes_inv_tlbs_pasid_input { 383 uint32_t xcc_id; 384 uint16_t pasid; 385 uint8_t hub_id; 386 uint8_t flush_type; 387 }; 388 389 enum mes_misc_opcode { 390 MES_MISC_OP_WRITE_REG, 391 MES_MISC_OP_READ_REG, 392 MES_MISC_OP_WRM_REG_WAIT, 393 MES_MISC_OP_WRM_REG_WR_WAIT, 394 MES_MISC_OP_SET_SHADER_DEBUGGER, 395 MES_MISC_OP_CHANGE_CONFIG, 396 MES_MISC_OP_NOTIFY_WORK_ON_UNMAPPED_QUEUE, 397 MES_MISC_OP_SETUP_MES_DBGEXT, 398 }; 399 400 struct mes_misc_op_input { 401 uint32_t xcc_id; 402 enum mes_misc_opcode op; 403 404 union { 405 struct { 406 uint32_t reg_offset; 407 uint64_t buffer_addr; 408 } read_reg; 409 410 struct { 411 uint32_t reg_offset; 412 uint32_t reg_value; 413 } write_reg; 414 415 struct { 416 uint32_t ref; 417 uint32_t mask; 418 uint32_t reg0; 419 uint32_t reg1; 420 } wrm_reg; 421 422 struct { 423 uint64_t process_context_addr; 424 union { 425 struct { 426 uint32_t single_memop : 1; 427 uint32_t single_alu_op : 1; 428 uint32_t reserved: 29; 429 uint32_t process_ctx_flush: 1; 430 }; 431 uint32_t u32all; 432 } flags; 433 uint32_t spi_gdbg_per_vmid_cntl; 434 uint32_t tcp_watch_cntl[4]; 435 uint32_t trap_en; 436 } set_shader_debugger; 437 438 struct { 439 union { 440 struct { 441 uint32_t limit_single_process : 1; 442 uint32_t enable_hws_logging_buffer : 1; 443 uint32_t reserved : 30; 444 }; 445 uint32_t all; 446 } option; 447 struct { 448 uint32_t tdr_level; 449 uint32_t tdr_delay; 450 } tdr_config; 451 } change_config; 452 453 struct { 454 uint64_t log_buffer_mc_addr; 455 uint64_t log_options; 456 } setup_mes_dbgext; 457 }; 458 }; 459 460 struct amdgpu_mes_funcs { 461 int (*add_hw_queue)(struct amdgpu_mes *mes, 462 struct mes_add_queue_input *input); 463 464 int (*remove_hw_queue)(struct amdgpu_mes *mes, 465 struct mes_remove_queue_input *input); 466 467 int (*map_legacy_queue)(struct amdgpu_mes *mes, 468 struct mes_map_legacy_queue_input *input); 469 470 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 471 struct mes_unmap_legacy_queue_input *input); 472 473 int (*suspend_gang)(struct amdgpu_mes *mes, 474 struct mes_suspend_gang_input *input); 475 476 int (*resume_gang)(struct amdgpu_mes *mes, 477 struct mes_resume_gang_input *input); 478 479 int (*misc_op)(struct amdgpu_mes *mes, 480 struct mes_misc_op_input *input); 481 482 /* 483 * Enable/disable the MES firmware debug-extension host interrupt at the 484 * hardware level. Runs in process context (may take srbm_mutex), unlike 485 * the atomic irq .set callback. 486 */ 487 int (*enable_dbgext_irq)(struct amdgpu_mes *mes, bool enable); 488 489 int (*reset_hw_queue)(struct amdgpu_mes *mes, 490 struct mes_reset_queue_input *input); 491 492 int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, 493 struct mes_detect_and_reset_queue_input *input); 494 495 496 int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, 497 struct mes_inv_tlbs_pasid_input *input); 498 }; 499 500 enum amdgpu_mqd_update_flag { 501 AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, 502 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, 503 AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 504 }; 505 506 struct amdgpu_mqd_prop { 507 uint64_t mqd_gpu_addr; 508 uint64_t hqd_base_gpu_addr; 509 uint64_t rptr_gpu_addr; 510 uint64_t wptr_gpu_addr; 511 uint32_t queue_size; 512 bool use_doorbell; 513 uint32_t doorbell_index; 514 uint64_t eop_gpu_addr; 515 uint32_t hqd_pipe_priority; 516 uint32_t hqd_queue_priority; 517 uint32_t mqd_stride_size; 518 bool allow_tunneling; 519 bool hqd_active; 520 uint64_t shadow_addr; 521 uint64_t gds_bkup_addr; 522 uint64_t csa_addr; 523 uint64_t fence_address; 524 bool tmz_queue; 525 bool kernel_queue; 526 uint32_t *cu_mask; 527 uint32_t cu_mask_count; 528 uint32_t cu_flags; 529 bool is_user_cu_masked; 530 }; 531 532 struct amdgpu_mqd { 533 unsigned mqd_size; 534 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 535 struct amdgpu_mqd_prop *p); 536 }; 537 538 /* 539 * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) 540 * as fence address and writes a 32 bit fence value to this address. 541 * Driver needs to allocate at least 4 DWs extra memory in addition to 542 * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. 543 */ 544 #define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) 545 546 #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ 547 (adev)->mes.kiq_hw_init((adev), (xcc_id)) 548 #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ 549 (adev)->mes.kiq_hw_fini((adev), (xcc_id)) 550 551 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 552 void amdgpu_mes_validate_fw_version(struct amdgpu_device *adev); 553 int amdgpu_mes_init(struct amdgpu_device *adev); 554 void amdgpu_mes_fini(struct amdgpu_device *adev); 555 556 int amdgpu_mes_dbgext_start(struct amdgpu_device *adev); 557 void amdgpu_mes_dbgext_stop(struct amdgpu_device *adev); 558 void amdgpu_mes_dbgext_notify(struct amdgpu_device *adev, u32 context_data); 559 560 /* 561 * MES host-interrupt context dword (IH src_data[0]), same overlay as KMD 562 * IRQMGR_INTERRUPT_CONTEXTDATA_MES and firmware MES_INT_CONTEXT_DATA: 563 * bits 25:0 payload (doorbell / reserved) 564 * bits 31:26 interrupt type (MES_DBGMSG = 7) 565 */ 566 #define AMDGPU_MES_IH_INT_TYPE_SHIFT 26 567 #define AMDGPU_MES_IH_INT_TYPE_MASK 0x3f 568 #define AMDGPU_MES_IH_INT_TYPE_DBGMSG 7 569 570 static inline uint32_t amdgpu_mes_ih_int_type(uint32_t context_data) 571 { 572 return (context_data >> AMDGPU_MES_IH_INT_TYPE_SHIFT) & 573 AMDGPU_MES_IH_INT_TYPE_MASK; 574 } 575 576 int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id); 577 int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id); 578 579 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 580 struct amdgpu_ring *ring, uint32_t xcc_id); 581 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 582 struct amdgpu_ring *ring, 583 enum amdgpu_unmap_queues_action action, 584 u64 gpu_addr, u64 seq, uint32_t xcc_id); 585 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 586 struct amdgpu_ring *ring, 587 unsigned int vmid, 588 bool use_mmio, 589 uint32_t xcc_id); 590 int amdgpu_mes_reset_queue_mmio(struct amdgpu_device *adev, 591 int queue_type, 592 unsigned int vmid, 593 unsigned int me, 594 unsigned int pipe, 595 unsigned int queue, 596 uint32_t xcc_id); 597 int amdgpu_mes_reset_user_queue(struct amdgpu_device *adev, 598 int queue_type, 599 unsigned int doorbell_index, 600 unsigned int xcc_id); 601 602 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); 603 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 604 int queue_type, 605 bool detect_only, 606 unsigned int *hung_db_num, 607 u32 *hung_db_array, 608 uint32_t xcc_id); 609 610 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, 611 uint32_t xcc_id); 612 int amdgpu_mes_wreg(struct amdgpu_device *adev, 613 uint32_t reg, uint32_t val, uint32_t xcc_id); 614 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 615 uint32_t reg0, uint32_t reg1, 616 uint32_t ref, uint32_t mask, uint32_t xcc_id); 617 int amdgpu_mes_hdp_flush(struct amdgpu_device *adev); 618 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 619 uint64_t process_context_addr, 620 uint32_t spi_gdbg_per_vmid_cntl, 621 const uint32_t *tcp_watch_cntl, 622 uint32_t flags, 623 bool trap_en, 624 uint32_t xcc_id); 625 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 626 uint64_t process_context_addr, uint32_t xcc_id); 627 628 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 629 enum amdgpu_mes_priority_level prio); 630 631 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 632 633 /* 634 * MES lock can be taken in MMU notifiers. 635 * 636 * A bit more detail about why to set no-FS reclaim with MES lock: 637 * 638 * The purpose of the MMU notifier is to stop GPU access to memory so 639 * that the Linux VM subsystem can move pages around safely. This is 640 * done by preempting user mode queues for the affected process. When 641 * MES is used, MES lock needs to be taken to preempt the queues. 642 * 643 * The MMU notifier callback entry point in the driver is 644 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 645 * there is: 646 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 647 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 648 * 649 * The last part of the chain is a function pointer where we take the 650 * MES lock. 651 * 652 * The problem with taking locks in the MMU notifier is, that MMU 653 * notifiers can be called in reclaim-FS context. That's where the 654 * kernel frees up pages to make room for new page allocations under 655 * memory pressure. While we are running in reclaim-FS context, we must 656 * not trigger another memory reclaim operation because that would 657 * recursively reenter the reclaim code and cause a deadlock. The 658 * memalloc_nofs_save/restore calls guarantee that. 659 * 660 * In addition we also need to avoid lock dependencies on other locks taken 661 * under the MES lock, for example reservation locks. Here is a possible 662 * scenario of a deadlock: 663 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 664 * MMU notifier | blocks trying to take MES lock 665 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 666 * 667 * In this scenario Thread B gets involved in a deadlock even without 668 * triggering a reclaim-FS operation itself. 669 * To fix this and break the lock dependency chain you'd need to either: 670 * 1. protect reservation locks with memalloc_nofs_save/restore, or 671 * 2. avoid taking reservation locks under the MES lock. 672 * 673 * Reservation locks are taken all over the kernel in different subsystems, we 674 * have no control over them and their lock dependencies.So the only workable 675 * solution is to avoid taking other locks under the MES lock. 676 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 677 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 678 */ 679 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 680 { 681 mutex_lock(&mes->mutex_hidden); 682 mes->saved_flags = memalloc_noreclaim_save(); 683 } 684 685 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 686 { 687 memalloc_noreclaim_restore(mes->saved_flags); 688 mutex_unlock(&mes->mutex_hidden); 689 } 690 691 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 692 bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev); 693 694 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); 695 696 int amdgpu_mes_rs64mem_init(struct amdgpu_mes *mes); 697 void amdgpu_mes_rs64mem_fini(struct amdgpu_mes *mes); 698 int amdgpu_mes_rs64mem_setup_bitmaps(struct amdgpu_mes *mes); 699 int amdgpu_mes_alloc_proc_ctx_index(struct amdgpu_mes *mes, 700 uint32_t *index); 701 void amdgpu_mes_free_proc_ctx_index(struct amdgpu_mes *mes, 702 uint32_t index); 703 int amdgpu_mes_alloc_gang_ctx_index(struct amdgpu_mes *mes, 704 uint32_t *index); 705 void amdgpu_mes_free_gang_ctx_index(struct amdgpu_mes *mes, 706 uint32_t index); 707 708 int amdgpu_mes_notify_unmap_queue(struct amdgpu_device *adev); 709 void amdgpu_mes_userq_queue_mapped(struct amdgpu_device *adev); 710 void amdgpu_mes_userq_queue_unmapped(struct amdgpu_device *adev); 711 712 #endif /* __AMDGPU_MES_H__ */ 713