1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 #include "amdgpu_ttm.h" 39 40 struct drm_exec; 41 42 struct amdgpu_bo_va; 43 struct amdgpu_job; 44 struct amdgpu_bo_list_entry; 45 struct amdgpu_bo_vm; 46 47 /* 48 * GPUVM handling 49 */ 50 51 /* Maximum number of PTEs the hardware can write with one command */ 52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 53 54 /* number of entries in page table */ 55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 56 57 #define AMDGPU_PTE_VALID (1ULL << 0) 58 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 59 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 60 61 /* RV+ */ 62 #define AMDGPU_PTE_TMZ (1ULL << 3) 63 64 /* VI only */ 65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 66 67 #define AMDGPU_PTE_READABLE (1ULL << 5) 68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 69 70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 71 72 /* TILED for VEGA10, reserved for older ASICs */ 73 #define AMDGPU_PTE_PRT (1ULL << 51) 74 75 /* PDE is handled as PTE for VEGA10 */ 76 #define AMDGPU_PDE_PTE (1ULL << 54) 77 78 #define AMDGPU_PTE_LOG (1ULL << 55) 79 80 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 81 #define AMDGPU_PTE_TF (1ULL << 56) 82 83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 84 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 85 86 /* PDE Block Fragment Size for VEGA10 */ 87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 88 89 /* Flag combination to set no-retry with TF disabled */ 90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ 91 AMDGPU_PTE_TF) 92 93 /* Flag combination to set no-retry with TF enabled */ 94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ 95 AMDGPU_PTE_PRT) 96 /* For GFX9 */ 97 #define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype) ((uint64_t)(mtype) << 57) 98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL) 99 #define AMDGPU_PTE_MTYPE_VG10(flags, mtype) \ 100 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \ 101 AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) 102 103 #define AMDGPU_MTYPE_NC 0 104 #define AMDGPU_MTYPE_CC 2 105 106 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 107 | AMDGPU_PTE_SNOOPED \ 108 | AMDGPU_PTE_EXECUTABLE \ 109 | AMDGPU_PTE_READABLE \ 110 | AMDGPU_PTE_WRITEABLE \ 111 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 112 113 /* gfx10 */ 114 #define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48) 115 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL) 116 #define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \ 117 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \ 118 AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) 119 120 /* gfx12 */ 121 #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56) 122 #define AMDGPU_PTE_PRT_FLAG(adev) \ 123 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT) 124 125 #define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54) 126 #define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL) 127 #define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \ 128 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \ 129 AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) 130 131 #define AMDGPU_PTE_DCC (1ULL << 58) 132 #define AMDGPU_PTE_BUS_ATOMICS (1ULL << 59) 133 #define AMDGPU_PTE_IS_PTE (1ULL << 63) 134 135 /* PDE Block Fragment Size for gfx v12 */ 136 #define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58) 137 #define AMDGPU_PDE_BFS_FLAG(adev, a) \ 138 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a)) 139 /* PDE is handled as PTE for gfx v12 */ 140 #define AMDGPU_PDE_PTE_GFX12 (1ULL << 63) 141 #define AMDGPU_PDE_PTE_FLAG(adev) \ 142 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE) 143 144 /* How to program VM fault handling */ 145 #define AMDGPU_VM_FAULT_STOP_NEVER 0 146 #define AMDGPU_VM_FAULT_STOP_FIRST 1 147 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 148 149 /* How much VRAM be reserved for page tables */ 150 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 151 152 /* 153 * max number of VMHUB 154 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 155 */ 156 #define AMDGPU_MAX_VMHUBS 13 157 #define AMDGPU_GFXHUB_START 0 158 #define AMDGPU_MMHUB0_START 8 159 #define AMDGPU_MMHUB1_START 12 160 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) 161 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) 162 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) 163 164 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) 165 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) 166 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) 167 168 /* Reserve space at top/bottom of address space for kernel use */ 169 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) 170 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \ 171 << AMDGPU_GPU_PAGE_SHIFT) \ 172 - AMDGPU_VA_RESERVED_CSA_SIZE) 173 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) 174 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ 175 - AMDGPU_VA_RESERVED_SEQ64_SIZE) 176 #define AMDGPU_VA_RESERVED_TRAP_SIZE (1ULL << 16) 177 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ 178 - AMDGPU_VA_RESERVED_TRAP_SIZE) 179 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16) 180 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \ 181 AMDGPU_VA_RESERVED_SEQ64_SIZE + \ 182 AMDGPU_VA_RESERVED_CSA_SIZE) 183 184 /* See vm_update_mode */ 185 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 186 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 187 188 /* VMPT level enumerate, and the hiberachy is: 189 * PDB3->PDB2->PDB1->PDB0->PTB 190 */ 191 enum amdgpu_vm_level { 192 AMDGPU_VM_PDB3, 193 AMDGPU_VM_PDB2, 194 AMDGPU_VM_PDB1, 195 AMDGPU_VM_PDB0, 196 AMDGPU_VM_PTB 197 }; 198 199 /* base structure for tracking BO usage in a VM */ 200 struct amdgpu_vm_bo_base { 201 /* constant after initialization */ 202 struct amdgpu_vm *vm; 203 struct amdgpu_bo *bo; 204 205 /* protected by bo being reserved */ 206 struct amdgpu_vm_bo_base *next; 207 208 /* protected by vm reservation and invalidated_lock */ 209 struct list_head vm_status; 210 211 /* if the bo is counted as shared in mem stats 212 * protected by vm BO being reserved */ 213 bool shared; 214 215 /* protected by the BO being reserved */ 216 bool moved; 217 }; 218 219 /* 220 * The following status lists contain amdgpu_vm_bo_base objects for 221 * either PD/PTs, per VM BOs or BOs with individual resv object. 222 * 223 * The state transits are: evicted -> moved -> idle 224 */ 225 struct amdgpu_vm_bo_status { 226 /* BOs evicted which need to move into place again */ 227 struct list_head evicted; 228 229 /* BOs which moved but new location hasn't been updated in the PDs/PTs */ 230 struct list_head moved; 231 232 /* BOs done with the state machine and need no further action */ 233 struct list_head idle; 234 }; 235 236 /* provided by hw blocks that can write ptes, e.g., sdma */ 237 struct amdgpu_vm_pte_funcs { 238 /* number of dw to reserve per operation */ 239 unsigned copy_pte_num_dw; 240 241 /* copy pte entries from GART */ 242 void (*copy_pte)(struct amdgpu_ib *ib, 243 uint64_t pe, uint64_t src, 244 unsigned count); 245 246 /* write pte one entry at a time with addr mapping */ 247 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 248 uint64_t value, unsigned count, 249 uint32_t incr); 250 /* for linear pte/pde updates without addr mapping */ 251 void (*set_pte_pde)(struct amdgpu_ib *ib, 252 uint64_t pe, 253 uint64_t addr, unsigned count, 254 uint32_t incr, uint64_t flags); 255 }; 256 257 struct amdgpu_task_info { 258 struct drm_wedge_task_info task; 259 char process_name[TASK_COMM_LEN]; 260 pid_t tgid; 261 struct kref refcount; 262 }; 263 264 /** 265 * struct amdgpu_vm_update_params 266 * 267 * Encapsulate some VM table update parameters to reduce 268 * the number of function parameters 269 * 270 */ 271 struct amdgpu_vm_update_params { 272 273 /** 274 * @adev: amdgpu device we do this update for 275 */ 276 struct amdgpu_device *adev; 277 278 /** 279 * @vm: optional amdgpu_vm we do this update for 280 */ 281 struct amdgpu_vm *vm; 282 283 /** 284 * @immediate: if changes should be made immediately 285 */ 286 bool immediate; 287 288 /** 289 * @unlocked: true if the root BO is not locked 290 */ 291 bool unlocked; 292 293 /** 294 * @pages_addr: 295 * 296 * DMA addresses to use for mapping 297 */ 298 dma_addr_t *pages_addr; 299 300 /** 301 * @job: job to used for hw submission 302 */ 303 struct amdgpu_job *job; 304 305 /** 306 * @num_dw_left: number of dw left for the IB 307 */ 308 unsigned int num_dw_left; 309 310 /** 311 * @needs_flush: true whenever we need to invalidate the TLB 312 */ 313 bool needs_flush; 314 315 /** 316 * @override_pte: true for memory that is not uncached and gmc override function is 317 * implemented to allow MTYPE to be overridden for NUMA local memory. 318 */ 319 bool override_pte; 320 321 /** 322 * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush 323 */ 324 struct list_head tlb_flush_waitlist; 325 }; 326 327 struct amdgpu_vm_update_funcs { 328 int (*map_table)(struct amdgpu_bo_vm *bo); 329 int (*prepare)(struct amdgpu_vm_update_params *p, 330 struct amdgpu_sync *sync, u64 k_job_id); 331 int (*update)(struct amdgpu_vm_update_params *p, 332 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 333 unsigned count, uint32_t incr, uint64_t flags); 334 int (*commit)(struct amdgpu_vm_update_params *p, 335 struct dma_fence **fence); 336 }; 337 338 struct amdgpu_vm_fault_info { 339 /* fault address */ 340 uint64_t addr; 341 /* fault status register */ 342 uint32_t status; 343 /* which vmhub? gfxhub, mmhub, etc. */ 344 unsigned int vmhub; 345 }; 346 347 struct amdgpu_mem_stats { 348 struct drm_memory_stats drm; 349 350 /* buffers that requested this placement but are currently evicted */ 351 uint64_t evicted; 352 }; 353 354 struct amdgpu_vm { 355 /* tree of virtual addresses mapped */ 356 struct rb_root_cached va; 357 358 /* Lock to prevent eviction while we are updating page tables 359 * use vm_eviction_lock/unlock(vm) 360 */ 361 struct mutex eviction_lock; 362 bool evicting; 363 unsigned int saved_flags; 364 365 /* Memory statistics for this vm, protected by stats_lock */ 366 spinlock_t stats_lock; 367 struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]; 368 369 /* BO's belonging to PD/PT which are internal to the kernel. */ 370 struct amdgpu_vm_bo_status kernel; 371 372 /* 373 * BOs allocated by userspace where the dma_resv is shared with the 374 * root PD 375 */ 376 struct amdgpu_vm_bo_status always_valid; 377 378 /* 379 * The following lists contain amdgpu_vm_bo_base objects for BOs which 380 * have their own dma_resv object and not depend on the root PD. 381 * 382 * Lists are protected by the individual_lock. 383 */ 384 spinlock_t individual_lock; 385 386 /* Userspace BOs with individual resv object */ 387 struct amdgpu_vm_bo_status individual; 388 389 /* 390 * This list contains amdgpu_bo_va_mapping objects which have been freed 391 * but not updated in the PTs 392 */ 393 struct list_head freed; 394 395 /* contains the page directory */ 396 struct amdgpu_vm_bo_base root; 397 struct dma_fence *last_update; 398 399 /* Scheduler entities for page table updates */ 400 struct drm_sched_entity immediate; 401 struct drm_sched_entity delayed; 402 403 /* Last finished delayed update */ 404 atomic64_t tlb_seq; 405 struct dma_fence *last_tlb_flush; 406 atomic64_t kfd_last_flushed_seq; 407 uint64_t tlb_fence_context; 408 409 /* How many times we had to re-generate the page tables */ 410 uint64_t generation; 411 412 /* Last unlocked submission to the scheduler entities */ 413 struct dma_fence *last_unlocked; 414 415 unsigned int pasid; 416 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS]; 417 418 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 419 bool use_cpu_for_update; 420 421 /* Functions to use for VM table updates */ 422 const struct amdgpu_vm_update_funcs *update_funcs; 423 424 /* Up to 128 pending retry page faults */ 425 DECLARE_KFIFO(faults, u64, 128); 426 427 /* Points to the KFD process VM info */ 428 struct amdkfd_process_info *process_info; 429 430 /* List node in amdkfd_process_info.vm_list_head */ 431 struct list_head vm_list_node; 432 433 /* Valid while the PD is reserved or fenced */ 434 uint64_t pd_phys_addr; 435 436 /* Some basic info about the task */ 437 struct amdgpu_task_info *task_info; 438 439 /* Store positions of group of BOs */ 440 struct ttm_lru_bulk_move lru_bulk_move; 441 /* Flag to indicate if VM is used for compute */ 442 bool is_compute_context; 443 /* Flag to indicate if VM needs a TLB fence (KFD or KGD) */ 444 bool need_tlb_fence; 445 446 /* Memory partition number, -1 means any partition */ 447 int8_t mem_id; 448 449 /* cached fault info */ 450 struct amdgpu_vm_fault_info fault_info; 451 }; 452 453 struct amdgpu_vm_manager { 454 /* Handling of VMIDs */ 455 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 456 unsigned int first_kfd_vmid; 457 bool concurrent_flush; 458 459 uint64_t max_pfn; 460 uint32_t max_level; 461 uint32_t num_level; 462 uint32_t block_size; 463 uint32_t fragment_size; 464 enum amdgpu_vm_level root_level; 465 /* vram base address for page table entry */ 466 u64 vram_base_offset; 467 /* vm pte handling */ 468 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 469 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 470 unsigned vm_pte_num_scheds; 471 struct amdgpu_ring *page_fault; 472 473 /* partial resident texture handling */ 474 spinlock_t prt_lock; 475 atomic_t num_prt_users; 476 477 /* controls how VM page tables are updated for Graphics and Compute. 478 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 479 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 480 */ 481 int vm_update_mode; 482 483 /* PASID to VM mapping, will be used in interrupt context to 484 * look up VM of a page fault 485 */ 486 struct xarray pasids; 487 /* Global registration of recent page fault information */ 488 struct amdgpu_vm_fault_info fault_info; 489 }; 490 491 struct amdgpu_bo_va_mapping; 492 493 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 494 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 495 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 496 497 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 498 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 499 500 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 501 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 502 503 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 504 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id, uint32_t pasid); 505 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 506 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 507 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, 508 unsigned int num_fences); 509 int amdgpu_vm_lock_individual(struct amdgpu_vm *vm, struct drm_exec *exec, 510 unsigned int num_fences); 511 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 512 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); 513 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, 514 struct ww_acquire_ctx *ticket, 515 int (*callback)(void *p, struct amdgpu_bo *bo), 516 void *param); 517 void amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 518 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 519 struct amdgpu_vm *vm, bool immediate); 520 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 521 struct amdgpu_vm *vm, 522 struct dma_fence **fence); 523 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 524 struct amdgpu_vm *vm, 525 struct ww_acquire_ctx *ticket); 526 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, 527 struct amdgpu_vm *vm, 528 uint32_t flush_type, 529 uint32_t xcc_mask); 530 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 531 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 532 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 533 bool immediate, bool unlocked, bool flush_tlb, 534 bool allow_override, struct amdgpu_sync *sync, 535 uint64_t start, uint64_t last, uint64_t flags, 536 uint64_t offset, uint64_t vram_base, 537 struct ttm_resource *res, dma_addr_t *pages_addr, 538 struct dma_fence **fence); 539 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 540 struct amdgpu_bo_va *bo_va, 541 bool clear); 542 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 543 void amdgpu_vm_bo_invalidate(struct amdgpu_bo *bo, bool evicted); 544 void amdgpu_vm_update_stats(struct amdgpu_vm_bo_base *base, 545 struct ttm_resource *new_res, int sign); 546 void amdgpu_vm_bo_update_shared(struct amdgpu_bo *bo); 547 void amdgpu_vm_bo_move(struct amdgpu_bo *bo, struct ttm_resource *new_mem, 548 bool evicted); 549 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 550 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 551 struct amdgpu_bo *bo); 552 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 553 struct amdgpu_vm *vm, 554 struct amdgpu_bo *bo); 555 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 556 struct amdgpu_bo_va *bo_va, 557 uint64_t addr, uint64_t offset, 558 uint64_t size, uint32_t flags); 559 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 560 struct amdgpu_bo_va *bo_va, 561 uint64_t addr, uint64_t offset, 562 uint64_t size, uint32_t flags); 563 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 564 struct amdgpu_bo_va *bo_va, 565 uint64_t addr); 566 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 567 struct amdgpu_vm *vm, 568 uint64_t saddr, uint64_t size); 569 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 570 uint64_t addr); 571 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 572 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 573 struct amdgpu_bo_va *bo_va); 574 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 575 uint32_t fragment_size_default, unsigned max_level, 576 unsigned max_bits); 577 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 578 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 579 struct amdgpu_job *job); 580 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 581 582 struct amdgpu_task_info * 583 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid); 584 585 struct amdgpu_task_info * 586 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm); 587 588 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info); 589 590 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 591 u32 vmid, u32 node_id, uint64_t addr, uint64_t ts, 592 bool write_fault); 593 594 struct amdgpu_vm *amdgpu_vm_lock_by_pasid(struct amdgpu_device *adev, 595 struct amdgpu_bo **root, u32 pasid); 596 597 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 598 599 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 600 struct amdgpu_vm *vm); 601 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 602 struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]); 603 604 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 605 struct amdgpu_bo_vm *vmbo, bool immediate); 606 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 607 int level, bool immediate, struct amdgpu_bo_vm **vmbo, 608 int32_t xcp_id); 609 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 610 611 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 612 struct amdgpu_vm_bo_base *entry); 613 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 614 uint64_t start, uint64_t end, 615 uint64_t dst, uint64_t flags); 616 void amdgpu_vm_pt_free_work(struct work_struct *work); 617 void amdgpu_vm_pt_free_list(struct amdgpu_device *adev, 618 struct amdgpu_vm_update_params *params); 619 620 #if defined(CONFIG_DEBUG_FS) 621 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 622 #endif 623 624 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); 625 626 bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo); 627 628 /** 629 * amdgpu_vm_tlb_seq - return tlb flush sequence number 630 * @vm: the amdgpu_vm structure to query 631 * 632 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 633 * to be invalidated whenever the sequence number change. 634 */ 635 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 636 { 637 unsigned long flags; 638 spinlock_t *lock; 639 640 /* 641 * Workaround to stop racing between the fence signaling and handling 642 * the cb. The lock is static after initially setting it up, just make 643 * sure that the dma_fence structure isn't freed up. 644 */ 645 rcu_read_lock(); 646 lock = dma_fence_spinlock(vm->last_tlb_flush); 647 rcu_read_unlock(); 648 649 spin_lock_irqsave(lock, flags); 650 spin_unlock_irqrestore(lock, flags); 651 652 return atomic64_read(&vm->tlb_seq); 653 } 654 655 /* 656 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 657 * happens while holding this lock anywhere to prevent deadlocks when 658 * an MMU notifier runs in reclaim-FS context. 659 */ 660 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 661 { 662 mutex_lock(&vm->eviction_lock); 663 vm->saved_flags = memalloc_noreclaim_save(); 664 } 665 666 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 667 { 668 if (mutex_trylock(&vm->eviction_lock)) { 669 vm->saved_flags = memalloc_noreclaim_save(); 670 return true; 671 } 672 return false; 673 } 674 675 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 676 { 677 memalloc_noreclaim_restore(vm->saved_flags); 678 mutex_unlock(&vm->eviction_lock); 679 } 680 681 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, 682 unsigned int pasid, 683 uint64_t addr, 684 uint32_t status, 685 unsigned int vmhub); 686 void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, 687 struct amdgpu_vm *vm, 688 struct dma_fence **fence); 689 690 void amdgpu_vm_print_task_info(struct amdgpu_device *adev, 691 struct amdgpu_task_info *task_info); 692 693 #define amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) \ 694 list_for_each_entry(mapping, &(bo_va)->valids, list) 695 #define amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) \ 696 list_for_each_entry(mapping, &(bo_va)->invalids, list) 697 698 #endif 699