1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linearized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 * 98 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 99 * signalling user mode queues. 100 */ 101 #define AMDGPU_GEM_DOMAIN_CPU 0x1 102 #define AMDGPU_GEM_DOMAIN_GTT 0x2 103 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 104 #define AMDGPU_GEM_DOMAIN_GDS 0x8 105 #define AMDGPU_GEM_DOMAIN_GWS 0x10 106 #define AMDGPU_GEM_DOMAIN_OA 0x20 107 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 108 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 109 AMDGPU_GEM_DOMAIN_GTT | \ 110 AMDGPU_GEM_DOMAIN_VRAM | \ 111 AMDGPU_GEM_DOMAIN_GDS | \ 112 AMDGPU_GEM_DOMAIN_GWS | \ 113 AMDGPU_GEM_DOMAIN_OA | \ 114 AMDGPU_GEM_DOMAIN_DOORBELL) 115 116 /* Flag that CPU access will be required for the case of VRAM domain */ 117 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 118 /* Flag that CPU access will not work, this VRAM domain is invisible */ 119 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 120 /* Flag that USWC attributes should be used for GTT */ 121 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 122 /* Flag that the memory should be in VRAM and cleared */ 123 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 124 /* Flag that allocating the BO should use linear VRAM */ 125 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 126 /* Flag that BO is always valid in this VM */ 127 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 128 /* Flag that BO sharing will be explicitly synchronized */ 129 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 130 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 131 * for the second page onward should be set to NC. It should never 132 * be used by user space applications. 133 */ 134 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 135 /* Flag that BO may contain sensitive data that must be wiped before 136 * releasing the memory 137 */ 138 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 139 /* Flag that BO will be encrypted and that the TMZ bit should be 140 * set in the PTEs when mapping this buffer via GPUVM or 141 * accessing it with various hw blocks 142 */ 143 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 144 /* Flag that BO will be used only in preemptible context, which does 145 * not require GTT memory accounting 146 */ 147 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 148 /* Flag that BO can be discarded under memory pressure without keeping the 149 * content. 150 */ 151 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 152 /* Flag that BO is shared coherently between multiple devices or CPU threads. 153 * May depend on GPU instructions to flush caches to system scope explicitly. 154 * 155 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 156 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 157 */ 158 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 159 /* Flag that BO should not be cached by GPU. Coherent without having to flush 160 * GPU caches explicitly 161 * 162 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 163 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 164 */ 165 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 166 /* Flag that BO should be coherent across devices when using device-level 167 * atomics. May depend on GPU instructions to flush caches to device scope 168 * explicitly, promoting them to system scope automatically. 169 * 170 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 171 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 172 */ 173 #define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 174 /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */ 175 #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) 176 177 struct drm_amdgpu_gem_create_in { 178 /** the requested memory size */ 179 __u64 bo_size; 180 /** physical start_addr alignment in bytes for some HW requirements */ 181 __u64 alignment; 182 /** the requested memory domains */ 183 __u64 domains; 184 /** allocation flags */ 185 __u64 domain_flags; 186 }; 187 188 struct drm_amdgpu_gem_create_out { 189 /** returned GEM object handle */ 190 __u32 handle; 191 __u32 _pad; 192 }; 193 194 union drm_amdgpu_gem_create { 195 struct drm_amdgpu_gem_create_in in; 196 struct drm_amdgpu_gem_create_out out; 197 }; 198 199 /** Opcode to create new residency list. */ 200 #define AMDGPU_BO_LIST_OP_CREATE 0 201 /** Opcode to destroy previously created residency list */ 202 #define AMDGPU_BO_LIST_OP_DESTROY 1 203 /** Opcode to update resource information in the list */ 204 #define AMDGPU_BO_LIST_OP_UPDATE 2 205 206 struct drm_amdgpu_bo_list_in { 207 /** Type of operation */ 208 __u32 operation; 209 /** Handle of list or 0 if we want to create one */ 210 __u32 list_handle; 211 /** Number of BOs in list */ 212 __u32 bo_number; 213 /** Size of each element describing BO */ 214 __u32 bo_info_size; 215 /** Pointer to array describing BOs */ 216 __u64 bo_info_ptr; 217 }; 218 219 struct drm_amdgpu_bo_list_entry { 220 /** Handle of BO */ 221 __u32 bo_handle; 222 /** New (if specified) BO priority to be used during migration */ 223 __u32 bo_priority; 224 }; 225 226 struct drm_amdgpu_bo_list_out { 227 /** Handle of resource list */ 228 __u32 list_handle; 229 __u32 _pad; 230 }; 231 232 union drm_amdgpu_bo_list { 233 struct drm_amdgpu_bo_list_in in; 234 struct drm_amdgpu_bo_list_out out; 235 }; 236 237 /* context related */ 238 #define AMDGPU_CTX_OP_ALLOC_CTX 1 239 #define AMDGPU_CTX_OP_FREE_CTX 2 240 #define AMDGPU_CTX_OP_QUERY_STATE 3 241 #define AMDGPU_CTX_OP_QUERY_STATE2 4 242 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 243 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 244 245 /* GPU reset status */ 246 #define AMDGPU_CTX_NO_RESET 0 247 /* this the context caused it */ 248 #define AMDGPU_CTX_GUILTY_RESET 1 249 /* some other context caused it */ 250 #define AMDGPU_CTX_INNOCENT_RESET 2 251 /* unknown cause */ 252 #define AMDGPU_CTX_UNKNOWN_RESET 3 253 254 /* indicate gpu reset occurred after ctx created */ 255 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 256 /* indicate vram lost occurred after ctx created */ 257 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 258 /* indicate some job from this context once cause gpu hang */ 259 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 260 /* indicate some errors are detected by RAS */ 261 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 262 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 263 /* indicate that the reset hasn't completed yet */ 264 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 265 266 /* Context priority level */ 267 #define AMDGPU_CTX_PRIORITY_UNSET -2048 268 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 269 #define AMDGPU_CTX_PRIORITY_LOW -512 270 #define AMDGPU_CTX_PRIORITY_NORMAL 0 271 /* 272 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 273 * CAP_SYS_NICE or DRM_MASTER 274 */ 275 #define AMDGPU_CTX_PRIORITY_HIGH 512 276 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 277 278 /* select a stable profiling pstate for perfmon tools */ 279 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 280 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 281 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 282 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 283 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 284 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 285 286 struct drm_amdgpu_ctx_in { 287 /** AMDGPU_CTX_OP_* */ 288 __u32 op; 289 /** Flags */ 290 __u32 flags; 291 __u32 ctx_id; 292 /** AMDGPU_CTX_PRIORITY_* */ 293 __s32 priority; 294 }; 295 296 union drm_amdgpu_ctx_out { 297 struct { 298 __u32 ctx_id; 299 __u32 _pad; 300 } alloc; 301 302 struct { 303 /** For future use, no flags defined so far */ 304 __u64 flags; 305 /** Number of resets caused by this context so far. */ 306 __u32 hangs; 307 /** Reset status since the last call of the ioctl. */ 308 __u32 reset_status; 309 } state; 310 311 struct { 312 __u32 flags; 313 __u32 _pad; 314 } pstate; 315 }; 316 317 union drm_amdgpu_ctx { 318 struct drm_amdgpu_ctx_in in; 319 union drm_amdgpu_ctx_out out; 320 }; 321 322 /* vm ioctl */ 323 #define AMDGPU_VM_OP_RESERVE_VMID 1 324 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 325 326 struct drm_amdgpu_vm_in { 327 /** AMDGPU_VM_OP_* */ 328 __u32 op; 329 __u32 flags; 330 }; 331 332 struct drm_amdgpu_vm_out { 333 /** For future use, no flags defined so far */ 334 __u64 flags; 335 }; 336 337 union drm_amdgpu_vm { 338 struct drm_amdgpu_vm_in in; 339 struct drm_amdgpu_vm_out out; 340 }; 341 342 /* sched ioctl */ 343 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 344 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 345 346 struct drm_amdgpu_sched_in { 347 /* AMDGPU_SCHED_OP_* */ 348 __u32 op; 349 __u32 fd; 350 /** AMDGPU_CTX_PRIORITY_* */ 351 __s32 priority; 352 __u32 ctx_id; 353 }; 354 355 union drm_amdgpu_sched { 356 struct drm_amdgpu_sched_in in; 357 }; 358 359 /* 360 * This is not a reliable API and you should expect it to fail for any 361 * number of reasons and have fallback path that do not use userptr to 362 * perform any operation. 363 */ 364 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 365 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 366 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 367 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 368 369 struct drm_amdgpu_gem_userptr { 370 __u64 addr; 371 __u64 size; 372 /* AMDGPU_GEM_USERPTR_* */ 373 __u32 flags; 374 /* Resulting GEM handle */ 375 __u32 handle; 376 }; 377 378 /* SI-CI-VI: */ 379 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 380 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 381 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 382 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 383 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 384 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 385 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 386 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 387 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 388 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 389 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 390 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 391 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 392 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 393 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 394 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 395 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 396 397 /* GFX9 - GFX11: */ 398 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 399 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 400 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 401 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 402 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 403 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 404 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 405 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 406 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 407 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 408 #define AMDGPU_TILING_SCANOUT_SHIFT 63 409 #define AMDGPU_TILING_SCANOUT_MASK 0x1 410 411 /* GFX12 and later: */ 412 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 413 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 414 /* These are DCC recompression setting for memory management: */ 415 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 416 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ 417 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 418 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ 419 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 420 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 421 422 /* Set/Get helpers for tiling flags. */ 423 #define AMDGPU_TILING_SET(field, value) \ 424 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 425 #define AMDGPU_TILING_GET(value, field) \ 426 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 427 428 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 429 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 430 431 /** The same structure is shared for input/output */ 432 struct drm_amdgpu_gem_metadata { 433 /** GEM Object handle */ 434 __u32 handle; 435 /** Do we want get or set metadata */ 436 __u32 op; 437 struct { 438 /** For future use, no flags defined so far */ 439 __u64 flags; 440 /** family specific tiling info */ 441 __u64 tiling_info; 442 __u32 data_size_bytes; 443 __u32 data[64]; 444 } data; 445 }; 446 447 struct drm_amdgpu_gem_mmap_in { 448 /** the GEM object handle */ 449 __u32 handle; 450 __u32 _pad; 451 }; 452 453 struct drm_amdgpu_gem_mmap_out { 454 /** mmap offset from the vma offset manager */ 455 __u64 addr_ptr; 456 }; 457 458 union drm_amdgpu_gem_mmap { 459 struct drm_amdgpu_gem_mmap_in in; 460 struct drm_amdgpu_gem_mmap_out out; 461 }; 462 463 struct drm_amdgpu_gem_wait_idle_in { 464 /** GEM object handle */ 465 __u32 handle; 466 /** For future use, no flags defined so far */ 467 __u32 flags; 468 /** Absolute timeout to wait */ 469 __u64 timeout; 470 }; 471 472 struct drm_amdgpu_gem_wait_idle_out { 473 /** BO status: 0 - BO is idle, 1 - BO is busy */ 474 __u32 status; 475 /** Returned current memory domain */ 476 __u32 domain; 477 }; 478 479 union drm_amdgpu_gem_wait_idle { 480 struct drm_amdgpu_gem_wait_idle_in in; 481 struct drm_amdgpu_gem_wait_idle_out out; 482 }; 483 484 struct drm_amdgpu_wait_cs_in { 485 /* Command submission handle 486 * handle equals 0 means none to wait for 487 * handle equals ~0ull means wait for the latest sequence number 488 */ 489 __u64 handle; 490 /** Absolute timeout to wait */ 491 __u64 timeout; 492 __u32 ip_type; 493 __u32 ip_instance; 494 __u32 ring; 495 __u32 ctx_id; 496 }; 497 498 struct drm_amdgpu_wait_cs_out { 499 /** CS status: 0 - CS completed, 1 - CS still busy */ 500 __u64 status; 501 }; 502 503 union drm_amdgpu_wait_cs { 504 struct drm_amdgpu_wait_cs_in in; 505 struct drm_amdgpu_wait_cs_out out; 506 }; 507 508 struct drm_amdgpu_fence { 509 __u32 ctx_id; 510 __u32 ip_type; 511 __u32 ip_instance; 512 __u32 ring; 513 __u64 seq_no; 514 }; 515 516 struct drm_amdgpu_wait_fences_in { 517 /** This points to uint64_t * which points to fences */ 518 __u64 fences; 519 __u32 fence_count; 520 __u32 wait_all; 521 __u64 timeout_ns; 522 }; 523 524 struct drm_amdgpu_wait_fences_out { 525 __u32 status; 526 __u32 first_signaled; 527 }; 528 529 union drm_amdgpu_wait_fences { 530 struct drm_amdgpu_wait_fences_in in; 531 struct drm_amdgpu_wait_fences_out out; 532 }; 533 534 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 535 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 536 537 /* Sets or returns a value associated with a buffer. */ 538 struct drm_amdgpu_gem_op { 539 /** GEM object handle */ 540 __u32 handle; 541 /** AMDGPU_GEM_OP_* */ 542 __u32 op; 543 /** Input or return value */ 544 __u64 value; 545 }; 546 547 #define AMDGPU_VA_OP_MAP 1 548 #define AMDGPU_VA_OP_UNMAP 2 549 #define AMDGPU_VA_OP_CLEAR 3 550 #define AMDGPU_VA_OP_REPLACE 4 551 552 /* Delay the page table update till the next CS */ 553 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 554 555 /* Mapping flags */ 556 /* readable mapping */ 557 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 558 /* writable mapping */ 559 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 560 /* executable mapping, new for VI */ 561 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 562 /* partially resident texture */ 563 #define AMDGPU_VM_PAGE_PRT (1 << 4) 564 /* MTYPE flags use bit 5 to 8 */ 565 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 566 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 567 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 568 /* Use Non Coherent MTYPE instead of default MTYPE */ 569 #define AMDGPU_VM_MTYPE_NC (1 << 5) 570 /* Use Write Combine MTYPE instead of default MTYPE */ 571 #define AMDGPU_VM_MTYPE_WC (2 << 5) 572 /* Use Cache Coherent MTYPE instead of default MTYPE */ 573 #define AMDGPU_VM_MTYPE_CC (3 << 5) 574 /* Use UnCached MTYPE instead of default MTYPE */ 575 #define AMDGPU_VM_MTYPE_UC (4 << 5) 576 /* Use Read Write MTYPE instead of default MTYPE */ 577 #define AMDGPU_VM_MTYPE_RW (5 << 5) 578 /* don't allocate MALL */ 579 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 580 581 struct drm_amdgpu_gem_va { 582 /** GEM object handle */ 583 __u32 handle; 584 __u32 _pad; 585 /** AMDGPU_VA_OP_* */ 586 __u32 operation; 587 /** AMDGPU_VM_PAGE_* */ 588 __u32 flags; 589 /** va address to assign . Must be correctly aligned.*/ 590 __u64 va_address; 591 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 592 __u64 offset_in_bo; 593 /** Specify mapping size. Must be correctly aligned. */ 594 __u64 map_size; 595 }; 596 597 #define AMDGPU_HW_IP_GFX 0 598 #define AMDGPU_HW_IP_COMPUTE 1 599 #define AMDGPU_HW_IP_DMA 2 600 #define AMDGPU_HW_IP_UVD 3 601 #define AMDGPU_HW_IP_VCE 4 602 #define AMDGPU_HW_IP_UVD_ENC 5 603 #define AMDGPU_HW_IP_VCN_DEC 6 604 /* 605 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 606 * both encoding and decoding jobs. 607 */ 608 #define AMDGPU_HW_IP_VCN_ENC 7 609 #define AMDGPU_HW_IP_VCN_JPEG 8 610 #define AMDGPU_HW_IP_VPE 9 611 #define AMDGPU_HW_IP_NUM 10 612 613 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 614 615 #define AMDGPU_CHUNK_ID_IB 0x01 616 #define AMDGPU_CHUNK_ID_FENCE 0x02 617 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 618 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 619 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 620 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 621 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 622 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 623 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 624 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 625 626 struct drm_amdgpu_cs_chunk { 627 __u32 chunk_id; 628 __u32 length_dw; 629 __u64 chunk_data; 630 }; 631 632 struct drm_amdgpu_cs_in { 633 /** Rendering context id */ 634 __u32 ctx_id; 635 /** Handle of resource list associated with CS */ 636 __u32 bo_list_handle; 637 __u32 num_chunks; 638 __u32 flags; 639 /** this points to __u64 * which point to cs chunks */ 640 __u64 chunks; 641 }; 642 643 struct drm_amdgpu_cs_out { 644 __u64 handle; 645 }; 646 647 union drm_amdgpu_cs { 648 struct drm_amdgpu_cs_in in; 649 struct drm_amdgpu_cs_out out; 650 }; 651 652 /* Specify flags to be used for IB */ 653 654 /* This IB should be submitted to CE */ 655 #define AMDGPU_IB_FLAG_CE (1<<0) 656 657 /* Preamble flag, which means the IB could be dropped if no context switch */ 658 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 659 660 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 661 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 662 663 /* The IB fence should do the L2 writeback but not invalidate any shader 664 * caches (L2/vL1/sL1/I$). */ 665 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 666 667 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 668 * This will reset wave ID counters for the IB. 669 */ 670 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 671 672 /* Flag the IB as secure (TMZ) 673 */ 674 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 675 676 /* Tell KMD to flush and invalidate caches 677 */ 678 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 679 680 struct drm_amdgpu_cs_chunk_ib { 681 __u32 _pad; 682 /** AMDGPU_IB_FLAG_* */ 683 __u32 flags; 684 /** Virtual address to begin IB execution */ 685 __u64 va_start; 686 /** Size of submission */ 687 __u32 ib_bytes; 688 /** HW IP to submit to */ 689 __u32 ip_type; 690 /** HW IP index of the same type to submit to */ 691 __u32 ip_instance; 692 /** Ring index to submit to */ 693 __u32 ring; 694 }; 695 696 struct drm_amdgpu_cs_chunk_dep { 697 __u32 ip_type; 698 __u32 ip_instance; 699 __u32 ring; 700 __u32 ctx_id; 701 __u64 handle; 702 }; 703 704 struct drm_amdgpu_cs_chunk_fence { 705 __u32 handle; 706 __u32 offset; 707 }; 708 709 struct drm_amdgpu_cs_chunk_sem { 710 __u32 handle; 711 }; 712 713 struct drm_amdgpu_cs_chunk_syncobj { 714 __u32 handle; 715 __u32 flags; 716 __u64 point; 717 }; 718 719 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 720 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 721 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 722 723 union drm_amdgpu_fence_to_handle { 724 struct { 725 struct drm_amdgpu_fence fence; 726 __u32 what; 727 __u32 pad; 728 } in; 729 struct { 730 __u32 handle; 731 } out; 732 }; 733 734 struct drm_amdgpu_cs_chunk_data { 735 union { 736 struct drm_amdgpu_cs_chunk_ib ib_data; 737 struct drm_amdgpu_cs_chunk_fence fence_data; 738 }; 739 }; 740 741 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 742 743 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 744 __u64 shadow_va; 745 __u64 csa_va; 746 __u64 gds_va; 747 __u64 flags; 748 }; 749 750 /* 751 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 752 * 753 */ 754 #define AMDGPU_IDS_FLAGS_FUSION 0x1 755 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 756 #define AMDGPU_IDS_FLAGS_TMZ 0x4 757 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 758 759 /* indicate if acceleration can be working */ 760 #define AMDGPU_INFO_ACCEL_WORKING 0x00 761 /* get the crtc_id from the mode object id? */ 762 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 763 /* query hw IP info */ 764 #define AMDGPU_INFO_HW_IP_INFO 0x02 765 /* query hw IP instance count for the specified type */ 766 #define AMDGPU_INFO_HW_IP_COUNT 0x03 767 /* timestamp for GL_ARB_timer_query */ 768 #define AMDGPU_INFO_TIMESTAMP 0x05 769 /* Query the firmware version */ 770 #define AMDGPU_INFO_FW_VERSION 0x0e 771 /* Subquery id: Query VCE firmware version */ 772 #define AMDGPU_INFO_FW_VCE 0x1 773 /* Subquery id: Query UVD firmware version */ 774 #define AMDGPU_INFO_FW_UVD 0x2 775 /* Subquery id: Query GMC firmware version */ 776 #define AMDGPU_INFO_FW_GMC 0x03 777 /* Subquery id: Query GFX ME firmware version */ 778 #define AMDGPU_INFO_FW_GFX_ME 0x04 779 /* Subquery id: Query GFX PFP firmware version */ 780 #define AMDGPU_INFO_FW_GFX_PFP 0x05 781 /* Subquery id: Query GFX CE firmware version */ 782 #define AMDGPU_INFO_FW_GFX_CE 0x06 783 /* Subquery id: Query GFX RLC firmware version */ 784 #define AMDGPU_INFO_FW_GFX_RLC 0x07 785 /* Subquery id: Query GFX MEC firmware version */ 786 #define AMDGPU_INFO_FW_GFX_MEC 0x08 787 /* Subquery id: Query SMC firmware version */ 788 #define AMDGPU_INFO_FW_SMC 0x0a 789 /* Subquery id: Query SDMA firmware version */ 790 #define AMDGPU_INFO_FW_SDMA 0x0b 791 /* Subquery id: Query PSP SOS firmware version */ 792 #define AMDGPU_INFO_FW_SOS 0x0c 793 /* Subquery id: Query PSP ASD firmware version */ 794 #define AMDGPU_INFO_FW_ASD 0x0d 795 /* Subquery id: Query VCN firmware version */ 796 #define AMDGPU_INFO_FW_VCN 0x0e 797 /* Subquery id: Query GFX RLC SRLC firmware version */ 798 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 799 /* Subquery id: Query GFX RLC SRLG firmware version */ 800 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 801 /* Subquery id: Query GFX RLC SRLS firmware version */ 802 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 803 /* Subquery id: Query DMCU firmware version */ 804 #define AMDGPU_INFO_FW_DMCU 0x12 805 #define AMDGPU_INFO_FW_TA 0x13 806 /* Subquery id: Query DMCUB firmware version */ 807 #define AMDGPU_INFO_FW_DMCUB 0x14 808 /* Subquery id: Query TOC firmware version */ 809 #define AMDGPU_INFO_FW_TOC 0x15 810 /* Subquery id: Query CAP firmware version */ 811 #define AMDGPU_INFO_FW_CAP 0x16 812 /* Subquery id: Query GFX RLCP firmware version */ 813 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 814 /* Subquery id: Query GFX RLCV firmware version */ 815 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 816 /* Subquery id: Query MES_KIQ firmware version */ 817 #define AMDGPU_INFO_FW_MES_KIQ 0x19 818 /* Subquery id: Query MES firmware version */ 819 #define AMDGPU_INFO_FW_MES 0x1a 820 /* Subquery id: Query IMU firmware version */ 821 #define AMDGPU_INFO_FW_IMU 0x1b 822 /* Subquery id: Query VPE firmware version */ 823 #define AMDGPU_INFO_FW_VPE 0x1c 824 825 /* number of bytes moved for TTM migration */ 826 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 827 /* the used VRAM size */ 828 #define AMDGPU_INFO_VRAM_USAGE 0x10 829 /* the used GTT size */ 830 #define AMDGPU_INFO_GTT_USAGE 0x11 831 /* Information about GDS, etc. resource configuration */ 832 #define AMDGPU_INFO_GDS_CONFIG 0x13 833 /* Query information about VRAM and GTT domains */ 834 #define AMDGPU_INFO_VRAM_GTT 0x14 835 /* Query information about register in MMR address space*/ 836 #define AMDGPU_INFO_READ_MMR_REG 0x15 837 /* Query information about device: rev id, family, etc. */ 838 #define AMDGPU_INFO_DEV_INFO 0x16 839 /* visible vram usage */ 840 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 841 /* number of TTM buffer evictions */ 842 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 843 /* Query memory about VRAM and GTT domains */ 844 #define AMDGPU_INFO_MEMORY 0x19 845 /* Query vce clock table */ 846 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 847 /* Query vbios related information */ 848 #define AMDGPU_INFO_VBIOS 0x1B 849 /* Subquery id: Query vbios size */ 850 #define AMDGPU_INFO_VBIOS_SIZE 0x1 851 /* Subquery id: Query vbios image */ 852 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 853 /* Subquery id: Query vbios info */ 854 #define AMDGPU_INFO_VBIOS_INFO 0x3 855 /* Query UVD handles */ 856 #define AMDGPU_INFO_NUM_HANDLES 0x1C 857 /* Query sensor related information */ 858 #define AMDGPU_INFO_SENSOR 0x1D 859 /* Subquery id: Query GPU shader clock */ 860 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 861 /* Subquery id: Query GPU memory clock */ 862 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 863 /* Subquery id: Query GPU temperature */ 864 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 865 /* Subquery id: Query GPU load */ 866 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 867 /* Subquery id: Query average GPU power */ 868 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 869 /* Subquery id: Query northbridge voltage */ 870 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 871 /* Subquery id: Query graphics voltage */ 872 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 873 /* Subquery id: Query GPU stable pstate shader clock */ 874 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 875 /* Subquery id: Query GPU stable pstate memory clock */ 876 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 877 /* Subquery id: Query GPU peak pstate shader clock */ 878 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 879 /* Subquery id: Query GPU peak pstate memory clock */ 880 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 881 /* Subquery id: Query input GPU power */ 882 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 883 /* Number of VRAM page faults on CPU access. */ 884 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 885 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 886 /* query ras mask of enabled features*/ 887 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 888 /* RAS MASK: UMC (VRAM) */ 889 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 890 /* RAS MASK: SDMA */ 891 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 892 /* RAS MASK: GFX */ 893 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 894 /* RAS MASK: MMHUB */ 895 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 896 /* RAS MASK: ATHUB */ 897 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 898 /* RAS MASK: PCIE */ 899 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 900 /* RAS MASK: HDP */ 901 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 902 /* RAS MASK: XGMI */ 903 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 904 /* RAS MASK: DF */ 905 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 906 /* RAS MASK: SMN */ 907 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 908 /* RAS MASK: SEM */ 909 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 910 /* RAS MASK: MP0 */ 911 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 912 /* RAS MASK: MP1 */ 913 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 914 /* RAS MASK: FUSE */ 915 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 916 /* query video encode/decode caps */ 917 #define AMDGPU_INFO_VIDEO_CAPS 0x21 918 /* Subquery id: Decode */ 919 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 920 /* Subquery id: Encode */ 921 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 922 /* Query the max number of IBs per gang per submission */ 923 #define AMDGPU_INFO_MAX_IBS 0x22 924 /* query last page fault info */ 925 #define AMDGPU_INFO_GPUVM_FAULT 0x23 926 927 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 928 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 929 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 930 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 931 932 struct drm_amdgpu_query_fw { 933 /** AMDGPU_INFO_FW_* */ 934 __u32 fw_type; 935 /** 936 * Index of the IP if there are more IPs of 937 * the same type. 938 */ 939 __u32 ip_instance; 940 /** 941 * Index of the engine. Whether this is used depends 942 * on the firmware type. (e.g. MEC, SDMA) 943 */ 944 __u32 index; 945 __u32 _pad; 946 }; 947 948 /* Input structure for the INFO ioctl */ 949 struct drm_amdgpu_info { 950 /* Where the return value will be stored */ 951 __u64 return_pointer; 952 /* The size of the return value. Just like "size" in "snprintf", 953 * it limits how many bytes the kernel can write. */ 954 __u32 return_size; 955 /* The query request id. */ 956 __u32 query; 957 958 union { 959 struct { 960 __u32 id; 961 __u32 _pad; 962 } mode_crtc; 963 964 struct { 965 /** AMDGPU_HW_IP_* */ 966 __u32 type; 967 /** 968 * Index of the IP if there are more IPs of the same 969 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 970 */ 971 __u32 ip_instance; 972 } query_hw_ip; 973 974 struct { 975 __u32 dword_offset; 976 /** number of registers to read */ 977 __u32 count; 978 __u32 instance; 979 /** For future use, no flags defined so far */ 980 __u32 flags; 981 } read_mmr_reg; 982 983 struct drm_amdgpu_query_fw query_fw; 984 985 struct { 986 __u32 type; 987 __u32 offset; 988 } vbios_info; 989 990 struct { 991 __u32 type; 992 } sensor_info; 993 994 struct { 995 __u32 type; 996 } video_cap; 997 }; 998 }; 999 1000 struct drm_amdgpu_info_gds { 1001 /** GDS GFX partition size */ 1002 __u32 gds_gfx_partition_size; 1003 /** GDS compute partition size */ 1004 __u32 compute_partition_size; 1005 /** total GDS memory size */ 1006 __u32 gds_total_size; 1007 /** GWS size per GFX partition */ 1008 __u32 gws_per_gfx_partition; 1009 /** GSW size per compute partition */ 1010 __u32 gws_per_compute_partition; 1011 /** OA size per GFX partition */ 1012 __u32 oa_per_gfx_partition; 1013 /** OA size per compute partition */ 1014 __u32 oa_per_compute_partition; 1015 __u32 _pad; 1016 }; 1017 1018 struct drm_amdgpu_info_vram_gtt { 1019 __u64 vram_size; 1020 __u64 vram_cpu_accessible_size; 1021 __u64 gtt_size; 1022 }; 1023 1024 struct drm_amdgpu_heap_info { 1025 /** max. physical memory */ 1026 __u64 total_heap_size; 1027 1028 /** Theoretical max. available memory in the given heap */ 1029 __u64 usable_heap_size; 1030 1031 /** 1032 * Number of bytes allocated in the heap. This includes all processes 1033 * and private allocations in the kernel. It changes when new buffers 1034 * are allocated, freed, and moved. It cannot be larger than 1035 * heap_size. 1036 */ 1037 __u64 heap_usage; 1038 1039 /** 1040 * Theoretical possible max. size of buffer which 1041 * could be allocated in the given heap 1042 */ 1043 __u64 max_allocation; 1044 }; 1045 1046 struct drm_amdgpu_memory_info { 1047 struct drm_amdgpu_heap_info vram; 1048 struct drm_amdgpu_heap_info cpu_accessible_vram; 1049 struct drm_amdgpu_heap_info gtt; 1050 }; 1051 1052 struct drm_amdgpu_info_firmware { 1053 __u32 ver; 1054 __u32 feature; 1055 }; 1056 1057 struct drm_amdgpu_info_vbios { 1058 __u8 name[64]; 1059 __u8 vbios_pn[64]; 1060 __u32 version; 1061 __u32 pad; 1062 __u8 vbios_ver_str[32]; 1063 __u8 date[32]; 1064 }; 1065 1066 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 1067 #define AMDGPU_VRAM_TYPE_GDDR1 1 1068 #define AMDGPU_VRAM_TYPE_DDR2 2 1069 #define AMDGPU_VRAM_TYPE_GDDR3 3 1070 #define AMDGPU_VRAM_TYPE_GDDR4 4 1071 #define AMDGPU_VRAM_TYPE_GDDR5 5 1072 #define AMDGPU_VRAM_TYPE_HBM 6 1073 #define AMDGPU_VRAM_TYPE_DDR3 7 1074 #define AMDGPU_VRAM_TYPE_DDR4 8 1075 #define AMDGPU_VRAM_TYPE_GDDR6 9 1076 #define AMDGPU_VRAM_TYPE_DDR5 10 1077 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1078 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1079 1080 struct drm_amdgpu_info_device { 1081 /** PCI Device ID */ 1082 __u32 device_id; 1083 /** Internal chip revision: A0, A1, etc.) */ 1084 __u32 chip_rev; 1085 __u32 external_rev; 1086 /** Revision id in PCI Config space */ 1087 __u32 pci_rev; 1088 __u32 family; 1089 __u32 num_shader_engines; 1090 __u32 num_shader_arrays_per_engine; 1091 /* in KHz */ 1092 __u32 gpu_counter_freq; 1093 __u64 max_engine_clock; 1094 __u64 max_memory_clock; 1095 /* cu information */ 1096 __u32 cu_active_number; 1097 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1098 __u32 cu_ao_mask; 1099 __u32 cu_bitmap[4][4]; 1100 /** Render backend pipe mask. One render backend is CB+DB. */ 1101 __u32 enabled_rb_pipes_mask; 1102 __u32 num_rb_pipes; 1103 __u32 num_hw_gfx_contexts; 1104 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1105 __u32 pcie_gen; 1106 __u64 ids_flags; 1107 /** Starting virtual address for UMDs. */ 1108 __u64 virtual_address_offset; 1109 /** The maximum virtual address */ 1110 __u64 virtual_address_max; 1111 /** Required alignment of virtual addresses. */ 1112 __u32 virtual_address_alignment; 1113 /** Page table entry - fragment size */ 1114 __u32 pte_fragment_size; 1115 __u32 gart_page_size; 1116 /** constant engine ram size*/ 1117 __u32 ce_ram_size; 1118 /** video memory type info*/ 1119 __u32 vram_type; 1120 /** video memory bit width*/ 1121 __u32 vram_bit_width; 1122 /* vce harvesting instance */ 1123 __u32 vce_harvest_config; 1124 /* gfx double offchip LDS buffers */ 1125 __u32 gc_double_offchip_lds_buf; 1126 /* NGG Primitive Buffer */ 1127 __u64 prim_buf_gpu_addr; 1128 /* NGG Position Buffer */ 1129 __u64 pos_buf_gpu_addr; 1130 /* NGG Control Sideband */ 1131 __u64 cntl_sb_buf_gpu_addr; 1132 /* NGG Parameter Cache */ 1133 __u64 param_buf_gpu_addr; 1134 __u32 prim_buf_size; 1135 __u32 pos_buf_size; 1136 __u32 cntl_sb_buf_size; 1137 __u32 param_buf_size; 1138 /* wavefront size*/ 1139 __u32 wave_front_size; 1140 /* shader visible vgprs*/ 1141 __u32 num_shader_visible_vgprs; 1142 /* CU per shader array*/ 1143 __u32 num_cu_per_sh; 1144 /* number of tcc blocks*/ 1145 __u32 num_tcc_blocks; 1146 /* gs vgt table depth*/ 1147 __u32 gs_vgt_table_depth; 1148 /* gs primitive buffer depth*/ 1149 __u32 gs_prim_buffer_depth; 1150 /* max gs wavefront per vgt*/ 1151 __u32 max_gs_waves_per_vgt; 1152 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1153 __u32 pcie_num_lanes; 1154 /* always on cu bitmap */ 1155 __u32 cu_ao_bitmap[4][4]; 1156 /** Starting high virtual address for UMDs. */ 1157 __u64 high_va_offset; 1158 /** The maximum high virtual address */ 1159 __u64 high_va_max; 1160 /* gfx10 pa_sc_tile_steering_override */ 1161 __u32 pa_sc_tile_steering_override; 1162 /* disabled TCCs */ 1163 __u64 tcc_disabled_mask; 1164 __u64 min_engine_clock; 1165 __u64 min_memory_clock; 1166 /* The following fields are only set on gfx11+, older chips set 0. */ 1167 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1168 __u32 num_sqc_per_wgp; 1169 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1170 __u32 sqc_inst_cache_size; 1171 __u32 gl1c_cache_size; 1172 __u32 gl2c_cache_size; 1173 __u64 mall_size; /* AKA infinity cache */ 1174 /* high 32 bits of the rb pipes mask */ 1175 __u32 enabled_rb_pipes_mask_hi; 1176 /* shadow area size for gfx11 */ 1177 __u32 shadow_size; 1178 /* shadow area base virtual alignment for gfx11 */ 1179 __u32 shadow_alignment; 1180 /* context save area size for gfx11 */ 1181 __u32 csa_size; 1182 /* context save area base virtual alignment for gfx11 */ 1183 __u32 csa_alignment; 1184 }; 1185 1186 struct drm_amdgpu_info_hw_ip { 1187 /** Version of h/w IP */ 1188 __u32 hw_ip_version_major; 1189 __u32 hw_ip_version_minor; 1190 /** Capabilities */ 1191 __u64 capabilities_flags; 1192 /** command buffer address start alignment*/ 1193 __u32 ib_start_alignment; 1194 /** command buffer size alignment*/ 1195 __u32 ib_size_alignment; 1196 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1197 __u32 available_rings; 1198 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1199 __u32 ip_discovery_version; 1200 }; 1201 1202 struct drm_amdgpu_info_num_handles { 1203 /** Max handles as supported by firmware for UVD */ 1204 __u32 uvd_max_handles; 1205 /** Handles currently in use for UVD */ 1206 __u32 uvd_used_handles; 1207 }; 1208 1209 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1210 1211 struct drm_amdgpu_info_vce_clock_table_entry { 1212 /** System clock */ 1213 __u32 sclk; 1214 /** Memory clock */ 1215 __u32 mclk; 1216 /** VCE clock */ 1217 __u32 eclk; 1218 __u32 pad; 1219 }; 1220 1221 struct drm_amdgpu_info_vce_clock_table { 1222 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1223 __u32 num_valid_entries; 1224 __u32 pad; 1225 }; 1226 1227 /* query video encode/decode caps */ 1228 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1229 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1230 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1231 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1232 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1233 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1234 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1235 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1236 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1237 1238 struct drm_amdgpu_info_video_codec_info { 1239 __u32 valid; 1240 __u32 max_width; 1241 __u32 max_height; 1242 __u32 max_pixels_per_frame; 1243 __u32 max_level; 1244 __u32 pad; 1245 }; 1246 1247 struct drm_amdgpu_info_video_caps { 1248 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1249 }; 1250 1251 #define AMDGPU_VMHUB_TYPE_MASK 0xff 1252 #define AMDGPU_VMHUB_TYPE_SHIFT 0 1253 #define AMDGPU_VMHUB_TYPE_GFX 0 1254 #define AMDGPU_VMHUB_TYPE_MM0 1 1255 #define AMDGPU_VMHUB_TYPE_MM1 2 1256 #define AMDGPU_VMHUB_IDX_MASK 0xff00 1257 #define AMDGPU_VMHUB_IDX_SHIFT 8 1258 1259 struct drm_amdgpu_info_gpuvm_fault { 1260 __u64 addr; 1261 __u32 status; 1262 __u32 vmhub; 1263 }; 1264 1265 /* 1266 * Supported GPU families 1267 */ 1268 #define AMDGPU_FAMILY_UNKNOWN 0 1269 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1270 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1271 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1272 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1273 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1274 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1275 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1276 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1277 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1278 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1279 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1280 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1281 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1282 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1283 #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ 1284 #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ 1285 1286 /* FIXME wrong namespace! */ 1287 struct drm_color_ctm_3x4 { 1288 /* 1289 * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude 1290 * (not two's complement!) format. 1291 */ 1292 __u64 matrix[12]; 1293 }; 1294 1295 #if defined(__cplusplus) 1296 } 1297 #endif 1298 1299 #endif 1300