1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 #define DRM_AMDGPU_USERQ 0x16 58 #define DRM_AMDGPU_USERQ_SIGNAL 0x17 59 #define DRM_AMDGPU_USERQ_WAIT 0x18 60 #define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 61 #define DRM_AMDGPU_PROC_OPTIONS 0x1A 62 #define DRM_AMDGPU_UALINK_HANDLE 0x1B 63 64 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 65 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 66 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 67 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 68 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 69 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 70 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 71 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 72 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 73 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 74 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 75 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 76 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 77 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 78 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 79 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 80 #define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) 81 #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) 82 #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) 83 #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles) 84 #define DRM_IOCTL_AMDGPU_PROC_OPTIONS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options) 85 #define DRM_IOCTL_AMDGPU_UALINK_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_UALINK_HANDLE, union drm_amdgpu_ualink_handle) 86 87 /** 88 * DOC: memory domains 89 * 90 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 91 * Memory in this pool could be swapped out to disk if there is pressure. 92 * 93 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 94 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 95 * pages of system memory, allows GPU access system memory in a linearized 96 * fashion. 97 * 98 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 99 * carved out by the BIOS. 100 * 101 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 102 * across shader threads. 103 * 104 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 105 * execution of all the waves on a device. 106 * 107 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 108 * for appending data. 109 * 110 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 111 * signalling user mode queues. 112 */ 113 #define AMDGPU_GEM_DOMAIN_CPU 0x1 114 #define AMDGPU_GEM_DOMAIN_GTT 0x2 115 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 116 #define AMDGPU_GEM_DOMAIN_GDS 0x8 117 #define AMDGPU_GEM_DOMAIN_GWS 0x10 118 #define AMDGPU_GEM_DOMAIN_OA 0x20 119 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 120 #define AMDGPU_GEM_DOMAIN_MMIO_REMAP 0x80 121 #define AMDGPU_GEM_DOMAIN_NPA 0x100 122 123 /* User-mode is not allowed to allocate NPA space. As a result, 124 * we don't add AMDGPU_GEM_DOMAIN_NPA in the DOMAIN_MASK below. 125 */ 126 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 127 AMDGPU_GEM_DOMAIN_GTT | \ 128 AMDGPU_GEM_DOMAIN_VRAM | \ 129 AMDGPU_GEM_DOMAIN_GDS | \ 130 AMDGPU_GEM_DOMAIN_GWS | \ 131 AMDGPU_GEM_DOMAIN_OA | \ 132 AMDGPU_GEM_DOMAIN_DOORBELL) 133 134 /* Flag that CPU access will be required for the case of VRAM domain */ 135 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 136 /* Flag that CPU access will not work, this VRAM domain is invisible */ 137 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 138 /* Flag that USWC attributes should be used for GTT */ 139 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 140 /* Flag that the memory should be in VRAM and cleared */ 141 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 142 /* Flag that allocating the BO should use linear VRAM */ 143 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 144 /* Flag that BO is always valid in this VM */ 145 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 146 /* Flag that BO sharing will be explicitly synchronized */ 147 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 148 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 149 * for the second page onward should be set to NC. It should never 150 * be used by user space applications. 151 */ 152 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 153 /* Flag that BO may contain sensitive data that must be wiped before 154 * releasing the memory 155 */ 156 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 157 /* Flag that BO will be encrypted and that the TMZ bit should be 158 * set in the PTEs when mapping this buffer via GPUVM or 159 * accessing it with various hw blocks 160 */ 161 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 162 /* Flag that BO will be used only in preemptible context, which does 163 * not require GTT memory accounting 164 */ 165 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 166 /* Flag that BO can be discarded under memory pressure without keeping the 167 * content. 168 */ 169 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 170 /* Flag that BO is shared coherently between multiple devices or CPU threads. 171 * May depend on GPU instructions to flush caches to system scope explicitly. 172 * 173 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 174 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 175 */ 176 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 177 /* Flag that BO should not be cached by GPU. Coherent without having to flush 178 * GPU caches explicitly 179 * 180 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 181 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 182 */ 183 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 184 /* Flag that BO should be coherent across devices when using device-level 185 * atomics. May depend on GPU instructions to flush caches to device scope 186 * explicitly, promoting them to system scope automatically. 187 * 188 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 189 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 190 */ 191 #define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 192 /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */ 193 #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) 194 195 struct drm_amdgpu_gem_create_in { 196 /** the requested memory size */ 197 __u64 bo_size; 198 /** physical start_addr alignment in bytes for some HW requirements */ 199 __u64 alignment; 200 /** the requested memory domains */ 201 __u64 domains; 202 /** allocation flags */ 203 __u64 domain_flags; 204 }; 205 206 struct drm_amdgpu_gem_create_out { 207 /** returned GEM object handle */ 208 __u32 handle; 209 __u32 _pad; 210 }; 211 212 union drm_amdgpu_gem_create { 213 struct drm_amdgpu_gem_create_in in; 214 struct drm_amdgpu_gem_create_out out; 215 }; 216 217 /** Opcode to create new residency list. */ 218 #define AMDGPU_BO_LIST_OP_CREATE 0 219 /** Opcode to destroy previously created residency list */ 220 #define AMDGPU_BO_LIST_OP_DESTROY 1 221 /** Opcode to update resource information in the list */ 222 #define AMDGPU_BO_LIST_OP_UPDATE 2 223 224 struct drm_amdgpu_bo_list_in { 225 /** Type of operation */ 226 __u32 operation; 227 /** Handle of list or 0 if we want to create one */ 228 __u32 list_handle; 229 /** Number of BOs in list */ 230 __u32 bo_number; 231 /** Size of each element describing BO */ 232 __u32 bo_info_size; 233 /** Pointer to array describing BOs */ 234 __u64 bo_info_ptr; 235 }; 236 237 struct drm_amdgpu_bo_list_entry { 238 /** Handle of BO */ 239 __u32 bo_handle; 240 /** New (if specified) BO priority to be used during migration */ 241 __u32 bo_priority; 242 }; 243 244 struct drm_amdgpu_bo_list_out { 245 /** Handle of resource list */ 246 __u32 list_handle; 247 __u32 _pad; 248 }; 249 250 union drm_amdgpu_bo_list { 251 struct drm_amdgpu_bo_list_in in; 252 struct drm_amdgpu_bo_list_out out; 253 }; 254 255 /* context related */ 256 #define AMDGPU_CTX_OP_ALLOC_CTX 1 257 #define AMDGPU_CTX_OP_FREE_CTX 2 258 #define AMDGPU_CTX_OP_QUERY_STATE 3 259 #define AMDGPU_CTX_OP_QUERY_STATE2 4 260 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 261 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 262 263 /* GPU reset status */ 264 #define AMDGPU_CTX_NO_RESET 0 265 /* this the context caused it */ 266 #define AMDGPU_CTX_GUILTY_RESET 1 267 /* some other context caused it */ 268 #define AMDGPU_CTX_INNOCENT_RESET 2 269 /* unknown cause */ 270 #define AMDGPU_CTX_UNKNOWN_RESET 3 271 272 /* indicate gpu reset occurred after ctx created */ 273 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 274 /* indicate vram lost occurred after ctx created */ 275 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 276 /* indicate some job from this context once cause gpu hang */ 277 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 278 /* indicate some errors are detected by RAS */ 279 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 280 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 281 /* indicate that the reset hasn't completed yet */ 282 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 283 284 /* Context priority level */ 285 #define AMDGPU_CTX_PRIORITY_UNSET -2048 286 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 287 #define AMDGPU_CTX_PRIORITY_LOW -512 288 #define AMDGPU_CTX_PRIORITY_NORMAL 0 289 /* 290 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 291 * CAP_SYS_NICE or DRM_MASTER 292 */ 293 #define AMDGPU_CTX_PRIORITY_HIGH 512 294 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 295 296 /* select a stable profiling pstate for perfmon tools */ 297 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 298 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 299 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 300 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 301 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 302 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 303 304 struct drm_amdgpu_ctx_in { 305 /** AMDGPU_CTX_OP_* */ 306 __u32 op; 307 /** Flags */ 308 __u32 flags; 309 __u32 ctx_id; 310 /** AMDGPU_CTX_PRIORITY_* */ 311 __s32 priority; 312 }; 313 314 union drm_amdgpu_ctx_out { 315 struct { 316 __u32 ctx_id; 317 __u32 _pad; 318 } alloc; 319 320 struct { 321 /** For future use, no flags defined so far */ 322 __u64 flags; 323 /** Number of resets caused by this context so far. */ 324 __u32 hangs; 325 /** Reset status since the last call of the ioctl. */ 326 __u32 reset_status; 327 } state; 328 329 struct { 330 __u32 flags; 331 __u32 _pad; 332 } pstate; 333 }; 334 335 union drm_amdgpu_ctx { 336 struct drm_amdgpu_ctx_in in; 337 union drm_amdgpu_ctx_out out; 338 }; 339 340 /* user queue IOCTL operations */ 341 #define AMDGPU_USERQ_OP_CREATE 1 342 #define AMDGPU_USERQ_OP_FREE 2 343 344 /* queue priority levels */ 345 /* low < normal low < normal high < high */ 346 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3 347 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0 348 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0 349 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1 350 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2 351 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */ 352 /* for queues that need access to protected content */ 353 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2) 354 355 /* 356 * This structure is a container to pass input configuration 357 * info for all supported userqueue related operations. 358 * For operation AMDGPU_USERQ_OP_CREATE: user is expected 359 * to set all fields, excep the parameter 'queue_id'. 360 * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected 361 * to be set is 'queue_id', eveything else is ignored. 362 */ 363 struct drm_amdgpu_userq_in { 364 /** AMDGPU_USERQ_OP_* */ 365 __u32 op; 366 /** Queue id passed for operation USERQ_OP_FREE */ 367 __u32 queue_id; 368 /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */ 369 __u32 ip_type; 370 /** 371 * @doorbell_handle: the handle of doorbell GEM object 372 * associated with this userqueue client. 373 */ 374 __u32 doorbell_handle; 375 /** 376 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo. 377 * Kernel will generate absolute doorbell offset using doorbell_handle 378 * and doorbell_offset in the doorbell bo. 379 */ 380 __u32 doorbell_offset; 381 /** 382 * @flags: flags used for queue parameters 383 */ 384 __u32 flags; 385 /** 386 * @queue_va: Virtual address of the GPU memory which holds the queue 387 * object. The queue holds the workload packets. 388 */ 389 __u64 queue_va; 390 /** 391 * @queue_size: Size of the queue in bytes, this needs to be 256-byte 392 * aligned. 393 */ 394 __u64 queue_size; 395 /** 396 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR. 397 * This object must be at least 8 byte in size and aligned to 8-byte offset. 398 */ 399 __u64 rptr_va; 400 /** 401 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR. 402 * This object must be at least 8 byte in size and aligned to 8-byte offset. 403 * 404 * Queue, RPTR and WPTR can come from the same object, as long as the size 405 * and alignment related requirements are met. 406 */ 407 __u64 wptr_va; 408 /** 409 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow 410 * the GPU to uniquely define and identify a usermode queue. 411 * 412 * MQD data can be of different size for different GPU IP/engine and 413 * their respective versions/revisions, so this points to a __u64 * 414 * which holds IP specific MQD of this usermode queue. 415 */ 416 __u64 mqd; 417 /** 418 * @size: size of MQD data in bytes, it must match the MQD structure 419 * size of the respective engine/revision defined in UAPI for ex, for 420 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11). 421 */ 422 __u64 mqd_size; 423 }; 424 425 /* The structure to carry output of userqueue ops */ 426 struct drm_amdgpu_userq_out { 427 /** 428 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique 429 * queue ID to represent the newly created userqueue in the system, otherwise 430 * it should be ignored. 431 */ 432 __u32 queue_id; 433 __u32 _pad; 434 }; 435 436 union drm_amdgpu_userq { 437 struct drm_amdgpu_userq_in in; 438 struct drm_amdgpu_userq_out out; 439 }; 440 441 /* GFX V11 IP specific MQD parameters */ 442 struct drm_amdgpu_userq_mqd_gfx11 { 443 /** 444 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer. 445 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 446 */ 447 __u64 shadow_va; 448 /** 449 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 450 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 451 */ 452 __u64 csa_va; 453 }; 454 455 /* GFX V11 SDMA IP specific MQD parameters */ 456 struct drm_amdgpu_userq_mqd_sdma_gfx11 { 457 /** 458 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 459 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 460 * to get the size. 461 */ 462 __u64 csa_va; 463 }; 464 465 /* GFX V11 Compute IP specific MQD parameters */ 466 struct drm_amdgpu_userq_mqd_compute_gfx11 { 467 /** 468 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer. 469 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 470 * to get the size. 471 */ 472 __u64 eop_va; 473 }; 474 475 /* userq signal/wait ioctl */ 476 struct drm_amdgpu_userq_signal { 477 /** 478 * @queue_id: Queue handle used by the userq fence creation function 479 * to retrieve the WPTR. 480 */ 481 __u32 queue_id; 482 __u32 pad; 483 /** 484 * @syncobj_handles: The list of syncobj handles submitted by the user queue 485 * job to be signaled. 486 */ 487 __u64 syncobj_handles; 488 /** 489 * @num_syncobj_handles: A count that represents the number of syncobj handles in 490 * @syncobj_handles. 491 */ 492 __u16 num_syncobj_handles; 493 __u16 pad0; 494 __u32 pad1; 495 /** 496 * @bo_read_handles: The list of BO handles that the submitted user queue job 497 * is using for read only. This will update BO fences in the kernel. 498 */ 499 __u64 bo_read_handles; 500 /** 501 * @bo_write_handles: The list of BO handles that the submitted user queue job 502 * is using for write only. This will update BO fences in the kernel. 503 */ 504 __u64 bo_write_handles; 505 /** 506 * @num_bo_read_handles: A count that represents the number of read BO handles in 507 * @bo_read_handles. 508 */ 509 __u32 num_bo_read_handles; 510 /** 511 * @num_bo_write_handles: A count that represents the number of write BO handles in 512 * @bo_write_handles. 513 */ 514 __u32 num_bo_write_handles; 515 /** 516 * @syncobj_points: The list of syncobj points submitted by the user queue job 517 * for the corresponding @syncobj_handles. 518 */ 519 __u64 syncobj_points; 520 }; 521 522 struct drm_amdgpu_userq_fence_info { 523 /** 524 * @va: A gpu address allocated for each queue which stores the 525 * read pointer (RPTR) value. 526 */ 527 __u64 va; 528 /** 529 * @value: A 64 bit value represents the write pointer (WPTR) of the 530 * queue commands which compared with the RPTR value to signal the 531 * fences. 532 */ 533 __u64 value; 534 }; 535 536 struct drm_amdgpu_userq_wait { 537 /** 538 * @waitq_id: Queue handle used by the userq wait IOCTL to retrieve the 539 * wait queue and maintain the fence driver references in it. 540 */ 541 __u32 waitq_id; 542 __u32 pad; 543 /** 544 * @syncobj_handles: The list of syncobj handles submitted by the user queue 545 * job to get the va/value pairs. 546 */ 547 __u64 syncobj_handles; 548 /** 549 * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by 550 * the user queue job to get the va/value pairs at given @syncobj_timeline_points. 551 */ 552 __u64 syncobj_timeline_handles; 553 /** 554 * @syncobj_timeline_points: The list of timeline syncobj points submitted by the 555 * user queue job for the corresponding @syncobj_timeline_handles. 556 */ 557 __u64 syncobj_timeline_points; 558 /** 559 * @bo_read_handles: The list of read BO handles submitted by the user queue 560 * job to get the va/value pairs. 561 */ 562 __u64 bo_read_handles; 563 /** 564 * @bo_write_handles: The list of write BO handles submitted by the user queue 565 * job to get the va/value pairs. 566 */ 567 __u64 bo_write_handles; 568 /** 569 * @num_syncobj_timeline_handles: A count that represents the number of timeline 570 * syncobj handles in @syncobj_timeline_handles. 571 */ 572 __u16 num_syncobj_timeline_handles; 573 /** 574 * @num_fences: This field can be used both as input and output. As input it defines 575 * the maximum number of fences that can be returned and as output it will specify 576 * how many fences were actually returned from the ioctl. 577 */ 578 __u16 num_fences; 579 /** 580 * @num_syncobj_handles: A count that represents the number of syncobj handles in 581 * @syncobj_handles. 582 */ 583 __u16 num_syncobj_handles; 584 __u16 pad0; 585 /** 586 * @num_bo_read_handles: A count that represents the number of read BO handles in 587 * @bo_read_handles. 588 */ 589 __u32 num_bo_read_handles; 590 /** 591 * @num_bo_write_handles: A count that represents the number of write BO handles in 592 * @bo_write_handles. 593 */ 594 __u32 num_bo_write_handles; 595 /** 596 * @out_fences: The field is a return value from the ioctl containing the list of 597 * address/value pairs to wait for. 598 */ 599 __u64 out_fences; 600 }; 601 602 /* vm ioctl */ 603 #define AMDGPU_VM_OP_RESERVE_VMID 1 604 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 605 606 struct drm_amdgpu_vm_in { 607 /** AMDGPU_VM_OP_* */ 608 __u32 op; 609 __u32 flags; 610 }; 611 612 struct drm_amdgpu_vm_out { 613 /** For future use, no flags defined so far */ 614 __u64 flags; 615 }; 616 617 union drm_amdgpu_vm { 618 struct drm_amdgpu_vm_in in; 619 struct drm_amdgpu_vm_out out; 620 }; 621 622 /* sched ioctl */ 623 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 624 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 625 626 struct drm_amdgpu_sched_in { 627 /* AMDGPU_SCHED_OP_* */ 628 __u32 op; 629 __u32 fd; 630 /** AMDGPU_CTX_PRIORITY_* */ 631 __s32 priority; 632 __u32 ctx_id; 633 }; 634 635 union drm_amdgpu_sched { 636 struct drm_amdgpu_sched_in in; 637 }; 638 639 /* 640 * This is not a reliable API and you should expect it to fail for any 641 * number of reasons and have fallback path that do not use userptr to 642 * perform any operation. 643 */ 644 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 645 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 646 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 647 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 648 649 struct drm_amdgpu_gem_userptr { 650 __u64 addr; 651 __u64 size; 652 /* AMDGPU_GEM_USERPTR_* */ 653 __u32 flags; 654 /* Resulting GEM handle */ 655 __u32 handle; 656 }; 657 658 /* SI-CI-VI: */ 659 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 660 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 661 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 662 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 663 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 664 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 665 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 666 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 667 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 668 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 669 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 670 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 671 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 672 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 673 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 674 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 675 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 676 677 /* GFX9 - GFX11: */ 678 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 679 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 680 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 681 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 682 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 683 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 684 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 685 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 686 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 687 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 688 #define AMDGPU_TILING_SCANOUT_SHIFT 63 689 #define AMDGPU_TILING_SCANOUT_MASK 0x1 690 691 /* GFX12 and later: */ 692 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 693 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 694 /* These are DCC recompression settings for memory management: */ 695 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 696 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ 697 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 698 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ 699 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 700 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 701 /* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata 702 * to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */ 703 #define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14 704 #define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1 705 /* bit gap */ 706 #define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63 707 #define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1 708 709 /* Set/Get helpers for tiling flags. */ 710 #define AMDGPU_TILING_SET(field, value) \ 711 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 712 #define AMDGPU_TILING_GET(value, field) \ 713 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 714 715 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 716 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 717 718 /** The same structure is shared for input/output */ 719 struct drm_amdgpu_gem_metadata { 720 /** GEM Object handle */ 721 __u32 handle; 722 /** Do we want get or set metadata */ 723 __u32 op; 724 struct { 725 /** For future use, no flags defined so far */ 726 __u64 flags; 727 /** family specific tiling info */ 728 __u64 tiling_info; 729 __u32 data_size_bytes; 730 __u32 data[64]; 731 } data; 732 }; 733 734 struct drm_amdgpu_gem_mmap_in { 735 /** the GEM object handle */ 736 __u32 handle; 737 __u32 _pad; 738 }; 739 740 struct drm_amdgpu_gem_mmap_out { 741 /** mmap offset from the vma offset manager */ 742 __u64 addr_ptr; 743 }; 744 745 union drm_amdgpu_gem_mmap { 746 struct drm_amdgpu_gem_mmap_in in; 747 struct drm_amdgpu_gem_mmap_out out; 748 }; 749 750 struct drm_amdgpu_gem_wait_idle_in { 751 /** GEM object handle */ 752 __u32 handle; 753 /** For future use, no flags defined so far */ 754 __u32 flags; 755 /** Absolute timeout to wait */ 756 __u64 timeout; 757 }; 758 759 struct drm_amdgpu_gem_wait_idle_out { 760 /** BO status: 0 - BO is idle, 1 - BO is busy */ 761 __u32 status; 762 /** Returned current memory domain */ 763 __u32 domain; 764 }; 765 766 union drm_amdgpu_gem_wait_idle { 767 struct drm_amdgpu_gem_wait_idle_in in; 768 struct drm_amdgpu_gem_wait_idle_out out; 769 }; 770 771 struct drm_amdgpu_wait_cs_in { 772 /* Command submission handle 773 * handle equals 0 means none to wait for 774 * handle equals ~0ull means wait for the latest sequence number 775 */ 776 __u64 handle; 777 /** Absolute timeout to wait */ 778 __u64 timeout; 779 __u32 ip_type; 780 __u32 ip_instance; 781 __u32 ring; 782 __u32 ctx_id; 783 }; 784 785 struct drm_amdgpu_wait_cs_out { 786 /** CS status: 0 - CS completed, 1 - CS still busy */ 787 __u64 status; 788 }; 789 790 union drm_amdgpu_wait_cs { 791 struct drm_amdgpu_wait_cs_in in; 792 struct drm_amdgpu_wait_cs_out out; 793 }; 794 795 struct drm_amdgpu_fence { 796 __u32 ctx_id; 797 __u32 ip_type; 798 __u32 ip_instance; 799 __u32 ring; 800 __u64 seq_no; 801 }; 802 803 struct drm_amdgpu_wait_fences_in { 804 /** This points to uint64_t * which points to fences */ 805 __u64 fences; 806 __u32 fence_count; 807 __u32 wait_all; 808 __u64 timeout_ns; 809 }; 810 811 struct drm_amdgpu_wait_fences_out { 812 __u32 status; 813 __u32 first_signaled; 814 }; 815 816 union drm_amdgpu_wait_fences { 817 struct drm_amdgpu_wait_fences_in in; 818 struct drm_amdgpu_wait_fences_out out; 819 }; 820 821 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 822 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 823 #define AMDGPU_GEM_OP_GET_MAPPING_INFO 2 824 825 struct drm_amdgpu_gem_vm_entry { 826 /* Start of mapping (in bytes) */ 827 __u64 addr; 828 829 /* Size of mapping (in bytes) */ 830 __u64 size; 831 832 /* Mapping offset */ 833 __u64 offset; 834 835 /* flags needed to recreate mapping */ 836 __u64 flags; 837 }; 838 839 /* Sets or returns a value associated with a buffer. */ 840 struct drm_amdgpu_gem_op { 841 /** GEM object handle */ 842 __u32 handle; 843 /** AMDGPU_GEM_OP_* */ 844 __u32 op; 845 /** Input or return value. For MAPPING_INFO op: pointer to array of struct drm_amdgpu_gem_vm_entry */ 846 __u64 value; 847 /** For MAPPING_INFO op: number of mappings (in/out) */ 848 __u32 num_entries; 849 850 __u32 padding; 851 }; 852 853 #define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT (1 << 0) 854 855 struct drm_amdgpu_gem_list_handles { 856 /* User pointer to array of drm_amdgpu_gem_bo_info_entry */ 857 __u64 entries; 858 859 /* Size of entries buffer / Number of handles in process (if larger than size of buffer, must retry) */ 860 __u32 num_entries; 861 862 __u32 padding; 863 }; 864 865 struct drm_amdgpu_gem_list_handles_entry { 866 /* gem handle of buffer object */ 867 __u32 gem_handle; 868 869 /* Currently just one flag: IS_IMPORT */ 870 __u32 flags; 871 872 /* Size of bo */ 873 __u64 size; 874 875 /* Preferred domains for GEM_CREATE */ 876 __u64 preferred_domains; 877 878 /* GEM_CREATE flags for re-creation of buffer */ 879 __u64 alloc_flags; 880 881 /* physical start_addr alignment in bytes for some HW requirements */ 882 __u64 alignment; 883 }; 884 885 #define AMDGPU_VA_OP_MAP 1 886 #define AMDGPU_VA_OP_UNMAP 2 887 #define AMDGPU_VA_OP_CLEAR 3 888 #define AMDGPU_VA_OP_REPLACE 4 889 890 /* Delay the page table update till the next CS */ 891 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 892 893 /* Mapping flags */ 894 /* readable mapping */ 895 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 896 /* writable mapping */ 897 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 898 /* executable mapping, new for VI */ 899 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 900 /* unmapped page of partially resident textures */ 901 #define AMDGPU_VM_PAGE_PRT (1 << 4) 902 /* MTYPE flags use bit 5 to 8 */ 903 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 904 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 905 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 906 /* Use Non Coherent MTYPE instead of default MTYPE */ 907 #define AMDGPU_VM_MTYPE_NC (1 << 5) 908 /* Use Write Combine MTYPE instead of default MTYPE */ 909 #define AMDGPU_VM_MTYPE_WC (2 << 5) 910 /* Use Cache Coherent MTYPE instead of default MTYPE */ 911 #define AMDGPU_VM_MTYPE_CC (3 << 5) 912 /* Use UnCached MTYPE instead of default MTYPE */ 913 #define AMDGPU_VM_MTYPE_UC (4 << 5) 914 /* Use Read Write MTYPE instead of default MTYPE */ 915 #define AMDGPU_VM_MTYPE_RW (5 << 5) 916 /* don't allocate MALL */ 917 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 918 919 struct drm_amdgpu_gem_va { 920 /** GEM object handle */ 921 __u32 handle; 922 __u32 _pad; 923 /** AMDGPU_VA_OP_* */ 924 __u32 operation; 925 /** AMDGPU_VM_PAGE_* */ 926 __u32 flags; 927 /** va address to assign . Must be correctly aligned.*/ 928 __u64 va_address; 929 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 930 __u64 offset_in_bo; 931 /** Specify mapping size. Must be correctly aligned. */ 932 __u64 map_size; 933 /** 934 * vm_timeline_point is a sequence number used to add new timeline point. 935 */ 936 __u64 vm_timeline_point; 937 /** 938 * The vm page table update fence is installed in given vm_timeline_syncobj_out 939 * at vm_timeline_point. 940 */ 941 __u32 vm_timeline_syncobj_out; 942 /** the number of syncobj handles in @input_fence_syncobj_handles */ 943 __u32 num_syncobj_handles; 944 /** Array of sync object handle to wait for given input fences */ 945 __u64 input_fence_syncobj_handles; 946 }; 947 948 #define AMDGPU_HW_IP_GFX 0 949 #define AMDGPU_HW_IP_COMPUTE 1 950 #define AMDGPU_HW_IP_DMA 2 951 #define AMDGPU_HW_IP_UVD 3 952 #define AMDGPU_HW_IP_VCE 4 953 #define AMDGPU_HW_IP_UVD_ENC 5 954 #define AMDGPU_HW_IP_VCN_DEC 6 955 /* 956 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 957 * both encoding and decoding jobs. 958 */ 959 #define AMDGPU_HW_IP_VCN_ENC 7 960 #define AMDGPU_HW_IP_VCN_JPEG 8 961 #define AMDGPU_HW_IP_VPE 9 962 #define AMDGPU_HW_IP_NUM 10 963 964 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 965 966 #define AMDGPU_CHUNK_ID_IB 0x01 967 #define AMDGPU_CHUNK_ID_FENCE 0x02 968 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 969 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 970 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 971 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 972 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 973 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 974 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 975 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 976 977 struct drm_amdgpu_cs_chunk { 978 __u32 chunk_id; 979 __u32 length_dw; 980 __u64 chunk_data; 981 }; 982 983 struct drm_amdgpu_cs_in { 984 /** Rendering context id */ 985 __u32 ctx_id; 986 /** Handle of resource list associated with CS */ 987 __u32 bo_list_handle; 988 __u32 num_chunks; 989 __u32 flags; 990 /** this points to __u64 * which point to cs chunks */ 991 __u64 chunks; 992 }; 993 994 struct drm_amdgpu_cs_out { 995 __u64 handle; 996 }; 997 998 union drm_amdgpu_cs { 999 struct drm_amdgpu_cs_in in; 1000 struct drm_amdgpu_cs_out out; 1001 }; 1002 1003 /* Specify flags to be used for IB */ 1004 1005 /* This IB should be submitted to CE */ 1006 #define AMDGPU_IB_FLAG_CE (1<<0) 1007 1008 /* Preamble flag, which means the IB could be dropped if no context switch */ 1009 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 1010 1011 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 1012 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 1013 1014 /* The IB fence should do the L2 writeback but not invalidate any shader 1015 * caches (L2/vL1/sL1/I$). */ 1016 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 1017 1018 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 1019 * This will reset wave ID counters for the IB. 1020 */ 1021 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 1022 1023 /* Flag the IB as secure (TMZ) 1024 */ 1025 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 1026 1027 /* Tell KMD to flush and invalidate caches 1028 */ 1029 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 1030 1031 struct drm_amdgpu_cs_chunk_ib { 1032 __u32 _pad; 1033 /** AMDGPU_IB_FLAG_* */ 1034 __u32 flags; 1035 /** Virtual address to begin IB execution */ 1036 __u64 va_start; 1037 /** Size of submission */ 1038 __u32 ib_bytes; 1039 /** HW IP to submit to */ 1040 __u32 ip_type; 1041 /** HW IP index of the same type to submit to */ 1042 __u32 ip_instance; 1043 /** Ring index to submit to */ 1044 __u32 ring; 1045 }; 1046 1047 struct drm_amdgpu_cs_chunk_dep { 1048 __u32 ip_type; 1049 __u32 ip_instance; 1050 __u32 ring; 1051 __u32 ctx_id; 1052 __u64 handle; 1053 }; 1054 1055 struct drm_amdgpu_cs_chunk_fence { 1056 __u32 handle; 1057 __u32 offset; 1058 }; 1059 1060 struct drm_amdgpu_cs_chunk_sem { 1061 __u32 handle; 1062 }; 1063 1064 struct drm_amdgpu_cs_chunk_syncobj { 1065 __u32 handle; 1066 __u32 flags; 1067 __u64 point; 1068 }; 1069 1070 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 1071 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 1072 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 1073 1074 union drm_amdgpu_fence_to_handle { 1075 struct { 1076 struct drm_amdgpu_fence fence; 1077 __u32 what; 1078 __u32 pad; 1079 } in; 1080 struct { 1081 __u32 handle; 1082 } out; 1083 }; 1084 1085 struct drm_amdgpu_cs_chunk_data { 1086 union { 1087 struct drm_amdgpu_cs_chunk_ib ib_data; 1088 struct drm_amdgpu_cs_chunk_fence fence_data; 1089 }; 1090 }; 1091 1092 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 1093 1094 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 1095 __u64 shadow_va; 1096 __u64 csa_va; 1097 __u64 gds_va; 1098 __u64 flags; 1099 }; 1100 1101 /* 1102 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 1103 * 1104 */ 1105 #define AMDGPU_IDS_FLAGS_FUSION 0x01 1106 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x02 1107 #define AMDGPU_IDS_FLAGS_TMZ 0x04 1108 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x08 1109 #define AMDGPU_IDS_FLAGS_GANG_SUBMIT 0x10 1110 1111 /* 1112 * Query h/w info: Flag identifying VF/PF/PT mode 1113 * 1114 */ 1115 #define AMDGPU_IDS_FLAGS_MODE_MASK 0x300 1116 #define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8 1117 #define AMDGPU_IDS_FLAGS_MODE_PF 0x0 1118 #define AMDGPU_IDS_FLAGS_MODE_VF 0x1 1119 #define AMDGPU_IDS_FLAGS_MODE_PT 0x2 1120 1121 /* indicate if acceleration can be working */ 1122 #define AMDGPU_INFO_ACCEL_WORKING 0x00 1123 /* get the crtc_id from the mode object id? */ 1124 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 1125 /* query hw IP info */ 1126 #define AMDGPU_INFO_HW_IP_INFO 0x02 1127 /* query hw IP instance count for the specified type */ 1128 #define AMDGPU_INFO_HW_IP_COUNT 0x03 1129 /* timestamp for GL_ARB_timer_query */ 1130 #define AMDGPU_INFO_TIMESTAMP 0x05 1131 /* Query the firmware version */ 1132 #define AMDGPU_INFO_FW_VERSION 0x0e 1133 /* Subquery id: Query VCE firmware version */ 1134 #define AMDGPU_INFO_FW_VCE 0x1 1135 /* Subquery id: Query UVD firmware version */ 1136 #define AMDGPU_INFO_FW_UVD 0x2 1137 /* Subquery id: Query GMC firmware version */ 1138 #define AMDGPU_INFO_FW_GMC 0x03 1139 /* Subquery id: Query GFX ME firmware version */ 1140 #define AMDGPU_INFO_FW_GFX_ME 0x04 1141 /* Subquery id: Query GFX PFP firmware version */ 1142 #define AMDGPU_INFO_FW_GFX_PFP 0x05 1143 /* Subquery id: Query GFX CE firmware version */ 1144 #define AMDGPU_INFO_FW_GFX_CE 0x06 1145 /* Subquery id: Query GFX RLC firmware version */ 1146 #define AMDGPU_INFO_FW_GFX_RLC 0x07 1147 /* Subquery id: Query GFX MEC firmware version */ 1148 #define AMDGPU_INFO_FW_GFX_MEC 0x08 1149 /* Subquery id: Query SMC firmware version */ 1150 #define AMDGPU_INFO_FW_SMC 0x0a 1151 /* Subquery id: Query SDMA firmware version */ 1152 #define AMDGPU_INFO_FW_SDMA 0x0b 1153 /* Subquery id: Query PSP SOS firmware version */ 1154 #define AMDGPU_INFO_FW_SOS 0x0c 1155 /* Subquery id: Query PSP ASD firmware version */ 1156 #define AMDGPU_INFO_FW_ASD 0x0d 1157 /* Subquery id: Query VCN firmware version */ 1158 #define AMDGPU_INFO_FW_VCN 0x0e 1159 /* Subquery id: Query GFX RLC SRLC firmware version */ 1160 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 1161 /* Subquery id: Query GFX RLC SRLG firmware version */ 1162 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 1163 /* Subquery id: Query GFX RLC SRLS firmware version */ 1164 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 1165 /* Subquery id: Query DMCU firmware version */ 1166 #define AMDGPU_INFO_FW_DMCU 0x12 1167 #define AMDGPU_INFO_FW_TA 0x13 1168 /* Subquery id: Query DMCUB firmware version */ 1169 #define AMDGPU_INFO_FW_DMCUB 0x14 1170 /* Subquery id: Query TOC firmware version */ 1171 #define AMDGPU_INFO_FW_TOC 0x15 1172 /* Subquery id: Query CAP firmware version */ 1173 #define AMDGPU_INFO_FW_CAP 0x16 1174 /* Subquery id: Query GFX RLCP firmware version */ 1175 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 1176 /* Subquery id: Query GFX RLCV firmware version */ 1177 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 1178 /* Subquery id: Query MES_KIQ firmware version */ 1179 #define AMDGPU_INFO_FW_MES_KIQ 0x19 1180 /* Subquery id: Query MES firmware version */ 1181 #define AMDGPU_INFO_FW_MES 0x1a 1182 /* Subquery id: Query IMU firmware version */ 1183 #define AMDGPU_INFO_FW_IMU 0x1b 1184 /* Subquery id: Query VPE firmware version */ 1185 #define AMDGPU_INFO_FW_VPE 0x1c 1186 /* Subquery id: Query MP5 firmware version */ 1187 #define AMDGPU_INFO_FW_MP5 0x1d 1188 1189 /* number of bytes moved for TTM migration */ 1190 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 1191 /* the used VRAM size */ 1192 #define AMDGPU_INFO_VRAM_USAGE 0x10 1193 /* the used GTT size */ 1194 #define AMDGPU_INFO_GTT_USAGE 0x11 1195 /* Information about GDS, etc. resource configuration */ 1196 #define AMDGPU_INFO_GDS_CONFIG 0x13 1197 /* Query information about VRAM and GTT domains */ 1198 #define AMDGPU_INFO_VRAM_GTT 0x14 1199 /* Query information about register in MMR address space*/ 1200 #define AMDGPU_INFO_READ_MMR_REG 0x15 1201 /* Query information about device: rev id, family, etc. */ 1202 #define AMDGPU_INFO_DEV_INFO 0x16 1203 /* visible vram usage */ 1204 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 1205 /* number of TTM buffer evictions */ 1206 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 1207 /* Query memory about VRAM and GTT domains */ 1208 #define AMDGPU_INFO_MEMORY 0x19 1209 /* Query vce clock table */ 1210 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 1211 /* Query vbios related information */ 1212 #define AMDGPU_INFO_VBIOS 0x1B 1213 /* Subquery id: Query vbios size */ 1214 #define AMDGPU_INFO_VBIOS_SIZE 0x1 1215 /* Subquery id: Query vbios image */ 1216 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 1217 /* Subquery id: Query vbios info */ 1218 #define AMDGPU_INFO_VBIOS_INFO 0x3 1219 /* Query UVD handles */ 1220 #define AMDGPU_INFO_NUM_HANDLES 0x1C 1221 /* Query sensor related information */ 1222 #define AMDGPU_INFO_SENSOR 0x1D 1223 /* Subquery id: Query GPU shader clock */ 1224 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 1225 /* Subquery id: Query GPU memory clock */ 1226 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 1227 /* Subquery id: Query GPU temperature */ 1228 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 1229 /* Subquery id: Query GPU load */ 1230 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 1231 /* Subquery id: Query average GPU power */ 1232 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 1233 /* Subquery id: Query northbridge voltage */ 1234 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 1235 /* Subquery id: Query graphics voltage */ 1236 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 1237 /* Subquery id: Query GPU stable pstate shader clock */ 1238 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 1239 /* Subquery id: Query GPU stable pstate memory clock */ 1240 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 1241 /* Subquery id: Query GPU peak pstate shader clock */ 1242 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 1243 /* Subquery id: Query GPU peak pstate memory clock */ 1244 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 1245 /* Subquery id: Query input GPU power */ 1246 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 1247 /* Number of VRAM page faults on CPU access. */ 1248 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 1249 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 1250 /* query ras mask of enabled features*/ 1251 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 1252 /* RAS MASK: UMC (VRAM) */ 1253 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 1254 /* RAS MASK: SDMA */ 1255 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 1256 /* RAS MASK: GFX */ 1257 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 1258 /* RAS MASK: MMHUB */ 1259 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 1260 /* RAS MASK: ATHUB */ 1261 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 1262 /* RAS MASK: PCIE */ 1263 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 1264 /* RAS MASK: HDP */ 1265 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 1266 /* RAS MASK: XGMI */ 1267 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 1268 /* RAS MASK: DF */ 1269 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 1270 /* RAS MASK: SMN */ 1271 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 1272 /* RAS MASK: SEM */ 1273 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 1274 /* RAS MASK: MP0 */ 1275 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 1276 /* RAS MASK: MP1 */ 1277 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 1278 /* RAS MASK: FUSE */ 1279 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 1280 /* query video encode/decode caps */ 1281 #define AMDGPU_INFO_VIDEO_CAPS 0x21 1282 /* Subquery id: Decode */ 1283 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 1284 /* Subquery id: Encode */ 1285 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 1286 /* Query the max number of IBs per gang per submission */ 1287 #define AMDGPU_INFO_MAX_IBS 0x22 1288 /* query last page fault info */ 1289 #define AMDGPU_INFO_GPUVM_FAULT 0x23 1290 /* query FW object size and alignment */ 1291 #define AMDGPU_INFO_UQ_FW_AREAS 0x24 1292 1293 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 1294 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 1295 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 1296 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 1297 1298 struct drm_amdgpu_query_fw { 1299 /** AMDGPU_INFO_FW_* */ 1300 __u32 fw_type; 1301 /** 1302 * Index of the IP if there are more IPs of 1303 * the same type. 1304 */ 1305 __u32 ip_instance; 1306 /** 1307 * Index of the engine. Whether this is used depends 1308 * on the firmware type. (e.g. MEC, SDMA) 1309 */ 1310 __u32 index; 1311 __u32 _pad; 1312 }; 1313 1314 /* Input structure for the INFO ioctl */ 1315 struct drm_amdgpu_info { 1316 /* Where the return value will be stored */ 1317 __u64 return_pointer; 1318 /* The size of the return value. Just like "size" in "snprintf", 1319 * it limits how many bytes the kernel can write. */ 1320 __u32 return_size; 1321 /* The query request id. */ 1322 __u32 query; 1323 1324 union { 1325 struct { 1326 __u32 id; 1327 __u32 _pad; 1328 } mode_crtc; 1329 1330 struct { 1331 /** AMDGPU_HW_IP_* */ 1332 __u32 type; 1333 /** 1334 * Index of the IP if there are more IPs of the same 1335 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 1336 */ 1337 __u32 ip_instance; 1338 } query_hw_ip; 1339 1340 struct { 1341 __u32 dword_offset; 1342 /** number of registers to read */ 1343 __u32 count; 1344 __u32 instance; 1345 /** For future use, no flags defined so far */ 1346 __u32 flags; 1347 } read_mmr_reg; 1348 1349 struct drm_amdgpu_query_fw query_fw; 1350 1351 struct { 1352 __u32 type; 1353 __u32 offset; 1354 } vbios_info; 1355 1356 struct { 1357 __u32 type; 1358 } sensor_info; 1359 1360 struct { 1361 __u32 type; 1362 } video_cap; 1363 }; 1364 }; 1365 1366 struct drm_amdgpu_info_gds { 1367 /** GDS GFX partition size */ 1368 __u32 gds_gfx_partition_size; 1369 /** GDS compute partition size */ 1370 __u32 compute_partition_size; 1371 /** total GDS memory size */ 1372 __u32 gds_total_size; 1373 /** GWS size per GFX partition */ 1374 __u32 gws_per_gfx_partition; 1375 /** GSW size per compute partition */ 1376 __u32 gws_per_compute_partition; 1377 /** OA size per GFX partition */ 1378 __u32 oa_per_gfx_partition; 1379 /** OA size per compute partition */ 1380 __u32 oa_per_compute_partition; 1381 __u32 _pad; 1382 }; 1383 1384 struct drm_amdgpu_info_vram_gtt { 1385 __u64 vram_size; 1386 __u64 vram_cpu_accessible_size; 1387 __u64 gtt_size; 1388 }; 1389 1390 struct drm_amdgpu_heap_info { 1391 /** max. physical memory */ 1392 __u64 total_heap_size; 1393 1394 /** Theoretical max. available memory in the given heap */ 1395 __u64 usable_heap_size; 1396 1397 /** 1398 * Number of bytes allocated in the heap. This includes all processes 1399 * and private allocations in the kernel. It changes when new buffers 1400 * are allocated, freed, and moved. It cannot be larger than 1401 * heap_size. 1402 */ 1403 __u64 heap_usage; 1404 1405 /** 1406 * Theoretical possible max. size of buffer which 1407 * could be allocated in the given heap 1408 */ 1409 __u64 max_allocation; 1410 }; 1411 1412 struct drm_amdgpu_memory_info { 1413 struct drm_amdgpu_heap_info vram; 1414 struct drm_amdgpu_heap_info cpu_accessible_vram; 1415 struct drm_amdgpu_heap_info gtt; 1416 }; 1417 1418 struct drm_amdgpu_info_firmware { 1419 __u32 ver; 1420 __u32 feature; 1421 }; 1422 1423 struct drm_amdgpu_info_vbios { 1424 __u8 name[64]; 1425 __u8 vbios_pn[64]; 1426 __u32 version; 1427 __u32 pad; 1428 __u8 vbios_ver_str[32]; 1429 __u8 date[32]; 1430 }; 1431 1432 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 1433 #define AMDGPU_VRAM_TYPE_GDDR1 1 1434 #define AMDGPU_VRAM_TYPE_DDR2 2 1435 #define AMDGPU_VRAM_TYPE_GDDR3 3 1436 #define AMDGPU_VRAM_TYPE_GDDR4 4 1437 #define AMDGPU_VRAM_TYPE_GDDR5 5 1438 #define AMDGPU_VRAM_TYPE_HBM 6 1439 #define AMDGPU_VRAM_TYPE_DDR3 7 1440 #define AMDGPU_VRAM_TYPE_DDR4 8 1441 #define AMDGPU_VRAM_TYPE_GDDR6 9 1442 #define AMDGPU_VRAM_TYPE_DDR5 10 1443 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1444 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1445 #define AMDGPU_VRAM_TYPE_HBM3E 13 1446 #define AMDGPU_VRAM_TYPE_HBM4 14 1447 1448 struct drm_amdgpu_info_device { 1449 /** PCI Device ID */ 1450 __u32 device_id; 1451 /** Internal chip revision: A0, A1, etc.) */ 1452 __u32 chip_rev; 1453 __u32 external_rev; 1454 /** Revision id in PCI Config space */ 1455 __u32 pci_rev; 1456 __u32 family; 1457 __u32 num_shader_engines; 1458 __u32 num_shader_arrays_per_engine; 1459 /* in KHz */ 1460 __u32 gpu_counter_freq; 1461 __u64 max_engine_clock; 1462 __u64 max_memory_clock; 1463 /* cu information */ 1464 __u32 cu_active_number; 1465 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1466 __u32 cu_ao_mask; 1467 __u32 cu_bitmap[4][4]; 1468 /** Render backend pipe mask. One render backend is CB+DB. */ 1469 __u32 enabled_rb_pipes_mask; 1470 __u32 num_rb_pipes; 1471 __u32 num_hw_gfx_contexts; 1472 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1473 __u32 pcie_gen; 1474 __u64 ids_flags; 1475 /** Starting virtual address for UMDs. */ 1476 __u64 virtual_address_offset; 1477 /** The maximum virtual address */ 1478 __u64 virtual_address_max; 1479 /** Required alignment of virtual addresses. */ 1480 __u32 virtual_address_alignment; 1481 /** Page table entry - fragment size */ 1482 __u32 pte_fragment_size; 1483 __u32 gart_page_size; 1484 /** constant engine ram size*/ 1485 __u32 ce_ram_size; 1486 /** video memory type info*/ 1487 __u32 vram_type; 1488 /** video memory bit width*/ 1489 __u32 vram_bit_width; 1490 /* vce harvesting instance */ 1491 __u32 vce_harvest_config; 1492 /* gfx double offchip LDS buffers */ 1493 __u32 gc_double_offchip_lds_buf; 1494 /* NGG Primitive Buffer */ 1495 __u64 prim_buf_gpu_addr; 1496 /* NGG Position Buffer */ 1497 __u64 pos_buf_gpu_addr; 1498 /* NGG Control Sideband */ 1499 __u64 cntl_sb_buf_gpu_addr; 1500 /* NGG Parameter Cache */ 1501 __u64 param_buf_gpu_addr; 1502 __u32 prim_buf_size; 1503 __u32 pos_buf_size; 1504 __u32 cntl_sb_buf_size; 1505 __u32 param_buf_size; 1506 /* wavefront size*/ 1507 __u32 wave_front_size; 1508 /* shader visible vgprs*/ 1509 __u32 num_shader_visible_vgprs; 1510 /* CU per shader array*/ 1511 __u32 num_cu_per_sh; 1512 /* number of tcc blocks*/ 1513 __u32 num_tcc_blocks; 1514 /* gs vgt table depth*/ 1515 __u32 gs_vgt_table_depth; 1516 /* gs primitive buffer depth*/ 1517 __u32 gs_prim_buffer_depth; 1518 /* max gs wavefront per vgt*/ 1519 __u32 max_gs_waves_per_vgt; 1520 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1521 __u32 pcie_num_lanes; 1522 /* always on cu bitmap */ 1523 __u32 cu_ao_bitmap[4][4]; 1524 /** Starting high virtual address for UMDs. */ 1525 __u64 high_va_offset; 1526 /** The maximum high virtual address */ 1527 __u64 high_va_max; 1528 /* gfx10 pa_sc_tile_steering_override */ 1529 __u32 pa_sc_tile_steering_override; 1530 __u32 pad; 1531 /* disabled TCCs */ 1532 __u64 tcc_disabled_mask; 1533 __u64 min_engine_clock; 1534 __u64 min_memory_clock; 1535 /* The following fields are only set on gfx11+, older chips set 0. */ 1536 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1537 __u32 num_sqc_per_wgp; 1538 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1539 __u32 sqc_inst_cache_size; 1540 __u32 gl1c_cache_size; 1541 __u32 gl2c_cache_size; 1542 __u64 mall_size; /* AKA infinity cache */ 1543 /* high 32 bits of the rb pipes mask */ 1544 __u32 enabled_rb_pipes_mask_hi; 1545 /* shadow area size for gfx11 */ 1546 __u32 shadow_size; 1547 /* shadow area base virtual alignment for gfx11 */ 1548 __u32 shadow_alignment; 1549 /* context save area size for gfx11 */ 1550 __u32 csa_size; 1551 /* context save area base virtual alignment for gfx11 */ 1552 __u32 csa_alignment; 1553 /* Userq IP mask (1 << AMDGPU_HW_IP_*) */ 1554 __u32 userq_ip_mask; 1555 }; 1556 1557 struct drm_amdgpu_info_hw_ip { 1558 /** Version of h/w IP */ 1559 __u32 hw_ip_version_major; 1560 __u32 hw_ip_version_minor; 1561 /** Capabilities */ 1562 __u64 capabilities_flags; 1563 /** command buffer address start alignment*/ 1564 __u32 ib_start_alignment; 1565 /** command buffer size alignment*/ 1566 __u32 ib_size_alignment; 1567 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1568 __u32 available_rings; 1569 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1570 __u32 ip_discovery_version; 1571 /* Userq available slots */ 1572 __u32 userq_num_slots; 1573 }; 1574 1575 struct drm_amdgpu_info_num_handles { 1576 /** Max handles as supported by firmware for UVD */ 1577 __u32 uvd_max_handles; 1578 /** Handles currently in use for UVD */ 1579 __u32 uvd_used_handles; 1580 }; 1581 1582 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1583 1584 struct drm_amdgpu_info_vce_clock_table_entry { 1585 /** System clock */ 1586 __u32 sclk; 1587 /** Memory clock */ 1588 __u32 mclk; 1589 /** VCE clock */ 1590 __u32 eclk; 1591 __u32 pad; 1592 }; 1593 1594 struct drm_amdgpu_info_vce_clock_table { 1595 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1596 __u32 num_valid_entries; 1597 __u32 pad; 1598 }; 1599 1600 /* query video encode/decode caps */ 1601 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1602 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1603 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1604 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1605 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1606 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1607 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1608 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1609 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1610 1611 struct drm_amdgpu_info_video_codec_info { 1612 __u32 valid; 1613 __u32 max_width; 1614 __u32 max_height; 1615 __u32 max_pixels_per_frame; 1616 __u32 max_level; 1617 __u32 pad; 1618 }; 1619 1620 struct drm_amdgpu_info_video_caps { 1621 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1622 }; 1623 1624 #define AMDGPU_VMHUB_TYPE_MASK 0xff 1625 #define AMDGPU_VMHUB_TYPE_SHIFT 0 1626 #define AMDGPU_VMHUB_TYPE_GFX 0 1627 #define AMDGPU_VMHUB_TYPE_MM0 1 1628 #define AMDGPU_VMHUB_TYPE_MM1 2 1629 #define AMDGPU_VMHUB_IDX_MASK 0xff00 1630 #define AMDGPU_VMHUB_IDX_SHIFT 8 1631 1632 struct drm_amdgpu_info_gpuvm_fault { 1633 __u64 addr; 1634 __u32 status; 1635 __u32 vmhub; 1636 }; 1637 1638 struct drm_amdgpu_info_uq_metadata_gfx { 1639 /* shadow area size for gfx11 */ 1640 __u32 shadow_size; 1641 /* shadow area base virtual alignment for gfx11 */ 1642 __u32 shadow_alignment; 1643 /* context save area size for gfx11 */ 1644 __u32 csa_size; 1645 /* context save area base virtual alignment for gfx11 */ 1646 __u32 csa_alignment; 1647 }; 1648 1649 struct drm_amdgpu_info_uq_metadata_compute { 1650 /* EOP size for gfx11 */ 1651 __u32 eop_size; 1652 /* EOP base virtual alignment for gfx11 */ 1653 __u32 eop_alignment; 1654 }; 1655 1656 struct drm_amdgpu_info_uq_metadata_sdma { 1657 /* context save area size for sdma6 */ 1658 __u32 csa_size; 1659 /* context save area base virtual alignment for sdma6 */ 1660 __u32 csa_alignment; 1661 }; 1662 1663 struct drm_amdgpu_info_uq_metadata { 1664 union { 1665 struct drm_amdgpu_info_uq_metadata_gfx gfx; 1666 struct drm_amdgpu_info_uq_metadata_compute compute; 1667 struct drm_amdgpu_info_uq_metadata_sdma sdma; 1668 }; 1669 }; 1670 1671 /* 1672 * Supported GPU families 1673 */ 1674 #define AMDGPU_FAMILY_UNKNOWN 0 1675 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1676 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1677 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1678 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1679 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1680 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1681 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1682 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1683 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1684 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1685 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1686 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1687 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1688 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1689 #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ 1690 #define AMDGPU_FAMILY_GC_11_5_4 154 /* GC 11.5.4 */ 1691 #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ 1692 1693 /* 1694 * Definition of user options 1695 * 1696 * option: AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY 1697 * 0: Disable sigbus delay - SIGBUS will be raised immediately 1698 * 0xFFFFFFFF: SIGBUS will not be raised 1699 * other: Set the sigbus delay in milliseconds 1700 */ 1701 #define AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY 0 1702 1703 #define AMDGPU_PROC_OPTIONS_KFD_SIGBUS_DELAY_DISABLED 0xFFFFFFFFu 1704 1705 struct drm_amdgpu_proc_options { 1706 __u32 op; 1707 struct { 1708 __u32 value; 1709 } kfd_sigbus_delay; 1710 }; 1711 1712 #define DRM_AMDGPU_UALINK_HANDLE_OP_EXPORT 0 1713 #define DRM_AMDGPU_UALINK_HANDLE_OP_IMPORT 1 1714 1715 struct drm_amdgpu_ualink_handle_in { 1716 /* Export or import */ 1717 __u32 op; 1718 /* For future use, no flags defined so far */ 1719 __u32 flags; 1720 union { 1721 /* GEM handle of the BO to export */ 1722 __u32 gem_handle; 1723 /* UALink handle to import */ 1724 __u64 import_ualink_handle[2]; 1725 }; 1726 }; 1727 1728 union drm_amdgpu_ualink_handle_out { 1729 /* Exported UALink handle */ 1730 __u64 export_ualink_handle[2]; 1731 /** DMABuf representing the imported UALink handle */ 1732 __u32 import_dmabuf_handle; 1733 }; 1734 1735 union drm_amdgpu_ualink_handle { 1736 struct drm_amdgpu_ualink_handle_in in; 1737 union drm_amdgpu_ualink_handle_out out; 1738 }; 1739 1740 #if defined(__cplusplus) 1741 } 1742 #endif 1743 1744 #endif 1745