1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef AMDGPU_MODE_H 31 #define AMDGPU_MODE_H 32 33 #include <drm/display/drm_dp_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_encoder.h> 36 #include <drm/drm_fixed.h> 37 #include <drm/drm_framebuffer.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 #include <linux/hrtimer.h> 42 #include "amdgpu_irq.h" 43 44 #include <drm/display/drm_dp_mst_helper.h> 45 #include "modules/inc/mod_freesync.h" 46 #include "amdgpu_dm_irq_params.h" 47 48 struct amdgpu_bo; 49 struct amdgpu_device; 50 struct amdgpu_encoder; 51 struct amdgpu_router; 52 struct amdgpu_hpd; 53 struct edid; 54 struct drm_edid; 55 56 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 57 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 58 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 59 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 60 61 #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base) 62 63 #define AMDGPU_MAX_HPD_PINS 6 64 #define AMDGPU_MAX_CRTCS 6 65 #define AMDGPU_MAX_PLANES 6 66 #define AMDGPU_MAX_AFMT_BLOCKS 9 67 68 enum amdgpu_rmx_type { 69 RMX_OFF, 70 RMX_FULL, 71 RMX_CENTER, 72 RMX_ASPECT 73 }; 74 75 enum amdgpu_underscan_type { 76 UNDERSCAN_OFF, 77 UNDERSCAN_ON, 78 UNDERSCAN_AUTO, 79 }; 80 81 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 82 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 83 84 enum amdgpu_hpd_id { 85 AMDGPU_HPD_1 = 0, 86 AMDGPU_HPD_2, 87 AMDGPU_HPD_3, 88 AMDGPU_HPD_4, 89 AMDGPU_HPD_5, 90 AMDGPU_HPD_6, 91 AMDGPU_HPD_NONE = 0xff, 92 }; 93 94 enum amdgpu_crtc_irq { 95 AMDGPU_CRTC_IRQ_VBLANK1 = 0, 96 AMDGPU_CRTC_IRQ_VBLANK2, 97 AMDGPU_CRTC_IRQ_VBLANK3, 98 AMDGPU_CRTC_IRQ_VBLANK4, 99 AMDGPU_CRTC_IRQ_VBLANK5, 100 AMDGPU_CRTC_IRQ_VBLANK6, 101 AMDGPU_CRTC_IRQ_VLINE1, 102 AMDGPU_CRTC_IRQ_VLINE2, 103 AMDGPU_CRTC_IRQ_VLINE3, 104 AMDGPU_CRTC_IRQ_VLINE4, 105 AMDGPU_CRTC_IRQ_VLINE5, 106 AMDGPU_CRTC_IRQ_VLINE6, 107 AMDGPU_CRTC_IRQ_NONE = 0xff 108 }; 109 110 enum amdgpu_pageflip_irq { 111 AMDGPU_PAGEFLIP_IRQ_D1 = 0, 112 AMDGPU_PAGEFLIP_IRQ_D2, 113 AMDGPU_PAGEFLIP_IRQ_D3, 114 AMDGPU_PAGEFLIP_IRQ_D4, 115 AMDGPU_PAGEFLIP_IRQ_D5, 116 AMDGPU_PAGEFLIP_IRQ_D6, 117 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 118 }; 119 120 enum amdgpu_flip_status { 121 AMDGPU_FLIP_NONE, 122 AMDGPU_FLIP_PENDING, 123 AMDGPU_FLIP_SUBMITTED 124 }; 125 126 #define AMDGPU_MAX_I2C_BUS 16 127 128 /* amdgpu gpio-based i2c 129 * 1. "mask" reg and bits 130 * grabs the gpio pins for software use 131 * 0=not held 1=held 132 * 2. "a" reg and bits 133 * output pin value 134 * 0=low 1=high 135 * 3. "en" reg and bits 136 * sets the pin direction 137 * 0=input 1=output 138 * 4. "y" reg and bits 139 * input pin value 140 * 0=low 1=high 141 */ 142 struct amdgpu_i2c_bus_rec { 143 bool valid; 144 /* id used by atom */ 145 uint8_t i2c_id; 146 /* id used by atom */ 147 enum amdgpu_hpd_id hpd; 148 /* can be used with hw i2c engine */ 149 bool hw_capable; 150 /* uses multi-media i2c engine */ 151 bool mm_i2c; 152 /* regs and bits */ 153 uint32_t mask_clk_reg; 154 uint32_t mask_data_reg; 155 uint32_t a_clk_reg; 156 uint32_t a_data_reg; 157 uint32_t en_clk_reg; 158 uint32_t en_data_reg; 159 uint32_t y_clk_reg; 160 uint32_t y_data_reg; 161 uint32_t mask_clk_mask; 162 uint32_t mask_data_mask; 163 uint32_t a_clk_mask; 164 uint32_t a_data_mask; 165 uint32_t en_clk_mask; 166 uint32_t en_data_mask; 167 uint32_t y_clk_mask; 168 uint32_t y_data_mask; 169 }; 170 171 #define AMDGPU_MAX_BIOS_CONNECTOR 16 172 173 /* pll flags */ 174 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 175 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 176 #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 177 #define AMDGPU_PLL_LEGACY (1 << 3) 178 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 179 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 180 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 181 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 182 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 183 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 184 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 185 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 186 #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 187 #define AMDGPU_PLL_IS_LCD (1 << 13) 188 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 189 190 struct amdgpu_pll { 191 /* reference frequency */ 192 uint32_t reference_freq; 193 194 /* fixed dividers */ 195 uint32_t reference_div; 196 uint32_t post_div; 197 198 /* pll in/out limits */ 199 uint32_t pll_in_min; 200 uint32_t pll_in_max; 201 uint32_t pll_out_min; 202 uint32_t pll_out_max; 203 uint32_t lcd_pll_out_min; 204 uint32_t lcd_pll_out_max; 205 uint32_t best_vco; 206 207 /* divider limits */ 208 uint32_t min_ref_div; 209 uint32_t max_ref_div; 210 uint32_t min_post_div; 211 uint32_t max_post_div; 212 uint32_t min_feedback_div; 213 uint32_t max_feedback_div; 214 uint32_t min_frac_feedback_div; 215 uint32_t max_frac_feedback_div; 216 217 /* flags for the current clock */ 218 uint32_t flags; 219 220 /* pll id */ 221 uint32_t id; 222 }; 223 224 struct amdgpu_i2c_chan { 225 struct i2c_adapter adapter; 226 struct drm_device *dev; 227 struct i2c_algo_bit_data bit; 228 struct amdgpu_i2c_bus_rec rec; 229 struct drm_dp_aux aux; 230 bool has_aux; 231 struct mutex mutex; 232 }; 233 234 struct amdgpu_afmt { 235 bool enabled; 236 int offset; 237 bool last_buffer_filled_status; 238 int id; 239 struct amdgpu_audio_pin *pin; 240 }; 241 242 /* 243 * Audio 244 */ 245 struct amdgpu_audio_pin { 246 int channels; 247 int rate; 248 int bits_per_sample; 249 u8 status_bits; 250 u8 category_code; 251 u32 offset; 252 bool connected; 253 u32 id; 254 }; 255 256 struct amdgpu_audio { 257 bool enabled; 258 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 259 int num_pins; 260 }; 261 262 struct amdgpu_display_funcs { 263 /* display watermarks */ 264 void (*bandwidth_update)(struct amdgpu_device *adev); 265 /* get frame count */ 266 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 267 /* set backlight level */ 268 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 269 u8 level); 270 /* get backlight level */ 271 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 272 /* hotplug detect */ 273 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 274 void (*hpd_set_polarity)(struct amdgpu_device *adev, 275 enum amdgpu_hpd_id hpd); 276 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 277 /* pageflipping */ 278 void (*page_flip)(struct amdgpu_device *adev, 279 int crtc_id, u64 crtc_base, bool async); 280 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 281 u32 *vbl, u32 *position); 282 /* display topology setup */ 283 void (*add_encoder)(struct amdgpu_device *adev, 284 uint32_t encoder_enum, 285 uint32_t supported_device, 286 u16 caps); 287 void (*add_connector)(struct amdgpu_device *adev, 288 uint32_t connector_id, 289 uint32_t supported_device, 290 int connector_type, 291 struct amdgpu_i2c_bus_rec *i2c_bus, 292 uint16_t connector_object_id, 293 struct amdgpu_hpd *hpd, 294 struct amdgpu_router *router); 295 296 297 }; 298 299 struct amdgpu_framebuffer { 300 struct drm_framebuffer base; 301 302 uint64_t tiling_flags; 303 bool tmz_surface; 304 bool gfx12_dcc; 305 306 /* caching for later use */ 307 uint64_t address; 308 }; 309 310 struct amdgpu_mode_info { 311 struct atom_context *atom_context; 312 struct card_info *atom_card_info; 313 bool mode_config_initialized; 314 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 315 struct drm_plane *planes[AMDGPU_MAX_PLANES]; 316 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 317 /* DVI-I properties */ 318 struct drm_property *coherent_mode_property; 319 /* DAC enable load detect */ 320 struct drm_property *load_detect_property; 321 /* underscan */ 322 struct drm_property *underscan_property; 323 struct drm_property *underscan_hborder_property; 324 struct drm_property *underscan_vborder_property; 325 /* audio */ 326 struct drm_property *audio_property; 327 /* FMT dithering */ 328 struct drm_property *dither_property; 329 /* hardcoded DFP edid from BIOS */ 330 const struct drm_edid *bios_hardcoded_edid; 331 332 /* firmware flags */ 333 u32 firmware_flags; 334 /* pointer to backlight encoder */ 335 struct amdgpu_encoder *bl_encoder; 336 u8 bl_level; /* saved backlight level */ 337 struct amdgpu_audio audio; /* audio stuff */ 338 int num_crtc; /* number of crtcs */ 339 int num_hpd; /* number of hpd pins */ 340 int num_dig; /* number of dig blocks */ 341 bool gpu_vm_support; /* supports display from GTT */ 342 int disp_priority; 343 const struct amdgpu_display_funcs *funcs; 344 const enum drm_plane_type *plane_type; 345 346 /* Driver-private color mgmt props */ 347 348 /* @plane_degamma_lut_property: Plane property to set a degamma LUT to 349 * convert encoded values to light linear values before sampling or 350 * blending. 351 */ 352 struct drm_property *plane_degamma_lut_property; 353 /* @plane_degamma_lut_size_property: Plane property to define the max 354 * size of degamma LUT as supported by the driver (read-only). 355 */ 356 struct drm_property *plane_degamma_lut_size_property; 357 /** 358 * @plane_degamma_tf_property: Plane pre-defined transfer function to 359 * to go from scanout/encoded values to linear values. 360 */ 361 struct drm_property *plane_degamma_tf_property; 362 /** 363 * @plane_hdr_mult_property: 364 */ 365 struct drm_property *plane_hdr_mult_property; 366 367 struct drm_property *plane_ctm_property; 368 /** 369 * @shaper_lut_property: Plane property to set pre-blending shaper LUT 370 * that converts color content before 3D LUT. If 371 * plane_shaper_tf_property != Identity TF, AMD color module will 372 * combine the user LUT values with pre-defined TF into the LUT 373 * parameters to be programmed. 374 */ 375 struct drm_property *plane_shaper_lut_property; 376 /** 377 * @shaper_lut_size_property: Plane property for the size of 378 * pre-blending shaper LUT as supported by the driver (read-only). 379 */ 380 struct drm_property *plane_shaper_lut_size_property; 381 /** 382 * @plane_shaper_tf_property: Plane property to set a predefined 383 * transfer function for pre-blending shaper (before applying 3D LUT) 384 * with or without LUT. There is no shaper ROM, but we can use AMD 385 * color modules to program LUT parameters from predefined TF (or 386 * from a combination of pre-defined TF and the custom 1D LUT). 387 */ 388 struct drm_property *plane_shaper_tf_property; 389 /** 390 * @plane_lut3d_property: Plane property for color transformation using 391 * a 3D LUT (pre-blending), a three-dimensional array where each 392 * element is an RGB triplet. Each dimension has the size of 393 * lut3d_size. The array contains samples from the approximated 394 * function. On AMD, values between samples are estimated by 395 * tetrahedral interpolation. The array is accessed with three indices, 396 * one for each input dimension (color channel), blue being the 397 * outermost dimension, red the innermost. 398 */ 399 struct drm_property *plane_lut3d_property; 400 /** 401 * @plane_degamma_lut_size_property: Plane property to define the max 402 * size of 3D LUT as supported by the driver (read-only). The max size 403 * is the max size of one dimension and, therefore, the max number of 404 * entries for 3D LUT array is the 3D LUT size cubed; 405 */ 406 struct drm_property *plane_lut3d_size_property; 407 /** 408 * @plane_blend_lut_property: Plane property for output gamma before 409 * blending. Userspace set a blend LUT to convert colors after 3D LUT 410 * conversion. It works as a post-3DLUT 1D LUT. With shaper LUT, they 411 * are sandwiching 3D LUT with two 1D LUT. If plane_blend_tf_property 412 * != Identity TF, AMD color module will combine the user LUT values 413 * with pre-defined TF into the LUT parameters to be programmed. 414 */ 415 struct drm_property *plane_blend_lut_property; 416 /** 417 * @plane_blend_lut_size_property: Plane property to define the max 418 * size of blend LUT as supported by the driver (read-only). 419 */ 420 struct drm_property *plane_blend_lut_size_property; 421 /** 422 * @plane_blend_tf_property: Plane property to set a predefined 423 * transfer function for pre-blending blend/out_gamma (after applying 424 * 3D LUT) with or without LUT. There is no blend ROM, but we can use 425 * AMD color modules to program LUT parameters from predefined TF (or 426 * from a combination of pre-defined TF and the custom 1D LUT). 427 */ 428 struct drm_property *plane_blend_tf_property; 429 /* @regamma_tf_property: Transfer function for CRTC regamma 430 * (post-blending). Possible values are defined by `enum 431 * amdgpu_transfer_function`. There is no regamma ROM, but we can use 432 * AMD color modules to program LUT parameters from predefined TF (or 433 * from a combination of pre-defined TF and the custom 1D LUT). 434 */ 435 struct drm_property *regamma_tf_property; 436 }; 437 438 #define AMDGPU_MAX_BL_LEVEL 0xFF 439 440 struct amdgpu_backlight_privdata { 441 struct amdgpu_encoder *encoder; 442 uint8_t negative; 443 }; 444 445 struct amdgpu_atom_ss { 446 uint16_t percentage; 447 uint16_t percentage_divider; 448 uint8_t type; 449 uint16_t step; 450 uint8_t delay; 451 uint8_t range; 452 uint8_t refdiv; 453 /* asic_ss */ 454 uint16_t rate; 455 uint16_t amount; 456 }; 457 458 struct amdgpu_crtc { 459 struct drm_crtc base; 460 int crtc_id; 461 bool enabled; 462 bool can_tile; 463 uint32_t crtc_offset; 464 struct drm_gem_object *cursor_bo; 465 uint64_t cursor_addr; 466 int cursor_x; 467 int cursor_y; 468 int cursor_hot_x; 469 int cursor_hot_y; 470 int cursor_width; 471 int cursor_height; 472 int max_cursor_width; 473 int max_cursor_height; 474 enum amdgpu_rmx_type rmx_type; 475 u8 h_border; 476 u8 v_border; 477 fixed20_12 vsc; 478 fixed20_12 hsc; 479 struct drm_display_mode native_mode; 480 u32 pll_id; 481 /* page flipping */ 482 struct amdgpu_flip_work *pflip_works; 483 enum amdgpu_flip_status pflip_status; 484 int deferred_flip_completion; 485 /* parameters access from DM IRQ handler */ 486 struct dm_irq_params dm_irq_params; 487 /* pll sharing */ 488 struct amdgpu_atom_ss ss; 489 bool ss_enabled; 490 u32 adjusted_clock; 491 int bpc; 492 u32 pll_reference_div; 493 u32 pll_post_div; 494 u32 pll_flags; 495 struct drm_encoder *encoder; 496 struct drm_connector *connector; 497 /* for dpm */ 498 u32 line_time; 499 u32 wm_low; 500 u32 wm_high; 501 u32 lb_vblank_lead_lines; 502 struct drm_display_mode hw_mode; 503 /* for virtual dce */ 504 struct hrtimer vblank_timer; 505 enum amdgpu_interrupt_state vsync_timer_enabled; 506 507 int otg_inst; 508 struct drm_pending_vblank_event *event; 509 510 bool wb_pending; 511 bool wb_enabled; 512 struct drm_writeback_connector *wb_conn; 513 }; 514 515 struct amdgpu_encoder_atom_dig { 516 bool linkb; 517 /* atom dig */ 518 bool coherent_mode; 519 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 520 /* atom lvds/edp */ 521 uint32_t lcd_misc; 522 uint16_t panel_pwr_delay; 523 uint32_t lcd_ss_id; 524 /* panel mode */ 525 struct drm_display_mode native_mode; 526 struct backlight_device *bl_dev; 527 int dpms_mode; 528 uint8_t backlight_level; 529 int panel_mode; 530 struct amdgpu_afmt *afmt; 531 }; 532 533 struct amdgpu_encoder { 534 struct drm_encoder base; 535 uint32_t encoder_enum; 536 uint32_t encoder_id; 537 uint32_t devices; 538 uint32_t active_device; 539 uint32_t flags; 540 uint32_t pixel_clock; 541 enum amdgpu_rmx_type rmx_type; 542 enum amdgpu_underscan_type underscan_type; 543 uint32_t underscan_hborder; 544 uint32_t underscan_vborder; 545 struct drm_display_mode native_mode; 546 void *enc_priv; 547 int audio_polling_active; 548 bool is_ext_encoder; 549 u16 caps; 550 }; 551 552 struct amdgpu_connector_atom_dig { 553 /* displayport */ 554 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 555 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 556 u8 dp_sink_type; 557 int dp_clock; 558 int dp_lane_count; 559 bool edp_on; 560 }; 561 562 struct amdgpu_gpio_rec { 563 bool valid; 564 u8 id; 565 u32 reg; 566 u32 mask; 567 u32 shift; 568 }; 569 570 struct amdgpu_hpd { 571 enum amdgpu_hpd_id hpd; 572 u8 plugged_state; 573 struct amdgpu_gpio_rec gpio; 574 }; 575 576 struct amdgpu_router { 577 u32 router_id; 578 struct amdgpu_i2c_bus_rec i2c_info; 579 u8 i2c_addr; 580 /* i2c mux */ 581 bool ddc_valid; 582 u8 ddc_mux_type; 583 u8 ddc_mux_control_pin; 584 u8 ddc_mux_state; 585 /* clock/data mux */ 586 bool cd_valid; 587 u8 cd_mux_type; 588 u8 cd_mux_control_pin; 589 u8 cd_mux_state; 590 }; 591 592 enum amdgpu_connector_audio { 593 AMDGPU_AUDIO_DISABLE = 0, 594 AMDGPU_AUDIO_ENABLE = 1, 595 AMDGPU_AUDIO_AUTO = 2 596 }; 597 598 enum amdgpu_connector_dither { 599 AMDGPU_FMT_DITHER_DISABLE = 0, 600 AMDGPU_FMT_DITHER_ENABLE = 1, 601 }; 602 603 struct amdgpu_dm_dp_aux { 604 struct drm_dp_aux aux; 605 struct ddc_service *ddc_service; 606 }; 607 608 struct amdgpu_i2c_adapter { 609 struct i2c_adapter base; 610 611 struct ddc_service *ddc_service; 612 }; 613 614 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 615 616 struct amdgpu_connector { 617 struct drm_connector base; 618 uint32_t connector_id; 619 uint32_t devices; 620 struct amdgpu_i2c_chan *ddc_bus; 621 /* some systems have an hdmi and vga port with a shared ddc line */ 622 bool shared_ddc; 623 bool use_digital; 624 /* we need to mind the EDID between detect 625 and get modes due to analog/digital/tvencoder */ 626 struct edid *edid; 627 void *con_priv; 628 bool dac_load_detect; 629 bool detected_by_load; /* if the connection status was determined by load */ 630 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ 631 uint16_t connector_object_id; 632 struct amdgpu_hpd hpd; 633 struct amdgpu_router router; 634 struct amdgpu_i2c_chan *router_bus; 635 enum amdgpu_connector_audio audio; 636 enum amdgpu_connector_dither dither; 637 unsigned pixelclock_for_modeset; 638 }; 639 640 /* TODO: start to use this struct and remove same field from base one */ 641 struct amdgpu_mst_connector { 642 struct amdgpu_connector base; 643 644 struct drm_dp_mst_topology_mgr mst_mgr; 645 struct amdgpu_dm_dp_aux dm_dp_aux; 646 struct drm_dp_mst_port *mst_output_port; 647 struct amdgpu_connector *mst_root; 648 bool is_mst_connector; 649 struct amdgpu_encoder *mst_encoder; 650 }; 651 652 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 653 ((em) == ATOM_ENCODER_MODE_DP_MST)) 654 655 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */ 656 #define DRM_SCANOUTPOS_VALID (1 << 0) 657 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 658 #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 659 #define USE_REAL_VBLANKSTART (1 << 30) 660 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 661 662 void amdgpu_link_encoder_connector(struct drm_device *dev); 663 664 struct drm_connector * 665 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 666 struct drm_connector * 667 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 668 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 669 u32 pixel_clock); 670 671 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 672 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 673 674 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 675 bool use_aux); 676 677 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 678 679 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 680 unsigned int pipe, unsigned int flags, int *vpos, 681 int *hpos, ktime_t *stime, ktime_t *etime, 682 const struct drm_display_mode *mode); 683 684 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 685 686 void amdgpu_enc_destroy(struct drm_encoder *encoder); 687 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 688 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 689 const struct drm_display_mode *mode, 690 struct drm_display_mode *adjusted_mode); 691 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 692 struct drm_display_mode *adjusted_mode); 693 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 694 695 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 696 bool in_vblank_irq, int *vpos, 697 int *hpos, ktime_t *stime, ktime_t *etime, 698 const struct drm_display_mode *mode); 699 700 /* amdgpu_display.c */ 701 void amdgpu_display_print_display_setup(struct drm_device *dev); 702 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); 703 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 704 struct drm_modeset_acquire_ctx *ctx); 705 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 706 struct drm_framebuffer *fb, 707 struct drm_pending_vblank_event *event, 708 uint32_t page_flip_flags, uint32_t target, 709 struct drm_modeset_acquire_ctx *ctx); 710 extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 711 712 #endif 713