1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "amdgpu_userq.h" 55 #include "amdgpu_userq_fence.h" 56 #include "../amdxcp/amdgpu_xcp_drv.h" 57 #include "amdgpu_ualink.h" 58 59 /* 60 * KMS wrapper. 61 * - 3.0.0 - initial driver 62 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 63 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 64 * at the end of IBs. 65 * - 3.3.0 - Add VM support for UVD on supported hardware. 66 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 67 * - 3.5.0 - Add support for new UVD_NO_OP register. 68 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 69 * - 3.7.0 - Add support for VCE clock list packet 70 * - 3.8.0 - Add support raster config init in the kernel 71 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 72 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 73 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 74 * - 3.12.0 - Add query for double offchip LDS buffers 75 * - 3.13.0 - Add PRT support 76 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 77 * - 3.15.0 - Export more gpu info for gfx9 78 * - 3.16.0 - Add reserved vmid support 79 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 80 * - 3.18.0 - Export gpu always on cu bitmap 81 * - 3.19.0 - Add support for UVD MJPEG decode 82 * - 3.20.0 - Add support for local BOs 83 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 84 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 85 * - 3.23.0 - Add query for VRAM lost counter 86 * - 3.24.0 - Add high priority compute support for gfx9 87 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 88 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 89 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 90 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 91 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 92 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 93 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 94 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 95 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 96 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 97 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 98 * - 3.36.0 - Allow reading more status registers on si/cik 99 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 100 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 101 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 102 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 103 * - 3.41.0 - Add video codec query 104 * - 3.42.0 - Add 16bpc fixed point display support 105 * - 3.43.0 - Add device hot plug/unplug support 106 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 107 * - 3.45.0 - Add context ioctl stable pstate interface 108 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 109 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 110 * - 3.48.0 - Add IP discovery version info to HW INFO 111 * - 3.49.0 - Add gang submit into CS IOCTL 112 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 113 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 114 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 115 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 116 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 117 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 118 * 3.53.0 - Support for GFX11 CP GFX shadowing 119 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 120 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 121 * - 3.56.0 - Update IB start address and size alignment for decode and encode 122 * - 3.57.0 - Compute tunneling on GFX10+ 123 * - 3.58.0 - Add GFX12 DCC support 124 * - 3.59.0 - Cleared VRAM 125 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 126 * - 3.61.0 - Contains fix for RV/PCO compute queues 127 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 128 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 129 * - 3.64.0 - Userq IP support query 130 * - 3.65.0 - Add userq syncobj timeline signaling support 131 */ 132 #define KMS_DRIVER_MAJOR 3 133 #define KMS_DRIVER_MINOR 65 134 #define KMS_DRIVER_PATCHLEVEL 0 135 136 /* 137 * amdgpu.debug module options. Are all disabled by default 138 */ 139 enum AMDGPU_DEBUG_MASK { 140 AMDGPU_DEBUG_VM = BIT(0), 141 AMDGPU_DEBUG_LARGEBAR = BIT(1), 142 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 143 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 144 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 145 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 146 AMDGPU_DEBUG_SMU_POOL = BIT(7), 147 AMDGPU_DEBUG_VM_USERPTR = BIT(8), 148 AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), 149 AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10), 150 AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU = BIT(11), 151 AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET = BIT(12), 152 AMDGPU_DEBUG_SDMA_RB_CMD = BIT(13), 153 }; 154 155 unsigned int amdgpu_vram_limit = UINT_MAX; 156 int amdgpu_vis_vram_limit; 157 int amdgpu_gart_size = -1; /* auto */ 158 int amdgpu_gtt_size = -1; /* auto */ 159 int amdgpu_moverate = -1; /* auto */ 160 int amdgpu_audio = -1; 161 int amdgpu_disp_priority; 162 int amdgpu_hw_i2c; 163 int amdgpu_pcie_gen2 = -1; 164 int amdgpu_msi = -1; 165 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 166 int amdgpu_dpm = -1; 167 int amdgpu_fw_load_type = -1; 168 int amdgpu_aspm = -1; 169 int amdgpu_runtime_pm = -1; 170 uint amdgpu_ip_block_mask = 0xffffffff; 171 int amdgpu_bapm = -1; 172 int amdgpu_deep_color; 173 int amdgpu_vm_size = -1; 174 int amdgpu_vm_fragment_size = -1; 175 int amdgpu_vm_block_size = -1; 176 int amdgpu_vm_fault_stop; 177 int amdgpu_vm_update_mode = -1; 178 int amdgpu_exp_hw_support; 179 int amdgpu_dc = -1; 180 int amdgpu_sched_jobs = 32; 181 int amdgpu_sched_hw_submission = 2; 182 uint amdgpu_pcie_gen_cap; 183 uint amdgpu_pcie_lane_cap; 184 u64 amdgpu_cg_mask = 0xffffffffffffffff; 185 uint amdgpu_pg_mask = 0xffffffff; 186 uint amdgpu_sdma_phase_quantum = 32; 187 char *amdgpu_disable_cu; 188 char *amdgpu_virtual_display; 189 int amdgpu_enforce_isolation = -1; 190 int amdgpu_modeset = -1; 191 int amdgpu_iommu_perfopt = -1; 192 193 /* Specifies the default granularity for SVM, used in buffer 194 * migration and restoration of backing memory when handling 195 * recoverable page faults. 196 * 197 * The value is given as log(numPages(buffer)); for a 2 MiB 198 * buffer it computes to be 9 199 */ 200 uint amdgpu_svm_default_granularity = 9; 201 202 /* 203 * OverDrive(bit 14) disabled by default 204 * GFX DCS(bit 19) disabled by default 205 */ 206 uint amdgpu_pp_feature_mask = 0xfff7bfff; 207 uint amdgpu_force_long_training; 208 int amdgpu_lbpw = -1; 209 int amdgpu_compute_multipipe = -1; 210 int amdgpu_gpu_recovery = -1; /* auto */ 211 int amdgpu_emu_mode; 212 uint amdgpu_smu_memory_pool_size; 213 int amdgpu_smu_pptable_id = -1; 214 /* 215 * FBC (bit 0) disabled by default 216 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 217 * - With this, for multiple monitors in sync(e.g. with the same model), 218 * mclk switching will be allowed. And the mclk will be not foced to the 219 * highest. That helps saving some idle power. 220 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 221 * PSR (bit 3) disabled by default 222 * EDP NO POWER SEQUENCING (bit 4) disabled by default 223 * FRL (bit 10) enabled by default 224 */ 225 uint amdgpu_dc_feature_mask = DC_MULTI_MON_PP_MCLK_SWITCH_MASK | DC_FRL_MASK; 226 uint amdgpu_dc_debug_mask; 227 uint amdgpu_dc_visual_confirm; 228 int amdgpu_async_gfx_ring = 1; 229 int amdgpu_mcbp = -1; 230 int amdgpu_discovery = -1; 231 int amdgpu_mes_log_enable; 232 int amdgpu_mes_dbgext_buffer_size; 233 int amdgpu_mes_dbgext_options = 1; 234 int amdgpu_uni_mes = 1; 235 int amdgpu_noretry = -1; 236 int amdgpu_force_asic_type = -1; 237 int amdgpu_tmz = -1; /* auto */ 238 uint amdgpu_freesync_vid_mode; 239 int amdgpu_reset_method = -1; /* auto */ 240 int amdgpu_num_kcq = -1; 241 int amdgpu_smartshift_bias; 242 int amdgpu_use_xgmi_p2p = 1; 243 int amdgpu_vcnfw_log; 244 int amdgpu_sg_display = -1; /* auto */ 245 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 246 int amdgpu_umsch_mm; 247 int amdgpu_seamless = -1; /* auto */ 248 uint amdgpu_debug_mask; 249 int amdgpu_agp = -1; /* auto */ 250 int amdgpu_wbrf = -1; 251 int amdgpu_damage_clips = -1; /* auto */ 252 int amdgpu_umsch_mm_fwlog; 253 int amdgpu_rebar = -1; /* auto */ 254 int amdgpu_user_queue = -1; 255 uint amdgpu_hdmi_hpd_debounce_delay_ms; 256 int amdgpu_ptl = -1; /* auto */ 257 258 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 259 "DRM_UT_CORE", 260 "DRM_UT_DRIVER", 261 "DRM_UT_KMS", 262 "DRM_UT_PRIME", 263 "DRM_UT_ATOMIC", 264 "DRM_UT_VBL", 265 "DRM_UT_STATE", 266 "DRM_UT_LEASE", 267 "DRM_UT_DP", 268 "DRM_UT_DRMRES"); 269 270 struct amdgpu_mgpu_info mgpu_info = { 271 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 272 }; 273 int amdgpu_ras_enable = -1; 274 u64 amdgpu_ras_mask = U64_MAX; 275 int amdgpu_bad_page_threshold = -1; 276 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 277 .timeout_fatal_disable = false, 278 .period = 0x0, /* default to 0x0 (timeout disable) */ 279 }; 280 281 /** 282 * DOC: vramlimit (int) 283 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 284 */ 285 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 286 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 287 288 /** 289 * DOC: vis_vramlimit (int) 290 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 291 */ 292 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 293 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 294 295 /** 296 * DOC: gartsize (uint) 297 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 298 * The default is -1 (The size depends on asic). 299 */ 300 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 301 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 302 303 /** 304 * DOC: gttsize (int) 305 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 306 * The default is -1 (Use value specified by TTM). 307 * This parameter is deprecated and will be removed in the future. 308 */ 309 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 310 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 311 312 /** 313 * DOC: moverate (int) 314 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 315 */ 316 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 317 module_param_named(moverate, amdgpu_moverate, int, 0600); 318 319 /** 320 * DOC: audio (int) 321 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 322 */ 323 MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)"); 324 module_param_named(audio, amdgpu_audio, int, 0444); 325 326 /** 327 * DOC: disp_priority (int) 328 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 329 */ 330 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 331 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 332 333 /** 334 * DOC: hw_i2c (int) 335 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 336 */ 337 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 338 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 339 340 /** 341 * DOC: pcie_gen2 (int) 342 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 343 */ 344 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 345 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 346 347 /** 348 * DOC: msi (int) 349 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 350 */ 351 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 352 module_param_named(msi, amdgpu_msi, int, 0444); 353 354 /** 355 * DOC: svm_default_granularity (uint) 356 * Used in buffer migration and handling of recoverable page faults 357 */ 358 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 359 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 360 361 /** 362 * DOC: lockup_timeout (string) 363 * Set GPU scheduler timeout value in ms. 364 * 365 * The format can be [single value] for setting all timeouts at once or 366 * [GFX,Compute,SDMA,Video] to set individual timeouts. 367 * Negative values mean infinity. 368 * 369 * By default(with no lockup_timeout settings), the timeout for all queues is 2000. 370 */ 371 MODULE_PARM_DESC(lockup_timeout, 372 "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video]."); 373 module_param_string(lockup_timeout, amdgpu_lockup_timeout, 374 sizeof(amdgpu_lockup_timeout), 0444); 375 376 /** 377 * DOC: dpm (int) 378 * Override for dynamic power management setting 379 * (0 = disable, 1 = enable) 380 * The default is -1 (auto). 381 */ 382 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 383 module_param_named(dpm, amdgpu_dpm, int, 0444); 384 385 /** 386 * DOC: fw_load_type (int) 387 * Set different firmware loading type for debugging, if supported. 388 * Set to 0 to force direct loading if supported by the ASIC. Set 389 * to -1 to select the default loading mode for the ASIC, as defined 390 * by the driver. The default is -1 (auto). 391 */ 392 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 393 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 394 395 /** 396 * DOC: aspm (int) 397 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 398 */ 399 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 400 module_param_named(aspm, amdgpu_aspm, int, 0444); 401 402 /** 403 * DOC: iommu_perfopt (int) 404 * Control the AMD IOMMU PerfOpt DMA-latency optimization 405 * (0 = disable; -1 = enable on supported devices). 406 * This arms the IOMMU PerfOpt control (IOMMU spec, MMIO Offset 016Ch, EFR PerfOptSup / PerfOptEn) 407 * Arming it disables ATS, PRI, PASID and SVA for the GPU and removes IOMMU DMA containment for it, 408 * trading isolation for lower DMA latency. 409 */ 410 MODULE_PARM_DESC(iommu_perfopt, "Control IOMMU PerfOpt DMA-latency optimization (-1 = enable on supported devices, 0 = disable)"); 411 module_param_named(iommu_perfopt, amdgpu_iommu_perfopt, int, 0444); 412 413 /** 414 * DOC: runpm (int) 415 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 416 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 417 * Setting the value to 0 disables this functionality. 418 * Setting the value to -2 is auto enabled with power down when displays are attached. 419 */ 420 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 421 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 422 423 /** 424 * DOC: ip_block_mask (uint) 425 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 426 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 427 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 428 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 429 */ 430 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 431 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 432 433 /** 434 * DOC: bapm (int) 435 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 436 * The default -1 (auto, enabled) 437 */ 438 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 439 module_param_named(bapm, amdgpu_bapm, int, 0444); 440 441 /** 442 * DOC: deep_color (int) 443 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 444 */ 445 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 446 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 447 448 /** 449 * DOC: vm_size (int) 450 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 451 */ 452 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 453 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 454 455 /** 456 * DOC: vm_fragment_size (int) 457 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 458 */ 459 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 460 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 461 462 /** 463 * DOC: vm_block_size (int) 464 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 465 */ 466 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 467 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 468 469 /** 470 * DOC: vm_fault_stop (int) 471 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 472 */ 473 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 474 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 475 476 /** 477 * DOC: vm_update_mode (int) 478 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 479 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 480 */ 481 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 482 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 483 484 /** 485 * DOC: exp_hw_support (int) 486 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 487 */ 488 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 489 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 490 491 /** 492 * DOC: dc (int) 493 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 494 */ 495 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 496 module_param_named(dc, amdgpu_dc, int, 0444); 497 498 /** 499 * DOC: sched_jobs (int) 500 * Override the max number of jobs supported in the sw queue. The default is 32. 501 */ 502 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 503 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 504 505 /** 506 * DOC: sched_hw_submission (int) 507 * Override the max number of HW submissions. The default is 2. 508 */ 509 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 510 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 511 512 /** 513 * DOC: ppfeaturemask (hexint) 514 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 515 * The default is the current set of stable power features. 516 */ 517 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 518 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 519 520 /** 521 * DOC: forcelongtraining (uint) 522 * Force long memory training in resume. 523 * The default is zero, indicates short training in resume. 524 */ 525 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 526 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 527 528 /** 529 * DOC: pcie_gen_cap (uint) 530 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 531 * The default is 0 (automatic for each asic). 532 */ 533 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 534 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 535 536 /** 537 * DOC: pcie_lane_cap (uint) 538 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 539 * The default is 0 (automatic for each asic). 540 */ 541 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 542 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 543 544 /** 545 * DOC: cg_mask (ullong) 546 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 547 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 548 */ 549 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 550 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 551 552 /** 553 * DOC: pg_mask (uint) 554 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 555 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 556 */ 557 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 558 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 559 560 /** 561 * DOC: sdma_phase_quantum (uint) 562 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 563 */ 564 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 565 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 566 567 /** 568 * DOC: disable_cu (charp) 569 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 570 */ 571 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 572 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 573 574 /** 575 * DOC: virtual_display (charp) 576 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 577 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 578 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 579 * device at 26:00.0. The default is NULL. 580 */ 581 MODULE_PARM_DESC(virtual_display, 582 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 583 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 584 585 /** 586 * DOC: lbpw (int) 587 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 588 */ 589 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 590 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 591 592 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 593 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 594 595 /** 596 * DOC: gpu_recovery (int) 597 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 598 */ 599 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 600 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 601 602 /** 603 * DOC: emu_mode (int) 604 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 605 */ 606 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 607 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 608 609 /** 610 * DOC: ras_enable (int) 611 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 612 */ 613 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 614 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 615 616 /** 617 * DOC: ras_mask (ullong) 618 * Mask of RAS features to enable (default 0xffffffffffffffff), only valid when ras_enable == 1 619 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 620 */ 621 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffffffffffff), only valid when ras_enable == 1"); 622 module_param_named(ras_mask, amdgpu_ras_mask, ullong, 0444); 623 624 /** 625 * DOC: timeout_fatal_disable (bool) 626 * Disable Watchdog timeout fatal error event 627 */ 628 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 629 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 630 631 /** 632 * DOC: timeout_period (uint) 633 * Modify the watchdog timeout max_cycles as (1 << period) 634 */ 635 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 636 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 637 638 /** 639 * DOC: si_support (int) 640 * 1 = enabled, 0 = disabled, -1 = default 641 * 642 * SI (Southern Islands) are first generation GCN GPUs, supported by both 643 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 644 * amdgpu should support SI. 645 * By default, SI dedicated GPUs are supported by amdgpu. 646 * Only relevant when CONFIG_DRM_AMDGPU_SI is enabled to build SI support in amdgpu. 647 * See also radeon.si_support which should be disabled when amdgpu.si_support is 648 * enabled, and vice versa. 649 */ 650 int amdgpu_si_support = -1; 651 #ifdef CONFIG_DRM_AMDGPU_SI 652 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)"); 653 module_param_named(si_support, amdgpu_si_support, int, 0444); 654 #endif 655 656 /** 657 * DOC: cik_support (int) 658 * 1 = enabled, 0 = disabled, -1 = default 659 * 660 * CIK (Sea Islands) are second generation GCN GPUs, supported by both 661 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 662 * amdgpu should support CIK. 663 * By default, CIK dedicated GPUs and APUs are supported by amdgpu. 664 * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu. 665 * See also radeon.cik_support which should be disabled when amdgpu.cik_support is 666 * enabled, and vice versa. 667 */ 668 int amdgpu_cik_support = -1; 669 #ifdef CONFIG_DRM_AMDGPU_CIK 670 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)"); 671 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 672 #endif 673 674 /** 675 * DOC: smu_memory_pool_size (uint) 676 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 677 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 678 */ 679 MODULE_PARM_DESC(smu_memory_pool_size, 680 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 681 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 682 683 /** 684 * DOC: async_gfx_ring (int) 685 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 686 */ 687 MODULE_PARM_DESC(async_gfx_ring, 688 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 689 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 690 691 /** 692 * DOC: mcbp (int) 693 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 694 */ 695 MODULE_PARM_DESC(mcbp, 696 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 697 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 698 699 /** 700 * DOC: discovery (int) 701 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 702 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 703 */ 704 MODULE_PARM_DESC(discovery, 705 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 706 module_param_named(discovery, amdgpu_discovery, int, 0444); 707 708 /** 709 * DOC: mes_log_enable (int) 710 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 711 * (0 = disabled (default), 1 = enabled) 712 */ 713 MODULE_PARM_DESC(mes_log_enable, 714 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 715 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 716 717 /** 718 * DOC: mes_dbgext_buffer_size (int) 719 * Size in KB of the MES firmware debug-extension log buffer. The MES firmware 720 * writes log messages into this buffer and the driver drains and prints them to 721 * dmesg. Requires an MES firmware image built with debug extension support. 722 * (0 = disabled at boot (default)) 723 * 724 * The feature can also be toggled at runtime via the per-device debugfs file 725 * <debugfs>/dri/N/amdgpu_mes_dbgext (echo 1/0 to enable/disable); when enabled 726 * at runtime with this parameter left at 0, a small default buffer is used. 727 */ 728 MODULE_PARM_DESC(mes_dbgext_buffer_size, 729 "MES firmware debug-extension log buffer size in KB (0 = disabled (default))"); 730 module_param_named(mes_dbgext_buffer_size, amdgpu_mes_dbgext_buffer_size, int, 0444); 731 732 /** 733 * DOC: mes_dbgext_options (int) 734 * MES firmware debug-extension option bits sent to the firmware (u64_all). 735 * bit0 = trigger_interrupt_per_new_msg: when set, the firmware raises an 736 * interrupt per message and the driver collects them via the interrupt path; 737 * when clear, the driver polls the log buffer with a kthread instead. 738 * (default 1 = interrupt driven) 739 */ 740 MODULE_PARM_DESC(mes_dbgext_options, 741 "MES debug-extension option bits (bit0: 1 = interrupt (default), 0 = polling)"); 742 module_param_named(mes_dbgext_options, amdgpu_mes_dbgext_options, int, 0444); 743 744 /** 745 * DOC: uni_mes (int) 746 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 747 * (0 = disabled (default), 1 = enabled) 748 */ 749 MODULE_PARM_DESC(uni_mes, 750 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 751 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 752 753 /** 754 * DOC: noretry (int) 755 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 756 * do not support per-process XNACK this also disables retry page faults. 757 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 758 */ 759 MODULE_PARM_DESC(noretry, 760 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 761 module_param_named(noretry, amdgpu_noretry, int, 0644); 762 763 /** 764 * DOC: force_asic_type (int) 765 * A non negative value used to specify the asic type for all supported GPUs. 766 */ 767 MODULE_PARM_DESC(force_asic_type, 768 "A non negative value used to specify the asic type for all supported GPUs"); 769 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 770 771 /** 772 * DOC: use_xgmi_p2p (int) 773 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 774 */ 775 MODULE_PARM_DESC(use_xgmi_p2p, 776 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 777 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 778 779 780 #ifdef CONFIG_HSA_AMD 781 /** 782 * DOC: sched_policy (int) 783 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 784 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 785 * assigns queues to HQDs. 786 */ 787 int sched_policy = KFD_SCHED_POLICY_HWS; 788 module_param_unsafe(sched_policy, int, 0444); 789 MODULE_PARM_DESC(sched_policy, 790 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 791 792 /** 793 * DOC: hws_max_conc_proc (int) 794 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 795 * number of VMIDs assigned to the HWS, which is also the default. 796 */ 797 int hws_max_conc_proc = -1; 798 module_param(hws_max_conc_proc, int, 0444); 799 MODULE_PARM_DESC(hws_max_conc_proc, 800 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 801 802 /** 803 * DOC: cwsr_enable (int) 804 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 805 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 806 * disables it as only in non-HWS mode. 807 */ 808 int cwsr_enable = 1; 809 module_param(cwsr_enable, int, 0444); 810 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off (debugging only), 1 = On (Default))"); 811 812 /** 813 * DOC: max_num_of_queues_per_device (int) 814 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 815 * is 4096. 816 */ 817 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 818 module_param(max_num_of_queues_per_device, int, 0444); 819 MODULE_PARM_DESC(max_num_of_queues_per_device, 820 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 821 822 /** 823 * DOC: send_sigterm (int) 824 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 825 * but just print errors on dmesg. Setting 1 enables sending sigterm. 826 */ 827 int send_sigterm; 828 module_param(send_sigterm, int, 0444); 829 MODULE_PARM_DESC(send_sigterm, 830 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 831 832 /** 833 * DOC: halt_if_hws_hang (int) 834 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 835 * Setting 1 enables halt on hang. 836 */ 837 int halt_if_hws_hang; 838 module_param_unsafe(halt_if_hws_hang, int, 0644); 839 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 840 841 /** 842 * DOC: hws_gws_support(bool) 843 * Assume that HWS supports GWS barriers regardless of what firmware version 844 * check says. Default value: false (rely on MEC2 firmware version check). 845 */ 846 bool hws_gws_support; 847 module_param_unsafe(hws_gws_support, bool, 0444); 848 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 849 850 /** 851 * DOC: queue_preemption_timeout_ms (int) 852 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 853 */ 854 int queue_preemption_timeout_ms = 9000; 855 module_param(queue_preemption_timeout_ms, int, 0644); 856 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 857 858 /** 859 * DOC: debug_evictions(bool) 860 * Enable extra debug messages to help determine the cause of evictions 861 */ 862 bool debug_evictions; 863 module_param(debug_evictions, bool, 0644); 864 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 865 866 /** 867 * DOC: no_system_mem_limit(bool) 868 * Disable system memory limit, to support multiple process shared memory 869 */ 870 bool no_system_mem_limit; 871 module_param(no_system_mem_limit, bool, 0644); 872 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 873 874 /** 875 * DOC: no_queue_eviction_on_vm_fault (int) 876 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 877 */ 878 int amdgpu_no_queue_eviction_on_vm_fault; 879 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 880 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 881 #endif 882 883 /** 884 * DOC: mtype_local (int) 885 */ 886 int amdgpu_mtype_local = -1; 887 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (default: ASIC dependent, 0 = MTYPE_RW, 1 = MTYPE_NC, 2 = MTYPE_CC)"); 888 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 889 890 /** 891 * DOC: mtype_remote (int) 892 */ 893 int amdgpu_mtype_remote = -1; 894 MODULE_PARM_DESC(mtype_remote, "MTYPE for remote memory (default: ASIC dependent, 0 = MTYPE_NC, 1 = MTYPE_UC)"); 895 module_param_named_unsafe(mtype_remote, amdgpu_mtype_remote, int, 0444); 896 897 /** 898 * DOC: pcie_p2p (bool) 899 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 900 */ 901 #ifdef CONFIG_HSA_AMD_P2P 902 bool pcie_p2p = true; 903 module_param(pcie_p2p, bool, 0444); 904 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 905 #endif 906 907 /** 908 * DOC: dcfeaturemask (uint) 909 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 910 * The default is the current set of stable display features. 911 */ 912 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 913 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 914 915 /** 916 * DOC: dcdebugmask (uint) 917 * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 918 */ 919 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 920 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 921 922 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 923 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 924 925 /** 926 * DOC: abmlevel (uint) 927 * Override the default ABM (Adaptive Backlight Management) level used for DC 928 * enabled hardware. Requires DMCU to be supported and loaded. 929 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 930 * default. Values 1-4 control the maximum allowable brightness reduction via 931 * the ABM algorithm, with 1 being the least reduction and 4 being the most 932 * reduction. 933 * 934 * Defaults to -1, or auto. Userspace can only override this level after 935 * boot if it's set to auto. 936 */ 937 int amdgpu_dm_abm_level = -1; 938 MODULE_PARM_DESC(abmlevel, 939 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 940 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 941 942 int amdgpu_backlight = -1; 943 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 944 module_param_named(backlight, amdgpu_backlight, bint, 0444); 945 946 /** 947 * DOC: damageclips (int) 948 * Enable or disable damage clips support. If damage clips support is disabled, 949 * we will force full frame updates, irrespective of what user space sends to 950 * us. 951 * 952 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 953 */ 954 MODULE_PARM_DESC(damageclips, 955 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 956 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 957 958 /** 959 * DOC: tmz (int) 960 * Trusted Memory Zone (TMZ) is a method to protect data being written 961 * to or read from memory. 962 * 963 * The default value: 0 (off). TODO: change to auto till it is completed. 964 */ 965 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 966 module_param_named(tmz, amdgpu_tmz, int, 0444); 967 968 /** 969 * DOC: freesync_video (uint) 970 * Enable the optimization to adjust front porch timing to achieve seamless 971 * mode change experience when setting a freesync supported mode for which full 972 * modeset is not needed. 973 * 974 * The Display Core will add a set of modes derived from the base FreeSync 975 * video mode into the corresponding connector's mode list based on commonly 976 * used refresh rates and VRR range of the connected display, when users enable 977 * this feature. From the userspace perspective, they can see a seamless mode 978 * change experience when the change between different refresh rates under the 979 * same resolution. Additionally, userspace applications such as Video playback 980 * can read this modeset list and change the refresh rate based on the video 981 * frame rate. Finally, the userspace can also derive an appropriate mode for a 982 * particular refresh rate based on the FreeSync Mode and add it to the 983 * connector's mode list. 984 * 985 * Note: This is an experimental feature. 986 * 987 * The default value: 0 (off). 988 */ 989 MODULE_PARM_DESC( 990 freesync_video, 991 "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)"); 992 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 993 994 /** 995 * DOC: reset_method (int) 996 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 997 */ 998 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 999 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 1000 1001 /** 1002 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 1003 * threshold value of faulty pages detected by RAS ECC, which may 1004 * result in the GPU entering bad status when the number of total 1005 * faulty pages by ECC exceeds the threshold value. 1006 */ 1007 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 1008 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 1009 1010 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 1011 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 1012 1013 /** 1014 * DOC: vcnfw_log (int) 1015 * Enable vcnfw log output for debugging, the default is disabled. 1016 */ 1017 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 1018 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 1019 1020 /** 1021 * DOC: sg_display (int) 1022 * Disable S/G (scatter/gather) display (i.e., display from system memory). 1023 * This option is only relevant on APUs. Set this option to 0 to disable 1024 * S/G display if you experience flickering or other issues under memory 1025 * pressure and report the issue. 1026 */ 1027 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 1028 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 1029 1030 /** 1031 * DOC: umsch_mm (int) 1032 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 1033 * (0 = disabled (default), 1 = enabled) 1034 */ 1035 MODULE_PARM_DESC(umsch_mm, 1036 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 1037 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 1038 1039 /** 1040 * DOC: umsch_mm_fwlog (int) 1041 * Enable umschfw log output for debugging, the default is disabled. 1042 */ 1043 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1044 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1045 1046 /** 1047 * DOC: smu_pptable_id (int) 1048 * Used to override pptable id. id = 0 use VBIOS pptable. 1049 * id > 0 use the soft pptable with specicfied id. 1050 */ 1051 MODULE_PARM_DESC(smu_pptable_id, 1052 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1053 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1054 1055 /** 1056 * DOC: partition_mode (int) 1057 * Used to override the default SPX mode. 1058 */ 1059 MODULE_PARM_DESC( 1060 user_partt_mode, 1061 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1062 0 = AMDGPU_SPX_PARTITION_MODE, \ 1063 1 = AMDGPU_DPX_PARTITION_MODE, \ 1064 2 = AMDGPU_TPX_PARTITION_MODE, \ 1065 3 = AMDGPU_QPX_PARTITION_MODE, \ 1066 4 = AMDGPU_CPX_PARTITION_MODE)"); 1067 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1068 1069 1070 /** 1071 * DOC: enforce_isolation (int) 1072 * enforce process isolation between graphics and compute. 1073 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader) 1074 */ 1075 module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444); 1076 MODULE_PARM_DESC(enforce_isolation, 1077 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)"); 1078 1079 /** 1080 * DOC: modeset (int) 1081 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1082 */ 1083 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1084 module_param_named(modeset, amdgpu_modeset, int, 0444); 1085 1086 /** 1087 * DOC: seamless (int) 1088 * Seamless boot will keep the image on the screen during the boot process. 1089 */ 1090 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1091 module_param_named(seamless, amdgpu_seamless, int, 0444); 1092 1093 /** 1094 * DOC: debug_mask (uint) 1095 * Debug options for amdgpu, work as a binary mask with the following options: 1096 * 1097 * - 0x1: Debug VM handling 1098 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1099 * limits the VRAM size reported to ROCm applications to the visible 1100 * size, usually 256MB. 1101 * - 0x4: Disable GPU soft recovery, always do a full reset 1102 * - 0x8: Use VRAM for firmware loading 1103 * - 0x10: Enable ACA based RAS logging 1104 * - 0x20: Enable experimental resets 1105 * - 0x40: Disable ring resets 1106 * - 0x80: Use VRAM for SMU pool 1107 */ 1108 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1109 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1110 1111 /** 1112 * DOC: agp (int) 1113 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1114 * address space for direct access to system memory. Note that these accesses 1115 * are non-snooped, so they are only used for access to uncached memory. 1116 */ 1117 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1118 module_param_named(agp, amdgpu_agp, int, 0444); 1119 1120 /** 1121 * DOC: wbrf (int) 1122 * Enable Wifi RFI interference mitigation feature. 1123 * Due to electrical and mechanical constraints there may be likely interference of 1124 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1125 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1126 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1127 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1128 * P-state transition. However, there may be potential performance impact with this 1129 * feature enabled. 1130 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1131 */ 1132 MODULE_PARM_DESC(wbrf, 1133 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1134 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1135 1136 /** 1137 * DOC: rebar (int) 1138 * Allow BAR resizing. Disable this to prevent the driver from attempting 1139 * to resize the BAR if the GPU supports it and there is available MMIO space. 1140 * Note that this just prevents the driver from resizing the BAR. The BIOS 1141 * may have already resized the BAR at boot time. 1142 */ 1143 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)"); 1144 module_param_named(rebar, amdgpu_rebar, int, 0444); 1145 1146 /** 1147 * DOC: user_queue (int) 1148 * Enable user queues on systems that support user queues. Possible values: 1149 * 1150 * - -1 = auto (ASIC specific default) 1151 * - 0 = user queues disabled 1152 * - 1 = user queues enabled and kernel queues enabled (if supported) 1153 * - 2 = user queues enabled and kernel queues disabled 1154 */ 1155 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)"); 1156 module_param_named(user_queue, amdgpu_user_queue, int, 0444); 1157 1158 /* 1159 * DOC: hdmi_hpd_debounce_delay_ms (uint) 1160 * HDMI HPD disconnect debounce delay in milliseconds. 1161 * 1162 * Used to filter short disconnect->reconnect HPD toggles some HDMI sinks 1163 * generate while entering/leaving power save. Set to 0 to disable by default. 1164 */ 1165 MODULE_PARM_DESC(hdmi_hpd_debounce_delay_ms, "HDMI HPD disconnect debounce delay in milliseconds (0 to disable (by default), 1500 is common)"); 1166 module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms, uint, 0644); 1167 1168 /** 1169 * DOC: ptl (int) 1170 * Enable PTL feature at boot time. Possible values: 1171 * 1172 * - -1 = auto (ASIC specific default) 1173 * - 0 = disable PTL (default) 1174 * - 1 = enable PTL 1175 * - 2 = permanently disable PTL (cannot be re-enabled at runtime) 1176 */ 1177 MODULE_PARM_DESC(ptl, "Enable PTL (-1 = auto, 0 = disable (default), 1 = enable, 2 = permanently disable)"); 1178 module_param_named(ptl, amdgpu_ptl, int, 0444); 1179 1180 /* These devices are not supported by amdgpu. 1181 * They are supported by the mach64, r128, radeon drivers 1182 */ 1183 static const u16 amdgpu_unsupported_pciidlist[] = { 1184 /* mach64 */ 1185 0x4354, 1186 0x4358, 1187 0x4554, 1188 0x4742, 1189 0x4744, 1190 0x4749, 1191 0x474C, 1192 0x474D, 1193 0x474E, 1194 0x474F, 1195 0x4750, 1196 0x4751, 1197 0x4752, 1198 0x4753, 1199 0x4754, 1200 0x4755, 1201 0x4756, 1202 0x4757, 1203 0x4758, 1204 0x4759, 1205 0x475A, 1206 0x4C42, 1207 0x4C44, 1208 0x4C47, 1209 0x4C49, 1210 0x4C4D, 1211 0x4C4E, 1212 0x4C50, 1213 0x4C51, 1214 0x4C52, 1215 0x4C53, 1216 0x5654, 1217 0x5655, 1218 0x5656, 1219 /* r128 */ 1220 0x4c45, 1221 0x4c46, 1222 0x4d46, 1223 0x4d4c, 1224 0x5041, 1225 0x5042, 1226 0x5043, 1227 0x5044, 1228 0x5045, 1229 0x5046, 1230 0x5047, 1231 0x5048, 1232 0x5049, 1233 0x504A, 1234 0x504B, 1235 0x504C, 1236 0x504D, 1237 0x504E, 1238 0x504F, 1239 0x5050, 1240 0x5051, 1241 0x5052, 1242 0x5053, 1243 0x5054, 1244 0x5055, 1245 0x5056, 1246 0x5057, 1247 0x5058, 1248 0x5245, 1249 0x5246, 1250 0x5247, 1251 0x524b, 1252 0x524c, 1253 0x534d, 1254 0x5446, 1255 0x544C, 1256 0x5452, 1257 /* radeon */ 1258 0x3150, 1259 0x3151, 1260 0x3152, 1261 0x3154, 1262 0x3155, 1263 0x3E50, 1264 0x3E54, 1265 0x4136, 1266 0x4137, 1267 0x4144, 1268 0x4145, 1269 0x4146, 1270 0x4147, 1271 0x4148, 1272 0x4149, 1273 0x414A, 1274 0x414B, 1275 0x4150, 1276 0x4151, 1277 0x4152, 1278 0x4153, 1279 0x4154, 1280 0x4155, 1281 0x4156, 1282 0x4237, 1283 0x4242, 1284 0x4336, 1285 0x4337, 1286 0x4437, 1287 0x4966, 1288 0x4967, 1289 0x4A48, 1290 0x4A49, 1291 0x4A4A, 1292 0x4A4B, 1293 0x4A4C, 1294 0x4A4D, 1295 0x4A4E, 1296 0x4A4F, 1297 0x4A50, 1298 0x4A54, 1299 0x4B48, 1300 0x4B49, 1301 0x4B4A, 1302 0x4B4B, 1303 0x4B4C, 1304 0x4C57, 1305 0x4C58, 1306 0x4C59, 1307 0x4C5A, 1308 0x4C64, 1309 0x4C66, 1310 0x4C67, 1311 0x4E44, 1312 0x4E45, 1313 0x4E46, 1314 0x4E47, 1315 0x4E48, 1316 0x4E49, 1317 0x4E4A, 1318 0x4E4B, 1319 0x4E50, 1320 0x4E51, 1321 0x4E52, 1322 0x4E53, 1323 0x4E54, 1324 0x4E56, 1325 0x5144, 1326 0x5145, 1327 0x5146, 1328 0x5147, 1329 0x5148, 1330 0x514C, 1331 0x514D, 1332 0x5157, 1333 0x5158, 1334 0x5159, 1335 0x515A, 1336 0x515E, 1337 0x5460, 1338 0x5462, 1339 0x5464, 1340 0x5548, 1341 0x5549, 1342 0x554A, 1343 0x554B, 1344 0x554C, 1345 0x554D, 1346 0x554E, 1347 0x554F, 1348 0x5550, 1349 0x5551, 1350 0x5552, 1351 0x5554, 1352 0x564A, 1353 0x564B, 1354 0x564F, 1355 0x5652, 1356 0x5653, 1357 0x5657, 1358 0x5834, 1359 0x5835, 1360 0x5954, 1361 0x5955, 1362 0x5974, 1363 0x5975, 1364 0x5960, 1365 0x5961, 1366 0x5962, 1367 0x5964, 1368 0x5965, 1369 0x5969, 1370 0x5a41, 1371 0x5a42, 1372 0x5a61, 1373 0x5a62, 1374 0x5b60, 1375 0x5b62, 1376 0x5b63, 1377 0x5b64, 1378 0x5b65, 1379 0x5c61, 1380 0x5c63, 1381 0x5d48, 1382 0x5d49, 1383 0x5d4a, 1384 0x5d4c, 1385 0x5d4d, 1386 0x5d4e, 1387 0x5d4f, 1388 0x5d50, 1389 0x5d52, 1390 0x5d57, 1391 0x5e48, 1392 0x5e4a, 1393 0x5e4b, 1394 0x5e4c, 1395 0x5e4d, 1396 0x5e4f, 1397 0x6700, 1398 0x6701, 1399 0x6702, 1400 0x6703, 1401 0x6704, 1402 0x6705, 1403 0x6706, 1404 0x6707, 1405 0x6708, 1406 0x6709, 1407 0x6718, 1408 0x6719, 1409 0x671c, 1410 0x671d, 1411 0x671f, 1412 0x6720, 1413 0x6721, 1414 0x6722, 1415 0x6723, 1416 0x6724, 1417 0x6725, 1418 0x6726, 1419 0x6727, 1420 0x6728, 1421 0x6729, 1422 0x6738, 1423 0x6739, 1424 0x673e, 1425 0x6740, 1426 0x6741, 1427 0x6742, 1428 0x6743, 1429 0x6744, 1430 0x6745, 1431 0x6746, 1432 0x6747, 1433 0x6748, 1434 0x6749, 1435 0x674A, 1436 0x6750, 1437 0x6751, 1438 0x6758, 1439 0x6759, 1440 0x675B, 1441 0x675D, 1442 0x675F, 1443 0x6760, 1444 0x6761, 1445 0x6762, 1446 0x6763, 1447 0x6764, 1448 0x6765, 1449 0x6766, 1450 0x6767, 1451 0x6768, 1452 0x6770, 1453 0x6771, 1454 0x6772, 1455 0x6778, 1456 0x6779, 1457 0x677B, 1458 0x6840, 1459 0x6841, 1460 0x6842, 1461 0x6843, 1462 0x6849, 1463 0x684C, 1464 0x6850, 1465 0x6858, 1466 0x6859, 1467 0x6880, 1468 0x6888, 1469 0x6889, 1470 0x688A, 1471 0x688C, 1472 0x688D, 1473 0x6898, 1474 0x6899, 1475 0x689b, 1476 0x689c, 1477 0x689d, 1478 0x689e, 1479 0x68a0, 1480 0x68a1, 1481 0x68a8, 1482 0x68a9, 1483 0x68b0, 1484 0x68b8, 1485 0x68b9, 1486 0x68ba, 1487 0x68be, 1488 0x68bf, 1489 0x68c0, 1490 0x68c1, 1491 0x68c7, 1492 0x68c8, 1493 0x68c9, 1494 0x68d8, 1495 0x68d9, 1496 0x68da, 1497 0x68de, 1498 0x68e0, 1499 0x68e1, 1500 0x68e4, 1501 0x68e5, 1502 0x68e8, 1503 0x68e9, 1504 0x68f1, 1505 0x68f2, 1506 0x68f8, 1507 0x68f9, 1508 0x68fa, 1509 0x68fe, 1510 0x7100, 1511 0x7101, 1512 0x7102, 1513 0x7103, 1514 0x7104, 1515 0x7105, 1516 0x7106, 1517 0x7108, 1518 0x7109, 1519 0x710A, 1520 0x710B, 1521 0x710C, 1522 0x710E, 1523 0x710F, 1524 0x7140, 1525 0x7141, 1526 0x7142, 1527 0x7143, 1528 0x7144, 1529 0x7145, 1530 0x7146, 1531 0x7147, 1532 0x7149, 1533 0x714A, 1534 0x714B, 1535 0x714C, 1536 0x714D, 1537 0x714E, 1538 0x714F, 1539 0x7151, 1540 0x7152, 1541 0x7153, 1542 0x715E, 1543 0x715F, 1544 0x7180, 1545 0x7181, 1546 0x7183, 1547 0x7186, 1548 0x7187, 1549 0x7188, 1550 0x718A, 1551 0x718B, 1552 0x718C, 1553 0x718D, 1554 0x718F, 1555 0x7193, 1556 0x7196, 1557 0x719B, 1558 0x719F, 1559 0x71C0, 1560 0x71C1, 1561 0x71C2, 1562 0x71C3, 1563 0x71C4, 1564 0x71C5, 1565 0x71C6, 1566 0x71C7, 1567 0x71CD, 1568 0x71CE, 1569 0x71D2, 1570 0x71D4, 1571 0x71D5, 1572 0x71D6, 1573 0x71DA, 1574 0x71DE, 1575 0x7200, 1576 0x7210, 1577 0x7211, 1578 0x7240, 1579 0x7243, 1580 0x7244, 1581 0x7245, 1582 0x7246, 1583 0x7247, 1584 0x7248, 1585 0x7249, 1586 0x724A, 1587 0x724B, 1588 0x724C, 1589 0x724D, 1590 0x724E, 1591 0x724F, 1592 0x7280, 1593 0x7281, 1594 0x7283, 1595 0x7284, 1596 0x7287, 1597 0x7288, 1598 0x7289, 1599 0x728B, 1600 0x728C, 1601 0x7290, 1602 0x7291, 1603 0x7293, 1604 0x7297, 1605 0x7834, 1606 0x7835, 1607 0x791e, 1608 0x791f, 1609 0x793f, 1610 0x7941, 1611 0x7942, 1612 0x796c, 1613 0x796d, 1614 0x796e, 1615 0x796f, 1616 0x9400, 1617 0x9401, 1618 0x9402, 1619 0x9403, 1620 0x9405, 1621 0x940A, 1622 0x940B, 1623 0x940F, 1624 0x94A0, 1625 0x94A1, 1626 0x94A3, 1627 0x94B1, 1628 0x94B3, 1629 0x94B4, 1630 0x94B5, 1631 0x94B9, 1632 0x9440, 1633 0x9441, 1634 0x9442, 1635 0x9443, 1636 0x9444, 1637 0x9446, 1638 0x944A, 1639 0x944B, 1640 0x944C, 1641 0x944E, 1642 0x9450, 1643 0x9452, 1644 0x9456, 1645 0x945A, 1646 0x945B, 1647 0x945E, 1648 0x9460, 1649 0x9462, 1650 0x946A, 1651 0x946B, 1652 0x947A, 1653 0x947B, 1654 0x9480, 1655 0x9487, 1656 0x9488, 1657 0x9489, 1658 0x948A, 1659 0x948F, 1660 0x9490, 1661 0x9491, 1662 0x9495, 1663 0x9498, 1664 0x949C, 1665 0x949E, 1666 0x949F, 1667 0x94C0, 1668 0x94C1, 1669 0x94C3, 1670 0x94C4, 1671 0x94C5, 1672 0x94C6, 1673 0x94C7, 1674 0x94C8, 1675 0x94C9, 1676 0x94CB, 1677 0x94CC, 1678 0x94CD, 1679 0x9500, 1680 0x9501, 1681 0x9504, 1682 0x9505, 1683 0x9506, 1684 0x9507, 1685 0x9508, 1686 0x9509, 1687 0x950F, 1688 0x9511, 1689 0x9515, 1690 0x9517, 1691 0x9519, 1692 0x9540, 1693 0x9541, 1694 0x9542, 1695 0x954E, 1696 0x954F, 1697 0x9552, 1698 0x9553, 1699 0x9555, 1700 0x9557, 1701 0x955f, 1702 0x9580, 1703 0x9581, 1704 0x9583, 1705 0x9586, 1706 0x9587, 1707 0x9588, 1708 0x9589, 1709 0x958A, 1710 0x958B, 1711 0x958C, 1712 0x958D, 1713 0x958E, 1714 0x958F, 1715 0x9590, 1716 0x9591, 1717 0x9593, 1718 0x9595, 1719 0x9596, 1720 0x9597, 1721 0x9598, 1722 0x9599, 1723 0x959B, 1724 0x95C0, 1725 0x95C2, 1726 0x95C4, 1727 0x95C5, 1728 0x95C6, 1729 0x95C7, 1730 0x95C9, 1731 0x95CC, 1732 0x95CD, 1733 0x95CE, 1734 0x95CF, 1735 0x9610, 1736 0x9611, 1737 0x9612, 1738 0x9613, 1739 0x9614, 1740 0x9615, 1741 0x9616, 1742 0x9640, 1743 0x9641, 1744 0x9642, 1745 0x9643, 1746 0x9644, 1747 0x9645, 1748 0x9647, 1749 0x9648, 1750 0x9649, 1751 0x964a, 1752 0x964b, 1753 0x964c, 1754 0x964e, 1755 0x964f, 1756 0x9710, 1757 0x9711, 1758 0x9712, 1759 0x9713, 1760 0x9714, 1761 0x9715, 1762 0x9802, 1763 0x9803, 1764 0x9804, 1765 0x9805, 1766 0x9806, 1767 0x9807, 1768 0x9808, 1769 0x9809, 1770 0x980A, 1771 0x9900, 1772 0x9901, 1773 0x9903, 1774 0x9904, 1775 0x9905, 1776 0x9906, 1777 0x9907, 1778 0x9908, 1779 0x9909, 1780 0x990A, 1781 0x990B, 1782 0x990C, 1783 0x990D, 1784 0x990E, 1785 0x990F, 1786 0x9910, 1787 0x9913, 1788 0x9917, 1789 0x9918, 1790 0x9919, 1791 0x9990, 1792 0x9991, 1793 0x9992, 1794 0x9993, 1795 0x9994, 1796 0x9995, 1797 0x9996, 1798 0x9997, 1799 0x9998, 1800 0x9999, 1801 0x999A, 1802 0x999B, 1803 0x999C, 1804 0x999D, 1805 0x99A0, 1806 0x99A2, 1807 0x99A4, 1808 /* radeon secondary ids */ 1809 0x3171, 1810 0x3e70, 1811 0x4164, 1812 0x4165, 1813 0x4166, 1814 0x4168, 1815 0x4170, 1816 0x4171, 1817 0x4172, 1818 0x4173, 1819 0x496e, 1820 0x4a69, 1821 0x4a6a, 1822 0x4a6b, 1823 0x4a70, 1824 0x4a74, 1825 0x4b69, 1826 0x4b6b, 1827 0x4b6c, 1828 0x4c6e, 1829 0x4e64, 1830 0x4e65, 1831 0x4e66, 1832 0x4e67, 1833 0x4e68, 1834 0x4e69, 1835 0x4e6a, 1836 0x4e71, 1837 0x4f73, 1838 0x5569, 1839 0x556b, 1840 0x556d, 1841 0x556f, 1842 0x5571, 1843 0x5854, 1844 0x5874, 1845 0x5940, 1846 0x5941, 1847 0x5b70, 1848 0x5b72, 1849 0x5b73, 1850 0x5b74, 1851 0x5b75, 1852 0x5d44, 1853 0x5d45, 1854 0x5d6d, 1855 0x5d6f, 1856 0x5d72, 1857 0x5d77, 1858 0x5e6b, 1859 0x5e6d, 1860 0x7120, 1861 0x7124, 1862 0x7129, 1863 0x712e, 1864 0x712f, 1865 0x7162, 1866 0x7163, 1867 0x7166, 1868 0x7167, 1869 0x7172, 1870 0x7173, 1871 0x71a0, 1872 0x71a1, 1873 0x71a3, 1874 0x71a7, 1875 0x71bb, 1876 0x71e0, 1877 0x71e1, 1878 0x71e2, 1879 0x71e6, 1880 0x71e7, 1881 0x71f2, 1882 0x7269, 1883 0x726b, 1884 0x726e, 1885 0x72a0, 1886 0x72a8, 1887 0x72b1, 1888 0x72b3, 1889 0x793f, 1890 }; 1891 1892 static const struct pci_device_id pciidlist[] = { 1893 { PCI_DEVICE(0x1002, 0x6780), .driver_data = CHIP_TAHITI }, 1894 { PCI_DEVICE(0x1002, 0x6784), .driver_data = CHIP_TAHITI }, 1895 { PCI_DEVICE(0x1002, 0x6788), .driver_data = CHIP_TAHITI }, 1896 { PCI_DEVICE(0x1002, 0x678A), .driver_data = CHIP_TAHITI }, 1897 { PCI_DEVICE(0x1002, 0x6790), .driver_data = CHIP_TAHITI }, 1898 { PCI_DEVICE(0x1002, 0x6791), .driver_data = CHIP_TAHITI }, 1899 { PCI_DEVICE(0x1002, 0x6792), .driver_data = CHIP_TAHITI }, 1900 { PCI_DEVICE(0x1002, 0x6798), .driver_data = CHIP_TAHITI }, 1901 { PCI_DEVICE(0x1002, 0x6799), .driver_data = CHIP_TAHITI }, 1902 { PCI_DEVICE(0x1002, 0x679A), .driver_data = CHIP_TAHITI }, 1903 { PCI_DEVICE(0x1002, 0x679B), .driver_data = CHIP_TAHITI }, 1904 { PCI_DEVICE(0x1002, 0x679E), .driver_data = CHIP_TAHITI }, 1905 { PCI_DEVICE(0x1002, 0x679F), .driver_data = CHIP_TAHITI }, 1906 { PCI_DEVICE(0x1002, 0x6800), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY }, 1907 { PCI_DEVICE(0x1002, 0x6801), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY }, 1908 { PCI_DEVICE(0x1002, 0x6802), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY }, 1909 { PCI_DEVICE(0x1002, 0x6806), .driver_data = CHIP_PITCAIRN }, 1910 { PCI_DEVICE(0x1002, 0x6808), .driver_data = CHIP_PITCAIRN }, 1911 { PCI_DEVICE(0x1002, 0x6809), .driver_data = CHIP_PITCAIRN }, 1912 { PCI_DEVICE(0x1002, 0x6810), .driver_data = CHIP_PITCAIRN }, 1913 { PCI_DEVICE(0x1002, 0x6811), .driver_data = CHIP_PITCAIRN }, 1914 { PCI_DEVICE(0x1002, 0x6816), .driver_data = CHIP_PITCAIRN }, 1915 { PCI_DEVICE(0x1002, 0x6817), .driver_data = CHIP_PITCAIRN }, 1916 { PCI_DEVICE(0x1002, 0x6818), .driver_data = CHIP_PITCAIRN }, 1917 { PCI_DEVICE(0x1002, 0x6819), .driver_data = CHIP_PITCAIRN }, 1918 { PCI_DEVICE(0x1002, 0x6600), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1919 { PCI_DEVICE(0x1002, 0x6601), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1920 { PCI_DEVICE(0x1002, 0x6602), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1921 { PCI_DEVICE(0x1002, 0x6603), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1922 { PCI_DEVICE(0x1002, 0x6604), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1923 { PCI_DEVICE(0x1002, 0x6605), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1924 { PCI_DEVICE(0x1002, 0x6606), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1925 { PCI_DEVICE(0x1002, 0x6607), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1926 { PCI_DEVICE(0x1002, 0x6608), .driver_data = CHIP_OLAND }, 1927 { PCI_DEVICE(0x1002, 0x6610), .driver_data = CHIP_OLAND }, 1928 { PCI_DEVICE(0x1002, 0x6611), .driver_data = CHIP_OLAND }, 1929 { PCI_DEVICE(0x1002, 0x6613), .driver_data = CHIP_OLAND }, 1930 { PCI_DEVICE(0x1002, 0x6617), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1931 { PCI_DEVICE(0x1002, 0x6620), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1932 { PCI_DEVICE(0x1002, 0x6621), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1933 { PCI_DEVICE(0x1002, 0x6623), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1934 { PCI_DEVICE(0x1002, 0x6631), .driver_data = CHIP_OLAND }, 1935 { PCI_DEVICE(0x1002, 0x6820), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1936 { PCI_DEVICE(0x1002, 0x6821), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1937 { PCI_DEVICE(0x1002, 0x6822), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1938 { PCI_DEVICE(0x1002, 0x6823), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1939 { PCI_DEVICE(0x1002, 0x6824), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1940 { PCI_DEVICE(0x1002, 0x6825), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1941 { PCI_DEVICE(0x1002, 0x6826), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1942 { PCI_DEVICE(0x1002, 0x6827), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1943 { PCI_DEVICE(0x1002, 0x6828), .driver_data = CHIP_VERDE }, 1944 { PCI_DEVICE(0x1002, 0x6829), .driver_data = CHIP_VERDE }, 1945 { PCI_DEVICE(0x1002, 0x682A), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1946 { PCI_DEVICE(0x1002, 0x682B), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1947 { PCI_DEVICE(0x1002, 0x682C), .driver_data = CHIP_VERDE }, 1948 { PCI_DEVICE(0x1002, 0x682D), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1949 { PCI_DEVICE(0x1002, 0x682F), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1950 { PCI_DEVICE(0x1002, 0x6830), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1951 { PCI_DEVICE(0x1002, 0x6831), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1952 { PCI_DEVICE(0x1002, 0x6835), .driver_data = CHIP_VERDE }, 1953 { PCI_DEVICE(0x1002, 0x6837), .driver_data = CHIP_VERDE }, 1954 { PCI_DEVICE(0x1002, 0x6838), .driver_data = CHIP_VERDE }, 1955 { PCI_DEVICE(0x1002, 0x6839), .driver_data = CHIP_VERDE }, 1956 { PCI_DEVICE(0x1002, 0x683B), .driver_data = CHIP_VERDE }, 1957 { PCI_DEVICE(0x1002, 0x683D), .driver_data = CHIP_VERDE }, 1958 { PCI_DEVICE(0x1002, 0x683F), .driver_data = CHIP_VERDE }, 1959 { PCI_DEVICE(0x1002, 0x6660), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1960 { PCI_DEVICE(0x1002, 0x6663), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1961 { PCI_DEVICE(0x1002, 0x6664), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1962 { PCI_DEVICE(0x1002, 0x6665), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1963 { PCI_DEVICE(0x1002, 0x6667), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1964 { PCI_DEVICE(0x1002, 0x666F), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1965 /* Kaveri */ 1966 { PCI_DEVICE(0x1002, 0x1304), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1967 { PCI_DEVICE(0x1002, 0x1305), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1968 { PCI_DEVICE(0x1002, 0x1306), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1969 { PCI_DEVICE(0x1002, 0x1307), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1970 { PCI_DEVICE(0x1002, 0x1309), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1971 { PCI_DEVICE(0x1002, 0x130A), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1972 { PCI_DEVICE(0x1002, 0x130B), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1973 { PCI_DEVICE(0x1002, 0x130C), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1974 { PCI_DEVICE(0x1002, 0x130D), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1975 { PCI_DEVICE(0x1002, 0x130E), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1976 { PCI_DEVICE(0x1002, 0x130F), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1977 { PCI_DEVICE(0x1002, 0x1310), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1978 { PCI_DEVICE(0x1002, 0x1311), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1979 { PCI_DEVICE(0x1002, 0x1312), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1980 { PCI_DEVICE(0x1002, 0x1313), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1981 { PCI_DEVICE(0x1002, 0x1315), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1982 { PCI_DEVICE(0x1002, 0x1316), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1983 { PCI_DEVICE(0x1002, 0x1317), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1984 { PCI_DEVICE(0x1002, 0x1318), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1985 { PCI_DEVICE(0x1002, 0x131B), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1986 { PCI_DEVICE(0x1002, 0x131C), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1987 { PCI_DEVICE(0x1002, 0x131D), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1988 /* Bonaire */ 1989 { PCI_DEVICE(0x1002, 0x6640), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1990 { PCI_DEVICE(0x1002, 0x6641), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1991 { PCI_DEVICE(0x1002, 0x6646), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1992 { PCI_DEVICE(0x1002, 0x6647), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1993 { PCI_DEVICE(0x1002, 0x6649), .driver_data = CHIP_BONAIRE }, 1994 { PCI_DEVICE(0x1002, 0x664D), .driver_data = CHIP_BONAIRE }, 1995 { PCI_DEVICE(0x1002, 0x6650), .driver_data = CHIP_BONAIRE }, 1996 { PCI_DEVICE(0x1002, 0x6651), .driver_data = CHIP_BONAIRE }, 1997 { PCI_DEVICE(0x1002, 0x6658), .driver_data = CHIP_BONAIRE }, 1998 { PCI_DEVICE(0x1002, 0x665c), .driver_data = CHIP_BONAIRE }, 1999 { PCI_DEVICE(0x1002, 0x665d), .driver_data = CHIP_BONAIRE }, 2000 { PCI_DEVICE(0x1002, 0x665f), .driver_data = CHIP_BONAIRE }, 2001 /* Hawaii */ 2002 { PCI_DEVICE(0x1002, 0x67A0), .driver_data = CHIP_HAWAII }, 2003 { PCI_DEVICE(0x1002, 0x67A1), .driver_data = CHIP_HAWAII }, 2004 { PCI_DEVICE(0x1002, 0x67A2), .driver_data = CHIP_HAWAII }, 2005 { PCI_DEVICE(0x1002, 0x67A8), .driver_data = CHIP_HAWAII }, 2006 { PCI_DEVICE(0x1002, 0x67A9), .driver_data = CHIP_HAWAII }, 2007 { PCI_DEVICE(0x1002, 0x67AA), .driver_data = CHIP_HAWAII }, 2008 { PCI_DEVICE(0x1002, 0x67B0), .driver_data = CHIP_HAWAII }, 2009 { PCI_DEVICE(0x1002, 0x67B1), .driver_data = CHIP_HAWAII }, 2010 { PCI_DEVICE(0x1002, 0x67B8), .driver_data = CHIP_HAWAII }, 2011 { PCI_DEVICE(0x1002, 0x67B9), .driver_data = CHIP_HAWAII }, 2012 { PCI_DEVICE(0x1002, 0x67BA), .driver_data = CHIP_HAWAII }, 2013 { PCI_DEVICE(0x1002, 0x67BE), .driver_data = CHIP_HAWAII }, 2014 /* Kabini */ 2015 { PCI_DEVICE(0x1002, 0x9830), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 2016 { PCI_DEVICE(0x1002, 0x9831), .driver_data = CHIP_KABINI|AMD_IS_APU }, 2017 { PCI_DEVICE(0x1002, 0x9832), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 2018 { PCI_DEVICE(0x1002, 0x9833), .driver_data = CHIP_KABINI|AMD_IS_APU }, 2019 { PCI_DEVICE(0x1002, 0x9834), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 2020 { PCI_DEVICE(0x1002, 0x9835), .driver_data = CHIP_KABINI|AMD_IS_APU }, 2021 { PCI_DEVICE(0x1002, 0x9836), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 2022 { PCI_DEVICE(0x1002, 0x9837), .driver_data = CHIP_KABINI|AMD_IS_APU }, 2023 { PCI_DEVICE(0x1002, 0x9838), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 2024 { PCI_DEVICE(0x1002, 0x9839), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 2025 { PCI_DEVICE(0x1002, 0x983a), .driver_data = CHIP_KABINI|AMD_IS_APU }, 2026 { PCI_DEVICE(0x1002, 0x983b), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 2027 { PCI_DEVICE(0x1002, 0x983c), .driver_data = CHIP_KABINI|AMD_IS_APU }, 2028 { PCI_DEVICE(0x1002, 0x983d), .driver_data = CHIP_KABINI|AMD_IS_APU }, 2029 { PCI_DEVICE(0x1002, 0x983e), .driver_data = CHIP_KABINI|AMD_IS_APU }, 2030 { PCI_DEVICE(0x1002, 0x983f), .driver_data = CHIP_KABINI|AMD_IS_APU }, 2031 /* mullins */ 2032 { PCI_DEVICE(0x1002, 0x9850), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2033 { PCI_DEVICE(0x1002, 0x9851), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2034 { PCI_DEVICE(0x1002, 0x9852), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2035 { PCI_DEVICE(0x1002, 0x9853), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2036 { PCI_DEVICE(0x1002, 0x9854), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2037 { PCI_DEVICE(0x1002, 0x9855), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2038 { PCI_DEVICE(0x1002, 0x9856), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2039 { PCI_DEVICE(0x1002, 0x9857), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2040 { PCI_DEVICE(0x1002, 0x9858), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2041 { PCI_DEVICE(0x1002, 0x9859), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2042 { PCI_DEVICE(0x1002, 0x985A), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2043 { PCI_DEVICE(0x1002, 0x985B), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2044 { PCI_DEVICE(0x1002, 0x985C), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2045 { PCI_DEVICE(0x1002, 0x985D), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2046 { PCI_DEVICE(0x1002, 0x985E), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2047 { PCI_DEVICE(0x1002, 0x985F), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2048 /* topaz */ 2049 { PCI_DEVICE(0x1002, 0x6900), .driver_data = CHIP_TOPAZ }, 2050 { PCI_DEVICE(0x1002, 0x6901), .driver_data = CHIP_TOPAZ }, 2051 { PCI_DEVICE(0x1002, 0x6902), .driver_data = CHIP_TOPAZ }, 2052 { PCI_DEVICE(0x1002, 0x6903), .driver_data = CHIP_TOPAZ }, 2053 { PCI_DEVICE(0x1002, 0x6907), .driver_data = CHIP_TOPAZ }, 2054 /* tonga */ 2055 { PCI_DEVICE(0x1002, 0x6920), .driver_data = CHIP_TONGA }, 2056 { PCI_DEVICE(0x1002, 0x6921), .driver_data = CHIP_TONGA }, 2057 { PCI_DEVICE(0x1002, 0x6928), .driver_data = CHIP_TONGA }, 2058 { PCI_DEVICE(0x1002, 0x6929), .driver_data = CHIP_TONGA }, 2059 { PCI_DEVICE(0x1002, 0x692B), .driver_data = CHIP_TONGA }, 2060 { PCI_DEVICE(0x1002, 0x692F), .driver_data = CHIP_TONGA }, 2061 { PCI_DEVICE(0x1002, 0x6930), .driver_data = CHIP_TONGA }, 2062 { PCI_DEVICE(0x1002, 0x6938), .driver_data = CHIP_TONGA }, 2063 { PCI_DEVICE(0x1002, 0x6939), .driver_data = CHIP_TONGA }, 2064 { PCI_DEVICE(0x1002, 0x693B), .driver_data = CHIP_TONGA }, 2065 /* fiji */ 2066 { PCI_DEVICE(0x1002, 0x7300), .driver_data = CHIP_FIJI }, 2067 { PCI_DEVICE(0x1002, 0x730F), .driver_data = CHIP_FIJI }, 2068 /* carrizo */ 2069 { PCI_DEVICE(0x1002, 0x9870), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2070 { PCI_DEVICE(0x1002, 0x9874), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2071 { PCI_DEVICE(0x1002, 0x9875), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2072 { PCI_DEVICE(0x1002, 0x9876), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2073 { PCI_DEVICE(0x1002, 0x9877), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2074 /* stoney */ 2075 { PCI_DEVICE(0x1002, 0x98E4), .driver_data = CHIP_STONEY|AMD_IS_APU }, 2076 /* Polaris11 */ 2077 { PCI_DEVICE(0x1002, 0x67E0), .driver_data = CHIP_POLARIS11 }, 2078 { PCI_DEVICE(0x1002, 0x67E3), .driver_data = CHIP_POLARIS11 }, 2079 { PCI_DEVICE(0x1002, 0x67E8), .driver_data = CHIP_POLARIS11 }, 2080 { PCI_DEVICE(0x1002, 0x67EB), .driver_data = CHIP_POLARIS11 }, 2081 { PCI_DEVICE(0x1002, 0x67EF), .driver_data = CHIP_POLARIS11 }, 2082 { PCI_DEVICE(0x1002, 0x67FF), .driver_data = CHIP_POLARIS11 }, 2083 { PCI_DEVICE(0x1002, 0x67E1), .driver_data = CHIP_POLARIS11 }, 2084 { PCI_DEVICE(0x1002, 0x67E7), .driver_data = CHIP_POLARIS11 }, 2085 { PCI_DEVICE(0x1002, 0x67E9), .driver_data = CHIP_POLARIS11 }, 2086 /* Polaris10 */ 2087 { PCI_DEVICE(0x1002, 0x67C0), .driver_data = CHIP_POLARIS10 }, 2088 { PCI_DEVICE(0x1002, 0x67C1), .driver_data = CHIP_POLARIS10 }, 2089 { PCI_DEVICE(0x1002, 0x67C2), .driver_data = CHIP_POLARIS10 }, 2090 { PCI_DEVICE(0x1002, 0x67C4), .driver_data = CHIP_POLARIS10 }, 2091 { PCI_DEVICE(0x1002, 0x67C7), .driver_data = CHIP_POLARIS10 }, 2092 { PCI_DEVICE(0x1002, 0x67D0), .driver_data = CHIP_POLARIS10 }, 2093 { PCI_DEVICE(0x1002, 0x67D4), .driver_data = CHIP_POLARIS10 }, 2094 { PCI_DEVICE(0x1002, 0x67DF), .driver_data = CHIP_POLARIS10 }, 2095 { PCI_DEVICE(0x1002, 0x67C8), .driver_data = CHIP_POLARIS10 }, 2096 { PCI_DEVICE(0x1002, 0x67C9), .driver_data = CHIP_POLARIS10 }, 2097 { PCI_DEVICE(0x1002, 0x67CA), .driver_data = CHIP_POLARIS10 }, 2098 { PCI_DEVICE(0x1002, 0x67CC), .driver_data = CHIP_POLARIS10 }, 2099 { PCI_DEVICE(0x1002, 0x67CF), .driver_data = CHIP_POLARIS10 }, 2100 { PCI_DEVICE(0x1002, 0x6FDF), .driver_data = CHIP_POLARIS10 }, 2101 /* Polaris12 */ 2102 { PCI_DEVICE(0x1002, 0x6980), .driver_data = CHIP_POLARIS12 }, 2103 { PCI_DEVICE(0x1002, 0x6981), .driver_data = CHIP_POLARIS12 }, 2104 { PCI_DEVICE(0x1002, 0x6985), .driver_data = CHIP_POLARIS12 }, 2105 { PCI_DEVICE(0x1002, 0x6986), .driver_data = CHIP_POLARIS12 }, 2106 { PCI_DEVICE(0x1002, 0x6987), .driver_data = CHIP_POLARIS12 }, 2107 { PCI_DEVICE(0x1002, 0x698F), .driver_data = CHIP_POLARIS12 }, 2108 { PCI_DEVICE(0x1002, 0x6995), .driver_data = CHIP_POLARIS12 }, 2109 { PCI_DEVICE(0x1002, 0x6997), .driver_data = CHIP_POLARIS12 }, 2110 { PCI_DEVICE(0x1002, 0x699F), .driver_data = CHIP_POLARIS12 }, 2111 /* VEGAM */ 2112 { PCI_DEVICE(0x1002, 0x694C), .driver_data = CHIP_VEGAM }, 2113 { PCI_DEVICE(0x1002, 0x694E), .driver_data = CHIP_VEGAM }, 2114 { PCI_DEVICE(0x1002, 0x694F), .driver_data = CHIP_VEGAM }, 2115 /* Vega 10 */ 2116 { PCI_DEVICE(0x1002, 0x6860), .driver_data = CHIP_VEGA10 }, 2117 { PCI_DEVICE(0x1002, 0x6861), .driver_data = CHIP_VEGA10 }, 2118 { PCI_DEVICE(0x1002, 0x6862), .driver_data = CHIP_VEGA10 }, 2119 { PCI_DEVICE(0x1002, 0x6863), .driver_data = CHIP_VEGA10 }, 2120 { PCI_DEVICE(0x1002, 0x6864), .driver_data = CHIP_VEGA10 }, 2121 { PCI_DEVICE(0x1002, 0x6867), .driver_data = CHIP_VEGA10 }, 2122 { PCI_DEVICE(0x1002, 0x6868), .driver_data = CHIP_VEGA10 }, 2123 { PCI_DEVICE(0x1002, 0x6869), .driver_data = CHIP_VEGA10 }, 2124 { PCI_DEVICE(0x1002, 0x686a), .driver_data = CHIP_VEGA10 }, 2125 { PCI_DEVICE(0x1002, 0x686b), .driver_data = CHIP_VEGA10 }, 2126 { PCI_DEVICE(0x1002, 0x686c), .driver_data = CHIP_VEGA10 }, 2127 { PCI_DEVICE(0x1002, 0x686d), .driver_data = CHIP_VEGA10 }, 2128 { PCI_DEVICE(0x1002, 0x686e), .driver_data = CHIP_VEGA10 }, 2129 { PCI_DEVICE(0x1002, 0x686f), .driver_data = CHIP_VEGA10 }, 2130 { PCI_DEVICE(0x1002, 0x687f), .driver_data = CHIP_VEGA10 }, 2131 /* Vega 12 */ 2132 { PCI_DEVICE(0x1002, 0x69A0), .driver_data = CHIP_VEGA12 }, 2133 { PCI_DEVICE(0x1002, 0x69A1), .driver_data = CHIP_VEGA12 }, 2134 { PCI_DEVICE(0x1002, 0x69A2), .driver_data = CHIP_VEGA12 }, 2135 { PCI_DEVICE(0x1002, 0x69A3), .driver_data = CHIP_VEGA12 }, 2136 { PCI_DEVICE(0x1002, 0x69AF), .driver_data = CHIP_VEGA12 }, 2137 /* Vega 20 */ 2138 { PCI_DEVICE(0x1002, 0x66A0), .driver_data = CHIP_VEGA20 }, 2139 { PCI_DEVICE(0x1002, 0x66A1), .driver_data = CHIP_VEGA20 }, 2140 { PCI_DEVICE(0x1002, 0x66A2), .driver_data = CHIP_VEGA20 }, 2141 { PCI_DEVICE(0x1002, 0x66A3), .driver_data = CHIP_VEGA20 }, 2142 { PCI_DEVICE(0x1002, 0x66A4), .driver_data = CHIP_VEGA20 }, 2143 { PCI_DEVICE(0x1002, 0x66A7), .driver_data = CHIP_VEGA20 }, 2144 { PCI_DEVICE(0x1002, 0x66AF), .driver_data = CHIP_VEGA20 }, 2145 /* Raven */ 2146 { PCI_DEVICE(0x1002, 0x15dd), .driver_data = CHIP_RAVEN|AMD_IS_APU }, 2147 { PCI_DEVICE(0x1002, 0x15d8), .driver_data = CHIP_RAVEN|AMD_IS_APU }, 2148 /* Arcturus */ 2149 { PCI_DEVICE(0x1002, 0x738C), .driver_data = CHIP_ARCTURUS }, 2150 { PCI_DEVICE(0x1002, 0x7388), .driver_data = CHIP_ARCTURUS }, 2151 { PCI_DEVICE(0x1002, 0x738E), .driver_data = CHIP_ARCTURUS }, 2152 { PCI_DEVICE(0x1002, 0x7390), .driver_data = CHIP_ARCTURUS }, 2153 /* Navi10 */ 2154 { PCI_DEVICE(0x1002, 0x7310), .driver_data = CHIP_NAVI10 }, 2155 { PCI_DEVICE(0x1002, 0x7312), .driver_data = CHIP_NAVI10 }, 2156 { PCI_DEVICE(0x1002, 0x7318), .driver_data = CHIP_NAVI10 }, 2157 { PCI_DEVICE(0x1002, 0x7319), .driver_data = CHIP_NAVI10 }, 2158 { PCI_DEVICE(0x1002, 0x731A), .driver_data = CHIP_NAVI10 }, 2159 { PCI_DEVICE(0x1002, 0x731B), .driver_data = CHIP_NAVI10 }, 2160 { PCI_DEVICE(0x1002, 0x731E), .driver_data = CHIP_NAVI10 }, 2161 { PCI_DEVICE(0x1002, 0x731F), .driver_data = CHIP_NAVI10 }, 2162 /* Navi14 */ 2163 { PCI_DEVICE(0x1002, 0x7340), .driver_data = CHIP_NAVI14 }, 2164 { PCI_DEVICE(0x1002, 0x7341), .driver_data = CHIP_NAVI14 }, 2165 { PCI_DEVICE(0x1002, 0x7347), .driver_data = CHIP_NAVI14 }, 2166 { PCI_DEVICE(0x1002, 0x734F), .driver_data = CHIP_NAVI14 }, 2167 2168 /* Renoir */ 2169 { PCI_DEVICE(0x1002, 0x15E7), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2170 { PCI_DEVICE(0x1002, 0x1636), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2171 { PCI_DEVICE(0x1002, 0x1638), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2172 { PCI_DEVICE(0x1002, 0x164C), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2173 2174 /* Navi12 */ 2175 { PCI_DEVICE(0x1002, 0x7360), .driver_data = CHIP_NAVI12 }, 2176 { PCI_DEVICE(0x1002, 0x7362), .driver_data = CHIP_NAVI12 }, 2177 2178 /* Sienna_Cichlid */ 2179 { PCI_DEVICE(0x1002, 0x73A0), .driver_data = CHIP_SIENNA_CICHLID }, 2180 { PCI_DEVICE(0x1002, 0x73A1), .driver_data = CHIP_SIENNA_CICHLID }, 2181 { PCI_DEVICE(0x1002, 0x73A2), .driver_data = CHIP_SIENNA_CICHLID }, 2182 { PCI_DEVICE(0x1002, 0x73A3), .driver_data = CHIP_SIENNA_CICHLID }, 2183 { PCI_DEVICE(0x1002, 0x73A5), .driver_data = CHIP_SIENNA_CICHLID }, 2184 { PCI_DEVICE(0x1002, 0x73A8), .driver_data = CHIP_SIENNA_CICHLID }, 2185 { PCI_DEVICE(0x1002, 0x73A9), .driver_data = CHIP_SIENNA_CICHLID }, 2186 { PCI_DEVICE(0x1002, 0x73AB), .driver_data = CHIP_SIENNA_CICHLID }, 2187 { PCI_DEVICE(0x1002, 0x73AC), .driver_data = CHIP_SIENNA_CICHLID }, 2188 { PCI_DEVICE(0x1002, 0x73AD), .driver_data = CHIP_SIENNA_CICHLID }, 2189 { PCI_DEVICE(0x1002, 0x73AE), .driver_data = CHIP_SIENNA_CICHLID }, 2190 { PCI_DEVICE(0x1002, 0x73AF), .driver_data = CHIP_SIENNA_CICHLID }, 2191 { PCI_DEVICE(0x1002, 0x73BF), .driver_data = CHIP_SIENNA_CICHLID }, 2192 2193 /* Yellow Carp */ 2194 { PCI_DEVICE(0x1002, 0x164D), .driver_data = CHIP_YELLOW_CARP|AMD_IS_APU }, 2195 { PCI_DEVICE(0x1002, 0x1681), .driver_data = CHIP_YELLOW_CARP|AMD_IS_APU }, 2196 2197 /* Navy_Flounder */ 2198 { PCI_DEVICE(0x1002, 0x73C0), .driver_data = CHIP_NAVY_FLOUNDER }, 2199 { PCI_DEVICE(0x1002, 0x73C1), .driver_data = CHIP_NAVY_FLOUNDER }, 2200 { PCI_DEVICE(0x1002, 0x73C3), .driver_data = CHIP_NAVY_FLOUNDER }, 2201 { PCI_DEVICE(0x1002, 0x73DA), .driver_data = CHIP_NAVY_FLOUNDER }, 2202 { PCI_DEVICE(0x1002, 0x73DB), .driver_data = CHIP_NAVY_FLOUNDER }, 2203 { PCI_DEVICE(0x1002, 0x73DC), .driver_data = CHIP_NAVY_FLOUNDER }, 2204 { PCI_DEVICE(0x1002, 0x73DD), .driver_data = CHIP_NAVY_FLOUNDER }, 2205 { PCI_DEVICE(0x1002, 0x73DE), .driver_data = CHIP_NAVY_FLOUNDER }, 2206 { PCI_DEVICE(0x1002, 0x73DF), .driver_data = CHIP_NAVY_FLOUNDER }, 2207 2208 /* DIMGREY_CAVEFISH */ 2209 { PCI_DEVICE(0x1002, 0x73E0), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2210 { PCI_DEVICE(0x1002, 0x73E1), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2211 { PCI_DEVICE(0x1002, 0x73E2), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2212 { PCI_DEVICE(0x1002, 0x73E3), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2213 { PCI_DEVICE(0x1002, 0x73E8), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2214 { PCI_DEVICE(0x1002, 0x73E9), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2215 { PCI_DEVICE(0x1002, 0x73EA), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2216 { PCI_DEVICE(0x1002, 0x73EB), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2217 { PCI_DEVICE(0x1002, 0x73EC), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2218 { PCI_DEVICE(0x1002, 0x73ED), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2219 { PCI_DEVICE(0x1002, 0x73EF), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2220 { PCI_DEVICE(0x1002, 0x73FF), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2221 2222 /* Aldebaran */ 2223 { PCI_DEVICE(0x1002, 0x7408), .driver_data = CHIP_ALDEBARAN }, 2224 { PCI_DEVICE(0x1002, 0x740C), .driver_data = CHIP_ALDEBARAN }, 2225 { PCI_DEVICE(0x1002, 0x740F), .driver_data = CHIP_ALDEBARAN }, 2226 { PCI_DEVICE(0x1002, 0x7410), .driver_data = CHIP_ALDEBARAN }, 2227 2228 /* CYAN_SKILLFISH */ 2229 { PCI_DEVICE(0x1002, 0x13DB), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2230 { PCI_DEVICE(0x1002, 0x13F9), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2231 { PCI_DEVICE(0x1002, 0x13FA), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2232 { PCI_DEVICE(0x1002, 0x13FB), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2233 { PCI_DEVICE(0x1002, 0x13FC), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2234 { PCI_DEVICE(0x1002, 0x13FE), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2235 { PCI_DEVICE(0x1002, 0x143F), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2236 2237 /* BEIGE_GOBY */ 2238 { PCI_DEVICE(0x1002, 0x7420), .driver_data = CHIP_BEIGE_GOBY }, 2239 { PCI_DEVICE(0x1002, 0x7421), .driver_data = CHIP_BEIGE_GOBY }, 2240 { PCI_DEVICE(0x1002, 0x7422), .driver_data = CHIP_BEIGE_GOBY }, 2241 { PCI_DEVICE(0x1002, 0x7423), .driver_data = CHIP_BEIGE_GOBY }, 2242 { PCI_DEVICE(0x1002, 0x7424), .driver_data = CHIP_BEIGE_GOBY }, 2243 { PCI_DEVICE(0x1002, 0x743F), .driver_data = CHIP_BEIGE_GOBY }, 2244 2245 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2246 .class = PCI_CLASS_DISPLAY_VGA << 8, 2247 .class_mask = 0xffffff, 2248 .driver_data = CHIP_IP_DISCOVERY }, 2249 2250 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2251 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2252 .class_mask = 0xffffff, 2253 .driver_data = CHIP_IP_DISCOVERY }, 2254 2255 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2256 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2257 .class_mask = 0xffffff, 2258 .driver_data = CHIP_IP_DISCOVERY }, 2259 2260 { } 2261 }; 2262 2263 MODULE_DEVICE_TABLE(pci, pciidlist); 2264 2265 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2266 /* differentiate between P10 and P11 asics with the same DID */ 2267 {0x67FF, 0xE3, CHIP_POLARIS10}, 2268 {0x67FF, 0xE7, CHIP_POLARIS10}, 2269 {0x67FF, 0xF3, CHIP_POLARIS10}, 2270 {0x67FF, 0xF7, CHIP_POLARIS10}, 2271 }; 2272 2273 static const struct drm_driver amdgpu_kms_driver; 2274 2275 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2276 { 2277 struct pci_dev *p = NULL; 2278 int i; 2279 2280 /* 0 - GPU 2281 * 1 - audio 2282 * 2 - USB 2283 * 3 - UCSI 2284 */ 2285 for (i = 1; i < 4; i++) { 2286 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2287 adev->pdev->bus->number, i); 2288 if (p) { 2289 pm_runtime_get_sync(&p->dev); 2290 pm_runtime_put_autosuspend(&p->dev); 2291 pci_dev_put(p); 2292 } 2293 } 2294 } 2295 2296 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2297 { 2298 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2299 pr_info("debug: VM handling debug enabled\n"); 2300 adev->debug_vm = true; 2301 } 2302 2303 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2304 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2305 adev->debug_largebar = true; 2306 } 2307 2308 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2309 pr_info("debug: soft recovery disabled\n"); 2310 adev->debug_disable_soft_recovery = true; 2311 } 2312 2313 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2314 pr_info("debug: place fw in vram for frontdoor loading\n"); 2315 adev->debug_use_vram_fw_buf = true; 2316 } 2317 2318 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2319 pr_info("debug: enable experimental reset features\n"); 2320 adev->debug_exp_resets = true; 2321 } 2322 2323 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2324 pr_info("debug: ring reset disabled\n"); 2325 adev->debug_disable_gpu_ring_reset = true; 2326 } 2327 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) { 2328 pr_info("debug: use vram for smu pool\n"); 2329 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM; 2330 } 2331 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) { 2332 pr_info("debug: VM mode debug for userptr is enabled\n"); 2333 adev->debug_vm_userptr = true; 2334 } 2335 2336 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) { 2337 pr_info("debug: disable kernel logs of correctable errors\n"); 2338 adev->debug_disable_ce_logs = true; 2339 } 2340 2341 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) { 2342 pr_info("debug: allowing command submission to CE engine\n"); 2343 adev->debug_enable_ce_cs = true; 2344 } 2345 2346 if (amdgpu_debug_mask & AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU) { 2347 pr_info("debug: resume gpu in thaw() of hibernation\n"); 2348 adev->debug_hibernation_thaw_resume_gpu = true; 2349 } 2350 2351 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET) { 2352 pr_info("debug: IP block soft reset disabled\n"); 2353 adev->debug_disable_ip_block_soft_reset = true; 2354 } 2355 2356 if (amdgpu_debug_mask & AMDGPU_DEBUG_SDMA_RB_CMD) { 2357 pr_info("debug: enable SDMA RB command switch\n"); 2358 adev->sdma.sdma_debug = true; 2359 } 2360 } 2361 2362 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2363 { 2364 int i; 2365 2366 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2367 if (pdev->device == asic_type_quirks[i].device && 2368 pdev->revision == asic_type_quirks[i].revision) { 2369 flags &= ~AMD_ASIC_MASK; 2370 flags |= asic_type_quirks[i].type; 2371 break; 2372 } 2373 } 2374 2375 return flags; 2376 } 2377 2378 static bool amdgpu_support_enabled(struct device *dev, 2379 const enum amd_asic_type family) 2380 { 2381 const char *gen; 2382 const char *param; 2383 int module_param = -1; 2384 bool radeon_support_built = IS_ENABLED(CONFIG_DRM_RADEON); 2385 bool amdgpu_support_built = false; 2386 bool support_by_default = false; 2387 2388 switch (family) { 2389 case CHIP_TAHITI: 2390 case CHIP_PITCAIRN: 2391 case CHIP_VERDE: 2392 case CHIP_OLAND: 2393 case CHIP_HAINAN: 2394 gen = "SI"; 2395 param = "si_support"; 2396 module_param = amdgpu_si_support; 2397 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_SI); 2398 support_by_default = true; 2399 break; 2400 2401 case CHIP_BONAIRE: 2402 case CHIP_HAWAII: 2403 case CHIP_KAVERI: 2404 case CHIP_KABINI: 2405 case CHIP_MULLINS: 2406 gen = "CIK"; 2407 param = "cik_support"; 2408 module_param = amdgpu_cik_support; 2409 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK); 2410 support_by_default = true; 2411 break; 2412 2413 default: 2414 /* All other chips are supported by amdgpu only */ 2415 return true; 2416 } 2417 2418 if (!amdgpu_support_built) { 2419 dev_info(dev, "amdgpu built without %s support\n", gen); 2420 return false; 2421 } 2422 2423 if ((module_param == -1 && (support_by_default || !radeon_support_built)) || 2424 module_param == 1) { 2425 if (radeon_support_built) 2426 dev_info(dev, "%s support provided by amdgpu.\n" 2427 "Use radeon.%s=1 amdgpu.%s=0 to override.\n", 2428 gen, param, param); 2429 2430 return true; 2431 } 2432 2433 if (radeon_support_built) 2434 dev_info(dev, "%s support provided by radeon.\n" 2435 "Use radeon.%s=0 amdgpu.%s=1 to override.\n", 2436 gen, param, param); 2437 else if (module_param == 0) 2438 dev_info(dev, "%s support disabled by module param\n", gen); 2439 2440 return false; 2441 } 2442 2443 static int amdgpu_pci_probe(struct pci_dev *pdev, 2444 const struct pci_device_id *ent) 2445 { 2446 struct drm_device *ddev; 2447 struct amdgpu_device *adev; 2448 unsigned long flags = ent->driver_data; 2449 int ret, retry = 0, i; 2450 bool supports_atomic = false; 2451 2452 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2453 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2454 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2455 return -EINVAL; 2456 } 2457 2458 /* skip devices which are owned by radeon */ 2459 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2460 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2461 return -ENODEV; 2462 } 2463 2464 if (amdgpu_virtual_display || 2465 amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) 2466 supports_atomic = true; 2467 2468 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2469 dev_info(&pdev->dev, "This hardware requires experimental hardware support.\n" 2470 "See modparam exp_hw_support\n"); 2471 return -ENODEV; 2472 } 2473 2474 flags = amdgpu_fix_asic_type(pdev, flags); 2475 2476 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2477 * however, SME requires an indirect IOMMU mapping because the encryption 2478 * bit is beyond the DMA mask of the chip. 2479 */ 2480 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2481 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2482 dev_info(&pdev->dev, 2483 "SME is not compatible with RAVEN\n"); 2484 return -ENOTSUPP; 2485 } 2486 2487 if (!amdgpu_support_enabled(&pdev->dev, flags & AMD_ASIC_MASK)) 2488 return -ENODEV; 2489 2490 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2491 if (IS_ERR(adev)) 2492 return PTR_ERR(adev); 2493 2494 adev->dev = &pdev->dev; 2495 adev->pdev = pdev; 2496 ddev = adev_to_drm(adev); 2497 2498 if (!supports_atomic) 2499 ddev->driver_features &= ~DRIVER_ATOMIC; 2500 2501 ret = pci_enable_device(pdev); 2502 if (ret) 2503 return ret; 2504 2505 pci_set_drvdata(pdev, ddev); 2506 2507 amdgpu_init_debug_options(adev); 2508 2509 ret = amdgpu_driver_load_kms(adev, flags); 2510 if (ret) 2511 goto err_pci; 2512 2513 retry_init: 2514 ret = drm_dev_register(ddev, flags); 2515 if (ret == -EAGAIN && ++retry <= 3) { 2516 drm_info(adev_to_drm(adev), "retry init %d\n", retry); 2517 /* Don't request EX mode too frequently which is attacking */ 2518 msleep(5000); 2519 goto retry_init; 2520 } else if (ret) { 2521 goto err_pci; 2522 } 2523 2524 ret = amdgpu_xcp_dev_register(adev, ent); 2525 if (ret) 2526 goto err_pci; 2527 2528 ret = amdgpu_amdkfd_drm_client_create(adev); 2529 if (ret) 2530 goto err_pci; 2531 2532 /* 2533 * 1. don't init fbdev on hw without DCE 2534 * 2. don't init fbdev if there are no connectors 2535 */ 2536 if (adev->mode_info.mode_config_initialized && 2537 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2538 const struct drm_format_info *format; 2539 2540 /* select 8 bpp console on low vram cards */ 2541 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2542 format = drm_format_info(DRM_FORMAT_C8); 2543 else 2544 format = NULL; 2545 2546 drm_client_setup(adev_to_drm(adev), format); 2547 } 2548 2549 ret = amdgpu_debugfs_init(adev); 2550 if (ret) 2551 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2552 2553 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2554 /* only need to skip on ATPX */ 2555 if (amdgpu_device_supports_px(adev)) 2556 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2557 /* we want direct complete for BOCO */ 2558 if (amdgpu_device_supports_boco(adev)) 2559 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2560 DPM_FLAG_SMART_SUSPEND | 2561 DPM_FLAG_MAY_SKIP_RESUME); 2562 pm_runtime_use_autosuspend(ddev->dev); 2563 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2564 2565 pm_runtime_allow(ddev->dev); 2566 2567 pm_runtime_put_autosuspend(ddev->dev); 2568 2569 pci_wake_from_d3(pdev, TRUE); 2570 2571 /* 2572 * For runpm implemented via BACO, PMFW will handle the 2573 * timing for BACO in and out: 2574 * - put ASIC into BACO state only when both video and 2575 * audio functions are in D3 state. 2576 * - pull ASIC out of BACO state when either video or 2577 * audio function is in D0 state. 2578 * Also, at startup, PMFW assumes both functions are in 2579 * D0 state. 2580 * 2581 * So if snd driver was loaded prior to amdgpu driver 2582 * and audio function was put into D3 state, there will 2583 * be no PMFW-aware D-state transition(D0->D3) on runpm 2584 * suspend. Thus the BACO will be not correctly kicked in. 2585 * 2586 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2587 * into D0 state. Then there will be a PMFW-aware D-state 2588 * transition(D0->D3) on runpm suspend. 2589 */ 2590 if (amdgpu_device_supports_baco(adev) && 2591 !(adev->flags & AMD_IS_APU) && 2592 adev->asic_type >= CHIP_NAVI10) 2593 amdgpu_get_secondary_funcs(adev); 2594 } 2595 2596 return 0; 2597 2598 err_pci: 2599 pci_disable_device(pdev); 2600 return ret; 2601 } 2602 2603 static void 2604 amdgpu_pci_remove(struct pci_dev *pdev) 2605 { 2606 struct drm_device *dev = pci_get_drvdata(pdev); 2607 struct amdgpu_device *adev = drm_to_adev(dev); 2608 2609 amdgpu_ras_eeprom_check_and_recover(adev); 2610 amdgpu_xcp_dev_unplug(adev); 2611 amdgpu_gmc_prepare_nps_mode_change(adev); 2612 drm_dev_unplug(dev); 2613 2614 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2615 pm_runtime_get_sync(dev->dev); 2616 pm_runtime_forbid(dev->dev); 2617 pm_runtime_dont_use_autosuspend(dev->dev); 2618 } 2619 2620 amdgpu_driver_unload_kms(dev); 2621 2622 amdgpu_discovery_sysfs_early_fini(pdev); 2623 2624 /* 2625 * Flush any in flight DMA operations from device. 2626 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2627 * StatusTransactions Pending bit. 2628 */ 2629 pci_disable_device(pdev); 2630 pci_wait_for_pending_transaction(pdev); 2631 } 2632 2633 static void 2634 amdgpu_pci_shutdown(struct pci_dev *pdev) 2635 { 2636 struct drm_device *dev = pci_get_drvdata(pdev); 2637 struct amdgpu_device *adev = drm_to_adev(dev); 2638 2639 if (amdgpu_ras_intr_triggered()) 2640 return; 2641 2642 /* device maybe not resumed here, return immediately in this case */ 2643 if (adev->in_s4 && adev->in_suspend) 2644 return; 2645 2646 /* if we are running in a VM, make sure the device 2647 * torn down properly on reboot/shutdown. 2648 * unfortunately we can't detect certain 2649 * hypervisors so just do this all the time. 2650 */ 2651 if (!amdgpu_passthrough(adev)) 2652 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2653 amdgpu_device_prepare(dev); 2654 amdgpu_device_suspend(dev, true); 2655 adev->mp1_state = PP_MP1_STATE_NONE; 2656 } 2657 2658 static int amdgpu_pmops_prepare(struct device *dev) 2659 { 2660 struct drm_device *drm_dev = dev_get_drvdata(dev); 2661 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2662 2663 /* device maybe not resumed here, return immediately in this case */ 2664 if (adev->in_s4 && adev->in_suspend) 2665 return 0; 2666 2667 /* Return a positive number here so 2668 * DPM_FLAG_SMART_SUSPEND works properly 2669 */ 2670 if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev)) 2671 return 1; 2672 2673 /* if we will not support s3 or s2i for the device 2674 * then skip suspend 2675 */ 2676 if (!amdgpu_acpi_is_s0ix_active(adev) && 2677 !amdgpu_acpi_is_s3_active(adev)) 2678 return 1; 2679 2680 return amdgpu_device_prepare(drm_dev); 2681 } 2682 2683 static void amdgpu_pmops_complete(struct device *dev) 2684 { 2685 amdgpu_device_complete(dev_get_drvdata(dev)); 2686 } 2687 2688 static int amdgpu_pmops_suspend(struct device *dev) 2689 { 2690 struct drm_device *drm_dev = dev_get_drvdata(dev); 2691 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2692 2693 if (amdgpu_acpi_is_s0ix_active(adev)) 2694 adev->in_s0ix = true; 2695 else if (amdgpu_acpi_is_s3_active(adev)) 2696 adev->in_s3 = true; 2697 if (!adev->in_s0ix && !adev->in_s3) { 2698 #if IS_ENABLED(CONFIG_SUSPEND) 2699 /* don't allow going deep first time followed by s2idle the next time */ 2700 if (adev->last_suspend_state != PM_SUSPEND_ON && 2701 adev->last_suspend_state != pm_suspend_target_state) { 2702 drm_err_once(drm_dev, "Unsupported suspend state %d\n", 2703 pm_suspend_target_state); 2704 return -EINVAL; 2705 } 2706 #endif 2707 return 0; 2708 } 2709 2710 #if IS_ENABLED(CONFIG_SUSPEND) 2711 /* cache the state last used for suspend */ 2712 adev->last_suspend_state = pm_suspend_target_state; 2713 #endif 2714 2715 return amdgpu_device_suspend(drm_dev, true); 2716 } 2717 2718 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2719 { 2720 struct drm_device *drm_dev = dev_get_drvdata(dev); 2721 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2722 int r; 2723 2724 /* 2725 * A GPU parked by vga_switcheroo has no power and no PCIe link, so the 2726 * ASIC reset below would fail and abort the whole noirq suspend phase. 2727 * Bail out like amdgpu_device_prepare/suspend/resume() already do. 2728 */ 2729 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 2730 return 0; 2731 2732 if (amdgpu_acpi_should_gpu_reset(adev)) { 2733 amdgpu_device_lock_reset_domain(adev->reset_domain); 2734 r = amdgpu_asic_reset(adev); 2735 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2736 return r; 2737 } 2738 2739 return 0; 2740 } 2741 2742 static int amdgpu_pmops_resume(struct device *dev) 2743 { 2744 struct drm_device *drm_dev = dev_get_drvdata(dev); 2745 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2746 int r; 2747 2748 if (!adev->in_s0ix && !adev->in_s3) 2749 return 0; 2750 2751 /* Avoids registers access if device is physically gone */ 2752 if (!pci_device_is_present(adev->pdev)) 2753 adev->no_hw_access = true; 2754 2755 r = amdgpu_device_resume(drm_dev, true); 2756 if (amdgpu_acpi_is_s0ix_active(adev)) 2757 adev->in_s0ix = false; 2758 else 2759 adev->in_s3 = false; 2760 return r; 2761 } 2762 2763 static int amdgpu_pmops_freeze(struct device *dev) 2764 { 2765 struct drm_device *drm_dev = dev_get_drvdata(dev); 2766 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2767 int r; 2768 2769 r = amdgpu_device_suspend(drm_dev, true); 2770 if (r) 2771 return r; 2772 2773 if (amdgpu_acpi_should_gpu_reset(adev)) { 2774 amdgpu_device_lock_reset_domain(adev->reset_domain); 2775 r = amdgpu_asic_reset(adev); 2776 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2777 return r; 2778 } 2779 return 0; 2780 } 2781 2782 static int amdgpu_pmops_thaw(struct device *dev) 2783 { 2784 struct drm_device *drm_dev = dev_get_drvdata(dev); 2785 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2786 2787 /* do not resume device if it's normal hibernation */ 2788 if (!adev->debug_hibernation_thaw_resume_gpu && 2789 !pm_hibernate_is_recovering() && 2790 !pm_hibernation_mode_is_suspend()) 2791 return 0; 2792 2793 return amdgpu_device_resume(drm_dev, true); 2794 } 2795 2796 static int amdgpu_pmops_poweroff(struct device *dev) 2797 { 2798 struct drm_device *drm_dev = dev_get_drvdata(dev); 2799 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2800 2801 /* device maybe not resumed here, return immediately in this case */ 2802 if (adev->in_s4 && adev->in_suspend) 2803 return 0; 2804 2805 return amdgpu_device_suspend(drm_dev, true); 2806 } 2807 2808 static int amdgpu_pmops_restore(struct device *dev) 2809 { 2810 struct drm_device *drm_dev = dev_get_drvdata(dev); 2811 2812 return amdgpu_device_resume(drm_dev, true); 2813 } 2814 2815 static int amdgpu_runtime_idle_check_display(struct device *dev) 2816 { 2817 struct pci_dev *pdev = to_pci_dev(dev); 2818 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2819 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2820 2821 if (adev->mode_info.num_crtc) { 2822 struct drm_connector *list_connector; 2823 struct drm_connector_list_iter iter; 2824 int ret = 0; 2825 2826 if (amdgpu_runtime_pm != -2) { 2827 /* XXX: Return busy if any displays are connected to avoid 2828 * possible display wakeups after runtime resume due to 2829 * hotplug events in case any displays were connected while 2830 * the GPU was in suspend. Remove this once that is fixed. 2831 */ 2832 mutex_lock(&drm_dev->mode_config.mutex); 2833 drm_connector_list_iter_begin(drm_dev, &iter); 2834 drm_for_each_connector_iter(list_connector, &iter) { 2835 if (list_connector->status == connector_status_connected) { 2836 ret = -EBUSY; 2837 break; 2838 } 2839 } 2840 drm_connector_list_iter_end(&iter); 2841 mutex_unlock(&drm_dev->mode_config.mutex); 2842 2843 if (ret) 2844 return ret; 2845 } 2846 2847 if (adev->dc_enabled) { 2848 struct drm_crtc *crtc; 2849 2850 drm_for_each_crtc(crtc, drm_dev) { 2851 drm_modeset_lock(&crtc->mutex, NULL); 2852 if (crtc->state->active) 2853 ret = -EBUSY; 2854 drm_modeset_unlock(&crtc->mutex); 2855 if (ret < 0) 2856 break; 2857 } 2858 } else { 2859 mutex_lock(&drm_dev->mode_config.mutex); 2860 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2861 2862 drm_connector_list_iter_begin(drm_dev, &iter); 2863 drm_for_each_connector_iter(list_connector, &iter) { 2864 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2865 ret = -EBUSY; 2866 break; 2867 } 2868 } 2869 2870 drm_connector_list_iter_end(&iter); 2871 2872 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2873 mutex_unlock(&drm_dev->mode_config.mutex); 2874 } 2875 if (ret) 2876 return ret; 2877 } 2878 2879 return 0; 2880 } 2881 2882 static int amdgpu_runtime_idle_check_userq(struct device *dev) 2883 { 2884 struct pci_dev *pdev = to_pci_dev(dev); 2885 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2886 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2887 2888 return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY; 2889 } 2890 2891 static int amdgpu_pmops_runtime_checks(struct device *dev) 2892 { 2893 struct drm_device *drm_dev = dev_get_drvdata(dev); 2894 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2895 int ret; 2896 2897 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2898 pm_runtime_forbid(dev); 2899 return -EBUSY; 2900 } 2901 2902 ret = amdgpu_runtime_idle_check_display(dev); 2903 if (ret) 2904 return ret; 2905 2906 return amdgpu_runtime_idle_check_userq(dev); 2907 } 2908 2909 static int amdgpu_pmops_runtime_idle(struct device *dev) 2910 { 2911 int ret; 2912 2913 ret = amdgpu_pmops_runtime_checks(dev); 2914 pm_runtime_autosuspend(dev); 2915 return ret; 2916 } 2917 2918 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2919 { 2920 struct pci_dev *pdev = to_pci_dev(dev); 2921 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2922 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2923 int ret, i; 2924 2925 ret = amdgpu_pmops_runtime_checks(dev); 2926 if (ret) 2927 return ret; 2928 2929 /* wait for all rings to drain before suspending */ 2930 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2931 struct amdgpu_ring *ring = adev->rings[i]; 2932 2933 if (ring && ring->sched.ready) { 2934 ret = amdgpu_fence_wait_empty(ring); 2935 if (ret) 2936 return -EBUSY; 2937 } 2938 } 2939 2940 adev->in_runpm = true; 2941 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2942 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2943 2944 /* 2945 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2946 * proper cleanups and put itself into a state ready for PNP. That 2947 * can address some random resuming failure observed on BOCO capable 2948 * platforms. 2949 * TODO: this may be also needed for PX capable platform. 2950 */ 2951 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2952 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2953 2954 ret = amdgpu_device_prepare(drm_dev); 2955 if (ret) 2956 return ret; 2957 ret = amdgpu_device_suspend(drm_dev, false); 2958 if (ret) { 2959 adev->in_runpm = false; 2960 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2961 adev->mp1_state = PP_MP1_STATE_NONE; 2962 return ret; 2963 } 2964 2965 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2966 adev->mp1_state = PP_MP1_STATE_NONE; 2967 2968 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2969 /* Only need to handle PCI state in the driver for ATPX 2970 * PCI core handles it for _PR3. 2971 */ 2972 amdgpu_device_cache_pci_state(pdev); 2973 pci_disable_device(pdev); 2974 pci_ignore_hotplug(pdev); 2975 pci_set_power_state(pdev, PCI_D3cold); 2976 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2977 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2978 /* nothing to do */ 2979 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2980 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2981 amdgpu_device_baco_enter(adev); 2982 } 2983 2984 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2985 2986 return 0; 2987 } 2988 2989 static void amdgpu_restore_umd_profile_pstate_after_runpm(struct amdgpu_device *adev) 2990 { 2991 enum amd_dpm_forced_level level; 2992 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2993 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2994 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2995 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2996 2997 level = amdgpu_dpm_get_performance_level(adev); 2998 if (level & profile_mode_mask) 2999 amdgpu_asic_update_umd_stable_pstate(adev, true); 3000 } 3001 3002 static int amdgpu_pmops_runtime_resume(struct device *dev) 3003 { 3004 struct pci_dev *pdev = to_pci_dev(dev); 3005 struct drm_device *drm_dev = pci_get_drvdata(pdev); 3006 struct amdgpu_device *adev = drm_to_adev(drm_dev); 3007 int ret; 3008 3009 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 3010 return -EINVAL; 3011 3012 /* Avoids registers access if device is physically gone */ 3013 if (!pci_device_is_present(adev->pdev)) 3014 adev->no_hw_access = true; 3015 3016 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 3017 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 3018 3019 /* Only need to handle PCI state in the driver for ATPX 3020 * PCI core handles it for _PR3. 3021 */ 3022 pci_set_power_state(pdev, PCI_D0); 3023 amdgpu_device_load_pci_state(pdev); 3024 ret = pci_enable_device(pdev); 3025 if (ret) 3026 return ret; 3027 pci_set_master(pdev); 3028 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 3029 /* Only need to handle PCI state in the driver for ATPX 3030 * PCI core handles it for _PR3. 3031 */ 3032 pci_set_master(pdev); 3033 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3034 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 3035 amdgpu_device_baco_exit(adev); 3036 } 3037 ret = amdgpu_device_resume(drm_dev, false); 3038 if (ret) { 3039 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 3040 pci_disable_device(pdev); 3041 return ret; 3042 } 3043 3044 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 3045 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 3046 3047 amdgpu_restore_umd_profile_pstate_after_runpm(adev); 3048 adev->in_runpm = false; 3049 return 0; 3050 } 3051 3052 static int amdgpu_drm_release(struct inode *inode, struct file *filp) 3053 { 3054 struct drm_file *file_priv = filp->private_data; 3055 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 3056 struct drm_device *dev = file_priv->minor->dev; 3057 int idx; 3058 3059 if (fpriv && drm_dev_enter(dev, &idx)) { 3060 amdgpu_evf_mgr_shutdown(&fpriv->evf_mgr); 3061 amdgpu_userq_mgr_cancel_resume(&fpriv->userq_mgr); 3062 amdgpu_evf_mgr_flush_suspend(&fpriv->evf_mgr); 3063 amdgpu_userq_mgr_fini(&fpriv->userq_mgr); 3064 amdgpu_evf_mgr_fini(&fpriv->evf_mgr); 3065 drm_dev_exit(idx); 3066 } 3067 3068 return drm_release(inode, filp); 3069 } 3070 3071 static const struct dev_pm_ops amdgpu_pm_ops = { 3072 .prepare = pm_sleep_ptr(amdgpu_pmops_prepare), 3073 .complete = pm_sleep_ptr(amdgpu_pmops_complete), 3074 .suspend = pm_sleep_ptr(amdgpu_pmops_suspend), 3075 .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq), 3076 .resume = pm_sleep_ptr(amdgpu_pmops_resume), 3077 .freeze = pm_sleep_ptr(amdgpu_pmops_freeze), 3078 .thaw = pm_sleep_ptr(amdgpu_pmops_thaw), 3079 .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff), 3080 .restore = pm_sleep_ptr(amdgpu_pmops_restore), 3081 .runtime_suspend = amdgpu_pmops_runtime_suspend, 3082 .runtime_resume = amdgpu_pmops_runtime_resume, 3083 .runtime_idle = amdgpu_pmops_runtime_idle, 3084 }; 3085 3086 static int amdgpu_flush(struct file *f, fl_owner_t id) 3087 { 3088 struct drm_file *file_priv = f->private_data; 3089 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 3090 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 3091 3092 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 3093 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 3094 3095 return timeout >= 0 ? 0 : timeout; 3096 } 3097 3098 static const struct file_operations amdgpu_driver_kms_fops = { 3099 .owner = THIS_MODULE, 3100 .open = drm_open, 3101 .flush = amdgpu_flush, 3102 .release = amdgpu_drm_release, 3103 .unlocked_ioctl = drm_ioctl, 3104 .mmap = drm_gem_mmap, 3105 .poll = drm_poll, 3106 .read = drm_read, 3107 #ifdef CONFIG_COMPAT 3108 .compat_ioctl = drm_compat_ioctl, 3109 #endif 3110 #ifdef CONFIG_PROC_FS 3111 .show_fdinfo = drm_show_fdinfo, 3112 #endif 3113 .fop_flags = FOP_UNSIGNED_OFFSET, 3114 }; 3115 3116 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 3117 { 3118 struct drm_file *file; 3119 3120 if (!filp) 3121 return -EINVAL; 3122 3123 if (filp->f_op != &amdgpu_driver_kms_fops) 3124 return -EINVAL; 3125 3126 file = filp->private_data; 3127 *fpriv = file->driver_priv; 3128 return 0; 3129 } 3130 3131 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 3132 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3133 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3134 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3135 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 3136 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3137 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3138 /* KMS */ 3139 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3140 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3141 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3142 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3143 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3144 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3145 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3146 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3147 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3148 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3149 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3150 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3151 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3152 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3153 DRM_IOCTL_DEF_DRV(AMDGPU_PROC_OPTIONS, amdgpu_proc_options_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3154 DRM_IOCTL_DEF_DRV(AMDGPU_UALINK_HANDLE, amdgpu_gem_ualink_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 3155 }; 3156 3157 static const struct drm_driver amdgpu_kms_driver = { 3158 .driver_features = 3159 DRIVER_ATOMIC | 3160 DRIVER_GEM | 3161 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 3162 DRIVER_SYNCOBJ_TIMELINE, 3163 .open = amdgpu_driver_open_kms, 3164 .postclose = amdgpu_driver_postclose_kms, 3165 .ioctls = amdgpu_ioctls_kms, 3166 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3167 .dumb_create = amdgpu_mode_dumb_create, 3168 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3169 DRM_FBDEV_TTM_DRIVER_OPS, 3170 .fops = &amdgpu_driver_kms_fops, 3171 .release = &amdgpu_driver_release_kms, 3172 #ifdef CONFIG_PROC_FS 3173 .show_fdinfo = amdgpu_show_fdinfo, 3174 #endif 3175 3176 .gem_prime_import = amdgpu_gem_prime_import, 3177 3178 .name = DRIVER_NAME, 3179 .desc = DRIVER_DESC, 3180 .major = KMS_DRIVER_MAJOR, 3181 .minor = KMS_DRIVER_MINOR, 3182 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3183 }; 3184 3185 const struct drm_driver amdgpu_partition_driver = { 3186 .driver_features = 3187 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 3188 DRIVER_SYNCOBJ_TIMELINE, 3189 .open = amdgpu_driver_open_kms, 3190 .postclose = amdgpu_driver_postclose_kms, 3191 .ioctls = amdgpu_ioctls_kms, 3192 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3193 .dumb_create = amdgpu_mode_dumb_create, 3194 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3195 DRM_FBDEV_TTM_DRIVER_OPS, 3196 .fops = &amdgpu_driver_kms_fops, 3197 .release = &amdgpu_driver_release_kms, 3198 3199 .gem_prime_import = amdgpu_gem_prime_import, 3200 3201 .name = DRIVER_NAME, 3202 .desc = DRIVER_DESC, 3203 .major = KMS_DRIVER_MAJOR, 3204 .minor = KMS_DRIVER_MINOR, 3205 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3206 }; 3207 3208 static struct pci_error_handlers amdgpu_pci_err_handler = { 3209 .error_detected = amdgpu_pci_error_detected, 3210 .mmio_enabled = amdgpu_pci_mmio_enabled, 3211 .slot_reset = amdgpu_pci_slot_reset, 3212 .resume = amdgpu_pci_resume, 3213 }; 3214 3215 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3216 &amdgpu_vram_mgr_attr_group, 3217 &amdgpu_gtt_mgr_attr_group, 3218 &amdgpu_flash_attr_group, 3219 NULL, 3220 }; 3221 3222 static struct pci_driver amdgpu_kms_pci_driver = { 3223 .name = DRIVER_NAME, 3224 .id_table = pciidlist, 3225 .probe = amdgpu_pci_probe, 3226 .remove = amdgpu_pci_remove, 3227 .shutdown = amdgpu_pci_shutdown, 3228 .driver.pm = pm_ptr(&amdgpu_pm_ops), 3229 .err_handler = &amdgpu_pci_err_handler, 3230 .dev_groups = amdgpu_sysfs_groups, 3231 }; 3232 3233 static int __init amdgpu_init(void) 3234 { 3235 int r; 3236 3237 /* Train lockdep on correct lock ordering */ 3238 amdgpu_lockdep_init(); 3239 3240 r = amdgpu_sync_init(); 3241 if (r) 3242 return r; 3243 3244 amdgpu_register_atpx_handler(); 3245 amdgpu_acpi_detect(); 3246 3247 /* Ignore KFD init failures when CONFIG_HSA_AMD is not set. */ 3248 r = amdgpu_amdkfd_init(); 3249 if (r && r != -ENOENT) 3250 goto error_fini_sync; 3251 3252 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3253 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3254 pr_crit("Overdrive is enabled, please disable it before " 3255 "reporting any bugs unrelated to overdrive.\n"); 3256 } 3257 3258 /* let modprobe override vga console setting */ 3259 return pci_register_driver(&amdgpu_kms_pci_driver); 3260 3261 error_fini_sync: 3262 amdgpu_sync_fini(); 3263 return r; 3264 } 3265 3266 static void __exit amdgpu_exit(void) 3267 { 3268 amdgpu_amdkfd_fini(); 3269 pci_unregister_driver(&amdgpu_kms_pci_driver); 3270 amdgpu_unregister_atpx_handler(); 3271 amdgpu_acpi_release(); 3272 amdgpu_sync_fini(); 3273 mmu_notifier_synchronize(); 3274 amdgpu_xcp_drv_release(); 3275 3276 /* 3277 * Flush outstanding call_rcu() callbacks before the 3278 * module text is freed. Otherwise a grace period elapsing after 3279 * unload invokes a callback in already-freed module memory and 3280 * faults in rcu_do_batch(). 3281 */ 3282 rcu_barrier(); 3283 } 3284 3285 module_init(amdgpu_init); 3286 module_exit(amdgpu_exit); 3287 3288 MODULE_AUTHOR(DRIVER_AUTHOR); 3289 MODULE_DESCRIPTION(DRIVER_DESC); 3290 MODULE_LICENSE("GPL and additional rights"); 3291