1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ADXL380 3-Axis Digital Accelerometer core driver
4 *
5 * Copyright 2024 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/property.h>
13 #include <linux/regmap.h>
14 #include <linux/units.h>
15
16 #include <linux/unaligned.h>
17
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/events.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/kfifo_buf.h>
22 #include <linux/iio/sysfs.h>
23
24 #include <linux/regulator/consumer.h>
25
26 #include "adxl380.h"
27
28 #define ADXL380_ID_VAL 380
29 #define ADXL318_ID_VAL 380
30 #define ADXL382_ID_VAL 382
31 #define ADXL319_ID_VAL 382
32
33 #define ADXL380_DEVID_AD_REG 0x00
34 #define ADLX380_PART_ID_REG 0x02
35
36 #define ADXL380_X_DATA_H_REG 0x15
37 #define ADXL380_Y_DATA_H_REG 0x17
38 #define ADXL380_Z_DATA_H_REG 0x19
39 #define ADXL380_T_DATA_H_REG 0x1B
40
41 #define ADXL380_MISC_0_REG 0x20
42 #define ADXL380_XL382_MSK BIT(7)
43
44 #define ADXL380_MISC_1_REG 0x21
45
46 #define ADXL380_X_DSM_OFFSET_REG 0x4D
47
48 #define ADXL380_ACT_INACT_CTL_REG 0x37
49 #define ADXL380_INACT_EN_MSK BIT(2)
50 #define ADXL380_ACT_EN_MSK BIT(0)
51
52 #define ADXL380_SNSR_AXIS_EN_REG 0x38
53 #define ADXL380_ACT_INACT_AXIS_EN_MSK GENMASK(2, 0)
54
55 #define ADXL380_THRESH_ACT_H_REG 0x39
56 #define ADXL380_TIME_ACT_H_REG 0x3B
57 #define ADXL380_THRESH_INACT_H_REG 0x3E
58 #define ADXL380_TIME_INACT_H_REG 0x40
59 #define ADXL380_THRESH_MAX GENMASK(12, 0)
60 #define ADXL380_TIME_MAX GENMASK(24, 0)
61
62 #define ADXL380_FIFO_CONFIG_0_REG 0x30
63 #define ADXL380_FIFO_SAMPLES_8_MSK BIT(0)
64 #define ADXL380_FIFO_MODE_MSK GENMASK(5, 4)
65
66 #define ADXL380_FIFO_DISABLED 0
67 #define ADXL380_FIFO_NORMAL 1
68 #define ADXL380_FIFO_STREAMED 2
69 #define ADXL380_FIFO_TRIGGERED 3
70
71 #define ADXL380_FIFO_CONFIG_1_REG 0x31
72 #define ADXL380_FIFO_STATUS_0_REG 0x1E
73
74 #define ADXL380_TAP_THRESH_REG 0x43
75 #define ADXL380_TAP_DUR_REG 0x44
76 #define ADXL380_TAP_LATENT_REG 0x45
77 #define ADXL380_TAP_WINDOW_REG 0x46
78 #define ADXL380_TAP_TIME_MAX GENMASK(7, 0)
79
80 #define ADXL380_TAP_CFG_REG 0x47
81 #define ADXL380_TAP_AXIS_MSK GENMASK(1, 0)
82
83 #define ADXL380_TRIG_CFG_REG 0x49
84 #define ADXL380_TRIG_CFG_DEC_2X_MSK BIT(7)
85 #define ADXL380_TRIG_CFG_SINC_RATE_MSK BIT(6)
86
87 #define ADXL380_FILTER_REG 0x50
88 #define ADXL380_FILTER_EQ_FILT_MSK BIT(6)
89 #define ADXL380_FILTER_LPF_MODE_MSK GENMASK(5, 4)
90 #define ADXL380_FILTER_HPF_PATH_MSK BIT(3)
91 #define ADXL380_FILTER_HPF_CORNER_MSK GENMASK(2, 0)
92
93 #define ADXL380_OP_MODE_REG 0x26
94 #define ADXL380_OP_MODE_RANGE_MSK GENMASK(7, 6)
95 #define ADXL380_OP_MODE_MSK GENMASK(3, 0)
96 #define ADXL380_OP_MODE_STANDBY 0
97 #define ADXL380_OP_MODE_HEART_SOUND 1
98 #define ADXL380_OP_MODE_ULP 2
99 #define ADXL380_OP_MODE_VLP 3
100 #define ADXL380_OP_MODE_LP 4
101 #define ADXL380_OP_MODE_LP_ULP 6
102 #define ADXL380_OP_MODE_LP_VLP 7
103 #define ADXL380_OP_MODE_RBW 8
104 #define ADXL380_OP_MODE_RBW_ULP 10
105 #define ADXL380_OP_MODE_RBW_VLP 11
106 #define ADXL380_OP_MODE_HP 12
107 #define ADXL380_OP_MODE_HP_ULP 14
108 #define ADXL380_OP_MODE_HP_VLP 15
109
110 #define ADXL380_OP_MODE_4G_RANGE 0
111 #define ADXL382_OP_MODE_15G_RANGE 0
112 #define ADXL380_OP_MODE_8G_RANGE 1
113 #define ADXL382_OP_MODE_30G_RANGE 1
114 #define ADXL380_OP_MODE_16G_RANGE 2
115 #define ADXL382_OP_MODE_60G_RANGE 2
116
117 #define ADXL380_DIG_EN_REG 0x27
118 #define ADXL380_CHAN_EN_MSK(chan) BIT(4 + (chan))
119 #define ADXL380_FIFO_EN_MSK BIT(3)
120
121 #define ADXL380_INT0_MAP0_REG 0x2B
122 #define ADXL380_INT1_MAP0_REG 0x2D
123 #define ADXL380_INT_MAP0_INACT_INT0_MSK BIT(6)
124 #define ADXL380_INT_MAP0_ACT_INT0_MSK BIT(5)
125 #define ADXL380_INT_MAP0_FIFO_WM_INT0_MSK BIT(3)
126
127 #define ADXL380_INT0_MAP1_REG 0x2C
128 #define ADXL380_INT1_MAP1_REG 0x2E
129 #define ADXL380_INT_MAP1_DOUBLE_TAP_INT0_MSK BIT(1)
130 #define ADXL380_INT_MAP1_SINGLE_TAP_INT0_MSK BIT(0)
131
132 #define ADXL380_INT0_REG 0x5D
133 #define ADXL380_INT0_POL_MSK BIT(7)
134
135 #define ADXL380_RESET_REG 0x2A
136 #define ADXL380_FIFO_DATA 0x1D
137
138 #define ADXL380_DEVID_AD_VAL 0xAD
139 #define ADXL380_RESET_CODE 0x52
140
141 #define ADXL380_STATUS_0_REG 0x11
142 #define ADXL380_STATUS_0_FIFO_FULL_MSK BIT(1)
143 #define ADXL380_STATUS_0_FIFO_WM_MSK BIT(3)
144
145 #define ADXL380_STATUS_1_INACT_MSK BIT(6)
146 #define ADXL380_STATUS_1_ACT_MSK BIT(5)
147 #define ADXL380_STATUS_1_DOUBLE_TAP_MSK BIT(1)
148 #define ADXL380_STATUS_1_SINGLE_TAP_MSK BIT(0)
149
150 #define ADXL380_FIFO_SAMPLES 315UL
151
152 enum adxl380_channels {
153 ADXL380_ACCEL_X,
154 ADXL380_ACCEL_Y,
155 ADXL380_ACCEL_Z,
156 ADXL380_TEMP,
157 ADXL380_CH_NUM
158 };
159
160 enum adxl380_axis {
161 ADXL380_X_AXIS,
162 ADXL380_Y_AXIS,
163 ADXL380_Z_AXIS,
164 };
165
166 enum adxl380_activity_type {
167 ADXL380_ACTIVITY,
168 ADXL380_INACTIVITY,
169 };
170
171 enum adxl380_tap_type {
172 ADXL380_SINGLE_TAP,
173 ADXL380_DOUBLE_TAP,
174 };
175
176 enum adxl380_tap_time_type {
177 ADXL380_TAP_TIME_LATENT,
178 ADXL380_TAP_TIME_WINDOW,
179 };
180
181 static const int adxl380_range_scale_factor_tbl[] = { 1, 2, 4 };
182
183 static const unsigned int adxl380_th_reg_high_addr[2] = {
184 [ADXL380_ACTIVITY] = ADXL380_THRESH_ACT_H_REG,
185 [ADXL380_INACTIVITY] = ADXL380_THRESH_INACT_H_REG,
186 };
187
188 static const unsigned int adxl380_time_reg_high_addr[2] = {
189 [ADXL380_ACTIVITY] = ADXL380_TIME_ACT_H_REG,
190 [ADXL380_INACTIVITY] = ADXL380_TIME_INACT_H_REG,
191 };
192
193 static const unsigned int adxl380_tap_time_reg[2] = {
194 [ADXL380_TAP_TIME_LATENT] = ADXL380_TAP_LATENT_REG,
195 [ADXL380_TAP_TIME_WINDOW] = ADXL380_TAP_WINDOW_REG,
196 };
197
198 struct adxl380_state {
199 struct regmap *regmap;
200 struct device *dev;
201 const struct adxl380_chip_info *chip_info;
202 /*
203 * Synchronize access to members of driver state, and ensure atomicity
204 * of consecutive regmap operations.
205 */
206 struct mutex lock;
207 enum adxl380_axis tap_axis_en;
208 u8 range;
209 u8 odr;
210 u8 fifo_set_size;
211 u8 transf_buf[3];
212 u16 watermark;
213 u32 act_time_ms;
214 u32 act_threshold;
215 u32 inact_time_ms;
216 u32 inact_threshold;
217 u32 tap_latent_us;
218 u32 tap_window_us;
219 u32 tap_duration_us;
220 u32 tap_threshold;
221 int irq;
222 int int_map[2];
223 int lpf_tbl[4];
224 int hpf_tbl[7][2];
225
226 __be16 fifo_buf[ADXL380_FIFO_SAMPLES] __aligned(IIO_DMA_MINALIGN);
227 };
228
adxl380_readable_noinc_reg(struct device * dev,unsigned int reg)229 bool adxl380_readable_noinc_reg(struct device *dev, unsigned int reg)
230 {
231 return reg == ADXL380_FIFO_DATA;
232 }
233 EXPORT_SYMBOL_NS_GPL(adxl380_readable_noinc_reg, "IIO_ADXL380");
234
adxl380_set_measure_en(struct adxl380_state * st,bool en)235 static int adxl380_set_measure_en(struct adxl380_state *st, bool en)
236 {
237 int ret;
238 unsigned int act_inact_ctl;
239 u8 op_mode = ADXL380_OP_MODE_STANDBY;
240
241 if (en) {
242 ret = regmap_read(st->regmap, ADXL380_ACT_INACT_CTL_REG, &act_inact_ctl);
243 if (ret)
244 return ret;
245
246 /*
247 * Activity/Inactivity detection available only in VLP/ULP
248 * mode and for devices that support low power modes. Otherwise
249 * go straight to measure mode (same bits as ADXL380_OP_MODE_HP).
250 */
251 if (st->chip_info->has_low_power &&
252 (FIELD_GET(ADXL380_ACT_EN_MSK, act_inact_ctl) ||
253 FIELD_GET(ADXL380_INACT_EN_MSK, act_inact_ctl)))
254 op_mode = ADXL380_OP_MODE_VLP;
255 else
256 op_mode = ADXL380_OP_MODE_HP;
257 }
258
259 return regmap_update_bits(st->regmap, ADXL380_OP_MODE_REG,
260 ADXL380_OP_MODE_MSK,
261 FIELD_PREP(ADXL380_OP_MODE_MSK, op_mode));
262 }
263
adxl380_scale_act_inact_thresholds(struct adxl380_state * st,u8 old_range,u8 new_range)264 static void adxl380_scale_act_inact_thresholds(struct adxl380_state *st,
265 u8 old_range,
266 u8 new_range)
267 {
268 st->act_threshold = mult_frac(st->act_threshold,
269 adxl380_range_scale_factor_tbl[old_range],
270 adxl380_range_scale_factor_tbl[new_range]);
271 st->inact_threshold = mult_frac(st->inact_threshold,
272 adxl380_range_scale_factor_tbl[old_range],
273 adxl380_range_scale_factor_tbl[new_range]);
274 }
275
adxl380_write_act_inact_threshold(struct adxl380_state * st,enum adxl380_activity_type act,unsigned int th)276 static int adxl380_write_act_inact_threshold(struct adxl380_state *st,
277 enum adxl380_activity_type act,
278 unsigned int th)
279 {
280 int ret;
281 u8 reg = adxl380_th_reg_high_addr[act];
282
283 if (th > ADXL380_THRESH_MAX)
284 return -EINVAL;
285
286 ret = regmap_write(st->regmap, reg + 1, th & GENMASK(7, 0));
287 if (ret)
288 return ret;
289
290 ret = regmap_update_bits(st->regmap, reg, GENMASK(2, 0), th >> 8);
291 if (ret)
292 return ret;
293
294 if (act == ADXL380_ACTIVITY)
295 st->act_threshold = th;
296 else
297 st->inact_threshold = th;
298
299 return 0;
300 }
301
adxl380_set_act_inact_threshold(struct iio_dev * indio_dev,enum adxl380_activity_type act,u16 th)302 static int adxl380_set_act_inact_threshold(struct iio_dev *indio_dev,
303 enum adxl380_activity_type act,
304 u16 th)
305 {
306 struct adxl380_state *st = iio_priv(indio_dev);
307 int ret;
308
309 guard(mutex)(&st->lock);
310
311 ret = adxl380_set_measure_en(st, false);
312 if (ret)
313 return ret;
314
315 ret = adxl380_write_act_inact_threshold(st, act, th);
316 if (ret)
317 return ret;
318
319 return adxl380_set_measure_en(st, true);
320 }
321
adxl380_set_tap_threshold_value(struct iio_dev * indio_dev,u8 th)322 static int adxl380_set_tap_threshold_value(struct iio_dev *indio_dev, u8 th)
323 {
324 int ret;
325 struct adxl380_state *st = iio_priv(indio_dev);
326
327 guard(mutex)(&st->lock);
328
329 ret = adxl380_set_measure_en(st, false);
330 if (ret)
331 return ret;
332
333 ret = regmap_write(st->regmap, ADXL380_TAP_THRESH_REG, th);
334 if (ret)
335 return ret;
336
337 st->tap_threshold = th;
338
339 return adxl380_set_measure_en(st, true);
340 }
341
_adxl380_write_tap_time_us(struct adxl380_state * st,enum adxl380_tap_time_type tap_time_type,u32 us)342 static int _adxl380_write_tap_time_us(struct adxl380_state *st,
343 enum adxl380_tap_time_type tap_time_type,
344 u32 us)
345 {
346 u8 reg = adxl380_tap_time_reg[tap_time_type];
347 unsigned int reg_val;
348 int ret;
349
350 /* scale factor for tap window is 1250us / LSB */
351 reg_val = DIV_ROUND_CLOSEST(us, 1250);
352 if (reg_val > ADXL380_TAP_TIME_MAX)
353 reg_val = ADXL380_TAP_TIME_MAX;
354
355 ret = regmap_write(st->regmap, reg, reg_val);
356 if (ret)
357 return ret;
358
359 if (tap_time_type == ADXL380_TAP_TIME_WINDOW)
360 st->tap_window_us = us;
361 else
362 st->tap_latent_us = us;
363
364 return 0;
365 }
366
adxl380_write_tap_time_us(struct adxl380_state * st,enum adxl380_tap_time_type tap_time_type,u32 us)367 static int adxl380_write_tap_time_us(struct adxl380_state *st,
368 enum adxl380_tap_time_type tap_time_type, u32 us)
369 {
370 int ret;
371
372 guard(mutex)(&st->lock);
373
374 ret = adxl380_set_measure_en(st, false);
375 if (ret)
376 return ret;
377
378 ret = _adxl380_write_tap_time_us(st, tap_time_type, us);
379 if (ret)
380 return ret;
381
382 return adxl380_set_measure_en(st, true);
383 }
384
adxl380_write_tap_dur_us(struct iio_dev * indio_dev,u32 us)385 static int adxl380_write_tap_dur_us(struct iio_dev *indio_dev, u32 us)
386 {
387 int ret;
388 unsigned int reg_val;
389 struct adxl380_state *st = iio_priv(indio_dev);
390
391 /* 625us per code is the scale factor of TAP_DUR register */
392 reg_val = DIV_ROUND_CLOSEST(us, 625);
393
394 ret = adxl380_set_measure_en(st, false);
395 if (ret)
396 return ret;
397
398 ret = regmap_write(st->regmap, ADXL380_TAP_DUR_REG, reg_val);
399 if (ret)
400 return ret;
401
402 return adxl380_set_measure_en(st, true);
403 }
404
adxl380_read_chn(struct adxl380_state * st,u8 addr)405 static int adxl380_read_chn(struct adxl380_state *st, u8 addr)
406 {
407 int ret;
408
409 guard(mutex)(&st->lock);
410
411 ret = regmap_bulk_read(st->regmap, addr, &st->transf_buf, 2);
412 if (ret)
413 return ret;
414
415 return get_unaligned_be16(st->transf_buf);
416 }
417
adxl380_get_odr(struct adxl380_state * st,int * odr)418 static int adxl380_get_odr(struct adxl380_state *st, int *odr)
419 {
420 int ret;
421 unsigned int trig_cfg, odr_idx;
422
423 ret = regmap_read(st->regmap, ADXL380_TRIG_CFG_REG, &trig_cfg);
424 if (ret)
425 return ret;
426
427 odr_idx = (FIELD_GET(ADXL380_TRIG_CFG_SINC_RATE_MSK, trig_cfg) << 1) |
428 (FIELD_GET(ADXL380_TRIG_CFG_DEC_2X_MSK, trig_cfg) & 1);
429
430 *odr = st->chip_info->samp_freq_tbl[odr_idx];
431
432 return 0;
433 }
434
435 static const int adxl380_lpf_div[] = {
436 1, 4, 8, 16,
437 };
438
adxl380_fill_lpf_tbl(struct adxl380_state * st)439 static int adxl380_fill_lpf_tbl(struct adxl380_state *st)
440 {
441 int ret, i;
442 int odr;
443
444 ret = adxl380_get_odr(st, &odr);
445 if (ret)
446 return ret;
447
448 for (i = 0; i < ARRAY_SIZE(st->lpf_tbl); i++)
449 st->lpf_tbl[i] = DIV_ROUND_CLOSEST(odr, adxl380_lpf_div[i]);
450
451 return 0;
452 }
453
454 static const int adxl380_hpf_mul[] = {
455 0, 247000, 62084, 15545, 3862, 954, 238,
456 };
457
adxl380_fill_hpf_tbl(struct adxl380_state * st)458 static int adxl380_fill_hpf_tbl(struct adxl380_state *st)
459 {
460 int i, ret, odr_hz;
461 u32 multiplier;
462 u64 div, rem, odr;
463
464 ret = adxl380_get_odr(st, &odr_hz);
465 if (ret)
466 return ret;
467
468 for (i = 0; i < ARRAY_SIZE(adxl380_hpf_mul); i++) {
469 odr = mul_u64_u32_shr(odr_hz, MEGA, 0);
470 multiplier = adxl380_hpf_mul[i];
471 div = div64_u64_rem(mul_u64_u32_shr(odr, multiplier, 0),
472 TERA * 100, &rem);
473
474 st->hpf_tbl[i][0] = div;
475 st->hpf_tbl[i][1] = div_u64(rem, MEGA * 100);
476 }
477
478 return 0;
479 }
480
adxl380_set_odr(struct adxl380_state * st,u8 odr)481 static int adxl380_set_odr(struct adxl380_state *st, u8 odr)
482 {
483 int ret;
484
485 guard(mutex)(&st->lock);
486
487 ret = adxl380_set_measure_en(st, false);
488 if (ret)
489 return ret;
490
491 ret = regmap_update_bits(st->regmap, ADXL380_TRIG_CFG_REG,
492 ADXL380_TRIG_CFG_DEC_2X_MSK,
493 FIELD_PREP(ADXL380_TRIG_CFG_DEC_2X_MSK, odr & 1));
494 if (ret)
495 return ret;
496
497 ret = regmap_update_bits(st->regmap, ADXL380_TRIG_CFG_REG,
498 ADXL380_TRIG_CFG_SINC_RATE_MSK,
499 FIELD_PREP(ADXL380_TRIG_CFG_SINC_RATE_MSK, odr >> 1));
500 if (ret)
501 return ret;
502
503 ret = adxl380_set_measure_en(st, true);
504 if (ret)
505 return ret;
506
507 ret = adxl380_fill_lpf_tbl(st);
508 if (ret)
509 return ret;
510
511 return adxl380_fill_hpf_tbl(st);
512 }
513
adxl380_find_match_1d_tbl(const int * array,unsigned int size,int val)514 static int adxl380_find_match_1d_tbl(const int *array, unsigned int size,
515 int val)
516 {
517 int i;
518
519 for (i = 0; i < size; i++) {
520 if (val == array[i])
521 return i;
522 }
523
524 return size - 1;
525 }
526
adxl380_find_match_2d_tbl(const int (* freq_tbl)[2],int n,int val,int val2)527 static int adxl380_find_match_2d_tbl(const int (*freq_tbl)[2], int n, int val, int val2)
528 {
529 int i;
530
531 for (i = 0; i < n; i++) {
532 if (freq_tbl[i][0] == val && freq_tbl[i][1] == val2)
533 return i;
534 }
535
536 return -EINVAL;
537 }
538
adxl380_get_lpf(struct adxl380_state * st,int * lpf)539 static int adxl380_get_lpf(struct adxl380_state *st, int *lpf)
540 {
541 int ret;
542 unsigned int trig_cfg, lpf_idx;
543
544 guard(mutex)(&st->lock);
545
546 ret = regmap_read(st->regmap, ADXL380_FILTER_REG, &trig_cfg);
547 if (ret)
548 return ret;
549
550 lpf_idx = FIELD_GET(ADXL380_FILTER_LPF_MODE_MSK, trig_cfg);
551
552 *lpf = st->lpf_tbl[lpf_idx];
553
554 return 0;
555 }
556
adxl380_set_lpf(struct adxl380_state * st,u8 lpf)557 static int adxl380_set_lpf(struct adxl380_state *st, u8 lpf)
558 {
559 int ret;
560 u8 eq_bypass = 0;
561
562 guard(mutex)(&st->lock);
563
564 ret = adxl380_set_measure_en(st, false);
565 if (ret)
566 return ret;
567
568 if (lpf)
569 eq_bypass = 1;
570
571 ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,
572 ADXL380_FILTER_EQ_FILT_MSK,
573 FIELD_PREP(ADXL380_FILTER_EQ_FILT_MSK, eq_bypass));
574 if (ret)
575 return ret;
576
577 ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,
578 ADXL380_FILTER_LPF_MODE_MSK,
579 FIELD_PREP(ADXL380_FILTER_LPF_MODE_MSK, lpf));
580 if (ret)
581 return ret;
582
583 return adxl380_set_measure_en(st, true);
584 }
585
adxl380_get_hpf(struct adxl380_state * st,int * hpf_int,int * hpf_frac)586 static int adxl380_get_hpf(struct adxl380_state *st, int *hpf_int, int *hpf_frac)
587 {
588 int ret;
589 unsigned int trig_cfg, hpf_idx;
590
591 guard(mutex)(&st->lock);
592
593 ret = regmap_read(st->regmap, ADXL380_FILTER_REG, &trig_cfg);
594 if (ret)
595 return ret;
596
597 hpf_idx = FIELD_GET(ADXL380_FILTER_HPF_CORNER_MSK, trig_cfg);
598
599 *hpf_int = st->hpf_tbl[hpf_idx][0];
600 *hpf_frac = st->hpf_tbl[hpf_idx][1];
601
602 return 0;
603 }
604
adxl380_set_hpf(struct adxl380_state * st,u8 hpf)605 static int adxl380_set_hpf(struct adxl380_state *st, u8 hpf)
606 {
607 int ret;
608 u8 hpf_path = 0;
609
610 guard(mutex)(&st->lock);
611
612 ret = adxl380_set_measure_en(st, false);
613 if (ret)
614 return ret;
615
616 if (hpf)
617 hpf_path = 1;
618
619 ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,
620 ADXL380_FILTER_HPF_PATH_MSK,
621 FIELD_PREP(ADXL380_FILTER_HPF_PATH_MSK, hpf_path));
622 if (ret)
623 return ret;
624
625 ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,
626 ADXL380_FILTER_HPF_CORNER_MSK,
627 FIELD_PREP(ADXL380_FILTER_HPF_CORNER_MSK, hpf));
628 if (ret)
629 return ret;
630
631 return adxl380_set_measure_en(st, true);
632 }
633
_adxl380_set_act_inact_time_ms(struct adxl380_state * st,enum adxl380_activity_type act,u32 ms)634 static int _adxl380_set_act_inact_time_ms(struct adxl380_state *st,
635 enum adxl380_activity_type act,
636 u32 ms)
637 {
638 u8 reg = adxl380_time_reg_high_addr[act];
639 unsigned int reg_val;
640 int ret;
641
642 /* 500us per code is the scale factor of TIME_ACT / TIME_INACT registers */
643 reg_val = min(DIV_ROUND_CLOSEST(ms * 1000, 500), ADXL380_TIME_MAX);
644
645 put_unaligned_be24(reg_val, &st->transf_buf[0]);
646
647 ret = regmap_bulk_write(st->regmap, reg, st->transf_buf, sizeof(st->transf_buf));
648 if (ret)
649 return ret;
650
651 if (act == ADXL380_ACTIVITY)
652 st->act_time_ms = ms;
653 else
654 st->inact_time_ms = ms;
655
656 return 0;
657 }
658
adxl380_set_act_inact_time_ms(struct adxl380_state * st,enum adxl380_activity_type act,u32 ms)659 static int adxl380_set_act_inact_time_ms(struct adxl380_state *st,
660 enum adxl380_activity_type act,
661 u32 ms)
662 {
663 int ret;
664
665 guard(mutex)(&st->lock);
666
667 ret = adxl380_set_measure_en(st, false);
668 if (ret)
669 return ret;
670
671 ret = _adxl380_set_act_inact_time_ms(st, act, ms);
672 if (ret)
673 return ret;
674
675 return adxl380_set_measure_en(st, true);
676 }
677
adxl380_set_range(struct adxl380_state * st,u8 range)678 static int adxl380_set_range(struct adxl380_state *st, u8 range)
679 {
680 int ret;
681
682 guard(mutex)(&st->lock);
683
684 ret = adxl380_set_measure_en(st, false);
685 if (ret)
686 return ret;
687
688 ret = regmap_update_bits(st->regmap, ADXL380_OP_MODE_REG,
689 ADXL380_OP_MODE_RANGE_MSK,
690 FIELD_PREP(ADXL380_OP_MODE_RANGE_MSK, range));
691
692 if (ret)
693 return ret;
694
695 adxl380_scale_act_inact_thresholds(st, st->range, range);
696
697 /* Activity thresholds depend on range */
698 ret = adxl380_write_act_inact_threshold(st, ADXL380_ACTIVITY,
699 st->act_threshold);
700 if (ret)
701 return ret;
702
703 ret = adxl380_write_act_inact_threshold(st, ADXL380_INACTIVITY,
704 st->inact_threshold);
705 if (ret)
706 return ret;
707
708 st->range = range;
709
710 return adxl380_set_measure_en(st, true);
711 }
712
adxl380_write_act_inact_en(struct adxl380_state * st,enum adxl380_activity_type type,bool en)713 static int adxl380_write_act_inact_en(struct adxl380_state *st,
714 enum adxl380_activity_type type,
715 bool en)
716 {
717 if (type == ADXL380_ACTIVITY)
718 return regmap_update_bits(st->regmap, ADXL380_ACT_INACT_CTL_REG,
719 ADXL380_ACT_EN_MSK,
720 FIELD_PREP(ADXL380_ACT_EN_MSK, en));
721
722 return regmap_update_bits(st->regmap, ADXL380_ACT_INACT_CTL_REG,
723 ADXL380_INACT_EN_MSK,
724 FIELD_PREP(ADXL380_INACT_EN_MSK, en));
725 }
726
adxl380_read_act_inact_int(struct adxl380_state * st,enum adxl380_activity_type type,bool * en)727 static int adxl380_read_act_inact_int(struct adxl380_state *st,
728 enum adxl380_activity_type type,
729 bool *en)
730 {
731 int ret;
732 unsigned int reg_val;
733
734 guard(mutex)(&st->lock);
735
736 ret = regmap_read(st->regmap, st->int_map[0], ®_val);
737 if (ret)
738 return ret;
739
740 if (type == ADXL380_ACTIVITY)
741 *en = FIELD_GET(ADXL380_INT_MAP0_ACT_INT0_MSK, reg_val);
742 else
743 *en = FIELD_GET(ADXL380_INT_MAP0_INACT_INT0_MSK, reg_val);
744
745 return 0;
746 }
747
adxl380_write_act_inact_int(struct adxl380_state * st,enum adxl380_activity_type act,bool en)748 static int adxl380_write_act_inact_int(struct adxl380_state *st,
749 enum adxl380_activity_type act,
750 bool en)
751 {
752 if (act == ADXL380_ACTIVITY)
753 return regmap_update_bits(st->regmap, st->int_map[0],
754 ADXL380_INT_MAP0_ACT_INT0_MSK,
755 FIELD_PREP(ADXL380_INT_MAP0_ACT_INT0_MSK, en));
756
757 return regmap_update_bits(st->regmap, st->int_map[0],
758 ADXL380_INT_MAP0_INACT_INT0_MSK,
759 FIELD_PREP(ADXL380_INT_MAP0_INACT_INT0_MSK, en));
760 }
761
adxl380_act_inact_config(struct adxl380_state * st,enum adxl380_activity_type type,bool en)762 static int adxl380_act_inact_config(struct adxl380_state *st,
763 enum adxl380_activity_type type,
764 bool en)
765 {
766 int ret;
767
768 guard(mutex)(&st->lock);
769
770 ret = adxl380_set_measure_en(st, false);
771 if (ret)
772 return ret;
773
774 ret = adxl380_write_act_inact_en(st, type, en);
775 if (ret)
776 return ret;
777
778 ret = adxl380_write_act_inact_int(st, type, en);
779 if (ret)
780 return ret;
781
782 return adxl380_set_measure_en(st, true);
783 }
784
adxl380_write_tap_axis(struct adxl380_state * st,enum adxl380_axis axis)785 static int adxl380_write_tap_axis(struct adxl380_state *st,
786 enum adxl380_axis axis)
787 {
788 int ret;
789
790 ret = regmap_update_bits(st->regmap, ADXL380_TAP_CFG_REG,
791 ADXL380_TAP_AXIS_MSK,
792 FIELD_PREP(ADXL380_TAP_AXIS_MSK, axis));
793
794 if (ret)
795 return ret;
796
797 st->tap_axis_en = axis;
798
799 return 0;
800 }
801
adxl380_read_tap_int(struct adxl380_state * st,enum adxl380_tap_type type,bool * en)802 static int adxl380_read_tap_int(struct adxl380_state *st, enum adxl380_tap_type type, bool *en)
803 {
804 int ret;
805 unsigned int reg_val;
806
807 ret = regmap_read(st->regmap, st->int_map[1], ®_val);
808 if (ret)
809 return ret;
810
811 if (type == ADXL380_SINGLE_TAP)
812 *en = FIELD_GET(ADXL380_INT_MAP1_SINGLE_TAP_INT0_MSK, reg_val);
813 else
814 *en = FIELD_GET(ADXL380_INT_MAP1_DOUBLE_TAP_INT0_MSK, reg_val);
815
816 return 0;
817 }
818
adxl380_write_tap_int(struct adxl380_state * st,enum adxl380_tap_type type,bool en)819 static int adxl380_write_tap_int(struct adxl380_state *st, enum adxl380_tap_type type, bool en)
820 {
821 if (type == ADXL380_SINGLE_TAP)
822 return regmap_update_bits(st->regmap, st->int_map[1],
823 ADXL380_INT_MAP1_SINGLE_TAP_INT0_MSK,
824 FIELD_PREP(ADXL380_INT_MAP1_SINGLE_TAP_INT0_MSK, en));
825
826 return regmap_update_bits(st->regmap, st->int_map[1],
827 ADXL380_INT_MAP1_DOUBLE_TAP_INT0_MSK,
828 FIELD_PREP(ADXL380_INT_MAP1_DOUBLE_TAP_INT0_MSK, en));
829 }
830
adxl380_tap_config(struct adxl380_state * st,enum adxl380_axis axis,enum adxl380_tap_type type,bool en)831 static int adxl380_tap_config(struct adxl380_state *st,
832 enum adxl380_axis axis,
833 enum adxl380_tap_type type,
834 bool en)
835 {
836 int ret;
837
838 guard(mutex)(&st->lock);
839
840 ret = adxl380_set_measure_en(st, false);
841 if (ret)
842 return ret;
843
844 ret = adxl380_write_tap_axis(st, axis);
845 if (ret)
846 return ret;
847
848 ret = adxl380_write_tap_int(st, type, en);
849 if (ret)
850 return ret;
851
852 return adxl380_set_measure_en(st, true);
853 }
854
adxl380_set_fifo_samples(struct adxl380_state * st)855 static int adxl380_set_fifo_samples(struct adxl380_state *st)
856 {
857 int ret;
858 u16 fifo_samples = st->watermark * st->fifo_set_size;
859
860 ret = regmap_update_bits(st->regmap, ADXL380_FIFO_CONFIG_0_REG,
861 ADXL380_FIFO_SAMPLES_8_MSK,
862 FIELD_PREP(ADXL380_FIFO_SAMPLES_8_MSK,
863 (fifo_samples & BIT(8))));
864 if (ret)
865 return ret;
866
867 return regmap_write(st->regmap, ADXL380_FIFO_CONFIG_1_REG,
868 fifo_samples & 0xFF);
869 }
870
adxl380_get_status(struct adxl380_state * st,u8 * status0,u8 * status1)871 static int adxl380_get_status(struct adxl380_state *st, u8 *status0, u8 *status1)
872 {
873 int ret;
874
875 /* STATUS0, STATUS1 are adjacent regs */
876 ret = regmap_bulk_read(st->regmap, ADXL380_STATUS_0_REG,
877 &st->transf_buf, 2);
878 if (ret)
879 return ret;
880
881 *status0 = st->transf_buf[0];
882 *status1 = st->transf_buf[1];
883
884 return 0;
885 }
886
adxl380_get_fifo_entries(struct adxl380_state * st,u16 * fifo_entries)887 static int adxl380_get_fifo_entries(struct adxl380_state *st, u16 *fifo_entries)
888 {
889 int ret;
890
891 ret = regmap_bulk_read(st->regmap, ADXL380_FIFO_STATUS_0_REG,
892 &st->transf_buf, 2);
893 if (ret)
894 return ret;
895
896 *fifo_entries = st->transf_buf[0] | ((BIT(0) & st->transf_buf[1]) << 8);
897
898 return 0;
899 }
900
adxl380_push_event(struct iio_dev * indio_dev,s64 timestamp,u8 status1)901 static void adxl380_push_event(struct iio_dev *indio_dev, s64 timestamp,
902 u8 status1)
903 {
904 if (FIELD_GET(ADXL380_STATUS_1_ACT_MSK, status1))
905 iio_push_event(indio_dev,
906 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
907 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
908 timestamp);
909
910 if (FIELD_GET(ADXL380_STATUS_1_INACT_MSK, status1))
911 iio_push_event(indio_dev,
912 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
913 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
914 timestamp);
915 if (FIELD_GET(ADXL380_STATUS_1_SINGLE_TAP_MSK, status1))
916 iio_push_event(indio_dev,
917 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
918 IIO_EV_TYPE_GESTURE, IIO_EV_DIR_SINGLETAP),
919 timestamp);
920
921 if (FIELD_GET(ADXL380_STATUS_1_DOUBLE_TAP_MSK, status1))
922 iio_push_event(indio_dev,
923 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
924 IIO_EV_TYPE_GESTURE, IIO_EV_DIR_DOUBLETAP),
925 timestamp);
926 }
927
adxl380_irq_handler(int irq,void * p)928 static irqreturn_t adxl380_irq_handler(int irq, void *p)
929 {
930 struct iio_dev *indio_dev = p;
931 struct adxl380_state *st = iio_priv(indio_dev);
932 u8 status0, status1;
933 u16 fifo_entries;
934 int i;
935 int ret;
936
937 guard(mutex)(&st->lock);
938
939 ret = adxl380_get_status(st, &status0, &status1);
940 if (ret)
941 return IRQ_HANDLED;
942
943 adxl380_push_event(indio_dev, iio_get_time_ns(indio_dev), status1);
944
945 if (!FIELD_GET(ADXL380_STATUS_0_FIFO_WM_MSK, status0))
946 return IRQ_HANDLED;
947
948 ret = adxl380_get_fifo_entries(st, &fifo_entries);
949 if (ret)
950 return IRQ_HANDLED;
951
952 for (i = 0; i < fifo_entries; i += st->fifo_set_size) {
953 ret = regmap_noinc_read(st->regmap, ADXL380_FIFO_DATA,
954 &st->fifo_buf[i],
955 2 * st->fifo_set_size);
956 if (ret)
957 return IRQ_HANDLED;
958 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
959 }
960
961 return IRQ_HANDLED;
962 }
963
adxl380_write_calibbias_value(struct adxl380_state * st,unsigned long chan_addr,s8 calibbias)964 static int adxl380_write_calibbias_value(struct adxl380_state *st,
965 unsigned long chan_addr,
966 s8 calibbias)
967 {
968 int ret;
969
970 guard(mutex)(&st->lock);
971
972 ret = adxl380_set_measure_en(st, false);
973 if (ret)
974 return ret;
975
976 ret = regmap_write(st->regmap, ADXL380_X_DSM_OFFSET_REG + chan_addr, calibbias);
977 if (ret)
978 return ret;
979
980 return adxl380_set_measure_en(st, true);
981 }
982
adxl380_read_calibbias_value(struct adxl380_state * st,unsigned long chan_addr,int * calibbias)983 static int adxl380_read_calibbias_value(struct adxl380_state *st,
984 unsigned long chan_addr,
985 int *calibbias)
986 {
987 int ret;
988 unsigned int reg_val;
989
990 guard(mutex)(&st->lock);
991
992 ret = regmap_read(st->regmap, ADXL380_X_DSM_OFFSET_REG + chan_addr, ®_val);
993 if (ret)
994 return ret;
995
996 *calibbias = sign_extend32(reg_val, 7);
997
998 return 0;
999 }
1000
hwfifo_watermark_min_show(struct device * dev,struct device_attribute * attr,char * buf)1001 static ssize_t hwfifo_watermark_min_show(struct device *dev,
1002 struct device_attribute *attr,
1003 char *buf)
1004 {
1005 return sysfs_emit(buf, "1\n");
1006 }
1007
hwfifo_watermark_max_show(struct device * dev,struct device_attribute * attr,char * buf)1008 static ssize_t hwfifo_watermark_max_show(struct device *dev,
1009 struct device_attribute *attr,
1010 char *buf)
1011 {
1012 return sysfs_emit(buf, "%lu\n", ADXL380_FIFO_SAMPLES);
1013 }
1014
adxl380_get_fifo_watermark(struct device * dev,struct device_attribute * attr,char * buf)1015 static ssize_t adxl380_get_fifo_watermark(struct device *dev,
1016 struct device_attribute *attr,
1017 char *buf)
1018 {
1019 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1020 struct adxl380_state *st = iio_priv(indio_dev);
1021
1022 return sysfs_emit(buf, "%d\n", st->watermark);
1023 }
1024
adxl380_get_fifo_enabled(struct device * dev,struct device_attribute * attr,char * buf)1025 static ssize_t adxl380_get_fifo_enabled(struct device *dev,
1026 struct device_attribute *attr,
1027 char *buf)
1028 {
1029 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1030 struct adxl380_state *st = iio_priv(indio_dev);
1031 int ret;
1032 unsigned int reg_val;
1033
1034 ret = regmap_read(st->regmap, ADXL380_DIG_EN_REG, ®_val);
1035 if (ret)
1036 return ret;
1037
1038 return sysfs_emit(buf, "%lu\n",
1039 FIELD_GET(ADXL380_FIFO_EN_MSK, reg_val));
1040 }
1041
1042 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
1043 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
1044 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1045 adxl380_get_fifo_watermark, NULL, 0);
1046 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1047 adxl380_get_fifo_enabled, NULL, 0);
1048
1049 static const struct iio_dev_attr *adxl380_fifo_attributes[] = {
1050 &iio_dev_attr_hwfifo_watermark_min,
1051 &iio_dev_attr_hwfifo_watermark_max,
1052 &iio_dev_attr_hwfifo_watermark,
1053 &iio_dev_attr_hwfifo_enabled,
1054 NULL
1055 };
1056
adxl380_buffer_postenable(struct iio_dev * indio_dev)1057 static int adxl380_buffer_postenable(struct iio_dev *indio_dev)
1058 {
1059 struct adxl380_state *st = iio_priv(indio_dev);
1060 int i;
1061 int ret;
1062
1063 guard(mutex)(&st->lock);
1064
1065 ret = adxl380_set_measure_en(st, false);
1066 if (ret)
1067 return ret;
1068
1069 ret = regmap_update_bits(st->regmap,
1070 st->int_map[0],
1071 ADXL380_INT_MAP0_FIFO_WM_INT0_MSK,
1072 FIELD_PREP(ADXL380_INT_MAP0_FIFO_WM_INT0_MSK, 1));
1073 if (ret)
1074 return ret;
1075
1076 for_each_clear_bit(i, indio_dev->active_scan_mask, ADXL380_CH_NUM) {
1077 ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG,
1078 ADXL380_CHAN_EN_MSK(i),
1079 0 << (4 + i));
1080 if (ret)
1081 return ret;
1082 }
1083
1084 st->fifo_set_size = bitmap_weight(indio_dev->active_scan_mask,
1085 iio_get_masklength(indio_dev));
1086
1087 if ((st->watermark * st->fifo_set_size) > ADXL380_FIFO_SAMPLES)
1088 st->watermark = (ADXL380_FIFO_SAMPLES / st->fifo_set_size);
1089
1090 ret = adxl380_set_fifo_samples(st);
1091 if (ret)
1092 return ret;
1093
1094 ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG, ADXL380_FIFO_EN_MSK,
1095 FIELD_PREP(ADXL380_FIFO_EN_MSK, 1));
1096 if (ret)
1097 return ret;
1098
1099 return adxl380_set_measure_en(st, true);
1100 }
1101
adxl380_buffer_predisable(struct iio_dev * indio_dev)1102 static int adxl380_buffer_predisable(struct iio_dev *indio_dev)
1103 {
1104 struct adxl380_state *st = iio_priv(indio_dev);
1105 int ret, i;
1106
1107 guard(mutex)(&st->lock);
1108
1109 ret = adxl380_set_measure_en(st, false);
1110 if (ret)
1111 return ret;
1112
1113 ret = regmap_update_bits(st->regmap,
1114 st->int_map[0],
1115 ADXL380_INT_MAP0_FIFO_WM_INT0_MSK,
1116 FIELD_PREP(ADXL380_INT_MAP0_FIFO_WM_INT0_MSK, 0));
1117 if (ret)
1118 return ret;
1119
1120 for (i = 0; i < indio_dev->num_channels; i++) {
1121 ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG,
1122 ADXL380_CHAN_EN_MSK(i),
1123 1 << (4 + i));
1124 if (ret)
1125 return ret;
1126 }
1127
1128 ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG, ADXL380_FIFO_EN_MSK,
1129 FIELD_PREP(ADXL380_FIFO_EN_MSK, 0));
1130 if (ret)
1131 return ret;
1132
1133 return adxl380_set_measure_en(st, true);
1134 }
1135
1136 static const struct iio_buffer_setup_ops adxl380_buffer_ops = {
1137 .postenable = adxl380_buffer_postenable,
1138 .predisable = adxl380_buffer_predisable,
1139 };
1140
adxl380_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)1141 static int adxl380_read_raw(struct iio_dev *indio_dev,
1142 struct iio_chan_spec const *chan,
1143 int *val, int *val2, long info)
1144 {
1145 struct adxl380_state *st = iio_priv(indio_dev);
1146 int ret;
1147
1148 switch (info) {
1149 case IIO_CHAN_INFO_RAW:
1150 if (!iio_device_claim_direct(indio_dev))
1151 return -EBUSY;
1152
1153 ret = adxl380_read_chn(st, chan->address);
1154 iio_device_release_direct(indio_dev);
1155 if (ret < 0)
1156 return ret;
1157
1158 *val = sign_extend32(ret >> chan->scan_type.shift,
1159 chan->scan_type.realbits - 1);
1160 return IIO_VAL_INT;
1161 case IIO_CHAN_INFO_SCALE:
1162 switch (chan->type) {
1163 case IIO_ACCEL:
1164 scoped_guard(mutex, &st->lock) {
1165 *val = st->chip_info->scale_tbl[st->range][0];
1166 *val2 = st->chip_info->scale_tbl[st->range][1];
1167 }
1168 return IIO_VAL_INT_PLUS_NANO;
1169 case IIO_TEMP:
1170 /* 10.2 LSB / Degree Celsius */
1171 *val = 10000;
1172 *val2 = 102;
1173 return IIO_VAL_FRACTIONAL;
1174 default:
1175 return -EINVAL;
1176 }
1177 case IIO_CHAN_INFO_OFFSET:
1178 switch (chan->type) {
1179 case IIO_TEMP:
1180 *val = st->chip_info->temp_offset;
1181 return IIO_VAL_INT;
1182 default:
1183 return -EINVAL;
1184 }
1185 case IIO_CHAN_INFO_CALIBBIAS:
1186 switch (chan->type) {
1187 case IIO_ACCEL:
1188 ret = adxl380_read_calibbias_value(st, chan->scan_index, val);
1189 if (ret)
1190 return ret;
1191 return IIO_VAL_INT;
1192 default:
1193 return -EINVAL;
1194 }
1195 case IIO_CHAN_INFO_SAMP_FREQ:
1196 ret = adxl380_get_odr(st, val);
1197 if (ret)
1198 return ret;
1199 return IIO_VAL_INT;
1200 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1201 ret = adxl380_get_lpf(st, val);
1202 if (ret)
1203 return ret;
1204 return IIO_VAL_INT;
1205 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
1206 ret = adxl380_get_hpf(st, val, val2);
1207 if (ret)
1208 return ret;
1209 return IIO_VAL_INT_PLUS_MICRO;
1210 }
1211
1212 return -EINVAL;
1213 }
1214
adxl380_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)1215 static int adxl380_read_avail(struct iio_dev *indio_dev,
1216 struct iio_chan_spec const *chan,
1217 const int **vals, int *type, int *length,
1218 long mask)
1219 {
1220 struct adxl380_state *st = iio_priv(indio_dev);
1221
1222 if (chan->type != IIO_ACCEL)
1223 return -EINVAL;
1224
1225 switch (mask) {
1226 case IIO_CHAN_INFO_SCALE:
1227 *vals = (const int *)st->chip_info->scale_tbl;
1228 *type = IIO_VAL_INT_PLUS_NANO;
1229 *length = ARRAY_SIZE(st->chip_info->scale_tbl) * 2;
1230 return IIO_AVAIL_LIST;
1231 case IIO_CHAN_INFO_SAMP_FREQ:
1232 *vals = (const int *)st->chip_info->samp_freq_tbl;
1233 *type = IIO_VAL_INT;
1234 *length = ARRAY_SIZE(st->chip_info->samp_freq_tbl);
1235 return IIO_AVAIL_LIST;
1236 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1237 *vals = (const int *)st->lpf_tbl;
1238 *type = IIO_VAL_INT;
1239 *length = ARRAY_SIZE(st->lpf_tbl);
1240 return IIO_AVAIL_LIST;
1241 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
1242 *vals = (const int *)st->hpf_tbl;
1243 *type = IIO_VAL_INT_PLUS_MICRO;
1244 /* Values are stored in a 2D matrix */
1245 *length = ARRAY_SIZE(st->hpf_tbl) * 2;
1246 return IIO_AVAIL_LIST;
1247 default:
1248 return -EINVAL;
1249 }
1250 }
1251
adxl380_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1252 static int adxl380_write_raw(struct iio_dev *indio_dev,
1253 struct iio_chan_spec const *chan,
1254 int val, int val2, long info)
1255 {
1256 struct adxl380_state *st = iio_priv(indio_dev);
1257 int odr_index, lpf_index, hpf_index, range_index;
1258
1259 switch (info) {
1260 case IIO_CHAN_INFO_SAMP_FREQ:
1261 odr_index = adxl380_find_match_1d_tbl(st->chip_info->samp_freq_tbl,
1262 ARRAY_SIZE(st->chip_info->samp_freq_tbl),
1263 val);
1264 return adxl380_set_odr(st, odr_index);
1265 case IIO_CHAN_INFO_CALIBBIAS:
1266 return adxl380_write_calibbias_value(st, chan->scan_index, val);
1267 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1268 lpf_index = adxl380_find_match_1d_tbl(st->lpf_tbl,
1269 ARRAY_SIZE(st->lpf_tbl),
1270 val);
1271 return adxl380_set_lpf(st, lpf_index);
1272 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
1273 hpf_index = adxl380_find_match_2d_tbl(st->hpf_tbl,
1274 ARRAY_SIZE(st->hpf_tbl),
1275 val, val2);
1276 if (hpf_index < 0)
1277 return hpf_index;
1278 return adxl380_set_hpf(st, hpf_index);
1279 case IIO_CHAN_INFO_SCALE:
1280 range_index = adxl380_find_match_2d_tbl(st->chip_info->scale_tbl,
1281 ARRAY_SIZE(st->chip_info->scale_tbl),
1282 val, val2);
1283 if (range_index < 0)
1284 return range_index;
1285 return adxl380_set_range(st, range_index);
1286 default:
1287 return -EINVAL;
1288 }
1289 }
1290
adxl380_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long info)1291 static int adxl380_write_raw_get_fmt(struct iio_dev *indio_dev,
1292 struct iio_chan_spec const *chan,
1293 long info)
1294 {
1295 switch (info) {
1296 case IIO_CHAN_INFO_SCALE:
1297 if (chan->type != IIO_ACCEL)
1298 return -EINVAL;
1299
1300 return IIO_VAL_INT_PLUS_NANO;
1301 default:
1302 return IIO_VAL_INT_PLUS_MICRO;
1303 }
1304 }
1305
adxl380_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1306 static int adxl380_read_event_config(struct iio_dev *indio_dev,
1307 const struct iio_chan_spec *chan,
1308 enum iio_event_type type,
1309 enum iio_event_direction dir)
1310 {
1311 struct adxl380_state *st = iio_priv(indio_dev);
1312 int ret;
1313 bool int_en;
1314 bool tap_axis_en = false;
1315
1316 switch (chan->channel2) {
1317 case IIO_MOD_X:
1318 tap_axis_en = st->tap_axis_en == ADXL380_X_AXIS;
1319 break;
1320 case IIO_MOD_Y:
1321 tap_axis_en = st->tap_axis_en == ADXL380_Y_AXIS;
1322 break;
1323 case IIO_MOD_Z:
1324 tap_axis_en = st->tap_axis_en == ADXL380_Z_AXIS;
1325 break;
1326 default:
1327 return -EINVAL;
1328 }
1329
1330 switch (dir) {
1331 case IIO_EV_DIR_RISING:
1332 ret = adxl380_read_act_inact_int(st, ADXL380_ACTIVITY, &int_en);
1333 if (ret)
1334 return ret;
1335 return int_en;
1336 case IIO_EV_DIR_FALLING:
1337 ret = adxl380_read_act_inact_int(st, ADXL380_INACTIVITY, &int_en);
1338 if (ret)
1339 return ret;
1340 return int_en;
1341 case IIO_EV_DIR_SINGLETAP:
1342 ret = adxl380_read_tap_int(st, ADXL380_SINGLE_TAP, &int_en);
1343 if (ret)
1344 return ret;
1345 return int_en && tap_axis_en;
1346 case IIO_EV_DIR_DOUBLETAP:
1347 ret = adxl380_read_tap_int(st, ADXL380_DOUBLE_TAP, &int_en);
1348 if (ret)
1349 return ret;
1350 return int_en && tap_axis_en;
1351 default:
1352 return -EINVAL;
1353 }
1354 }
1355
adxl380_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)1356 static int adxl380_write_event_config(struct iio_dev *indio_dev,
1357 const struct iio_chan_spec *chan,
1358 enum iio_event_type type,
1359 enum iio_event_direction dir,
1360 bool state)
1361 {
1362 struct adxl380_state *st = iio_priv(indio_dev);
1363 enum adxl380_axis axis;
1364
1365 switch (chan->channel2) {
1366 case IIO_MOD_X:
1367 axis = ADXL380_X_AXIS;
1368 break;
1369 case IIO_MOD_Y:
1370 axis = ADXL380_Y_AXIS;
1371 break;
1372 case IIO_MOD_Z:
1373 axis = ADXL380_Z_AXIS;
1374 break;
1375 default:
1376 return -EINVAL;
1377 }
1378
1379 switch (dir) {
1380 case IIO_EV_DIR_RISING:
1381 return adxl380_act_inact_config(st, ADXL380_ACTIVITY, state);
1382 case IIO_EV_DIR_FALLING:
1383 return adxl380_act_inact_config(st, ADXL380_INACTIVITY, state);
1384 case IIO_EV_DIR_SINGLETAP:
1385 return adxl380_tap_config(st, axis, ADXL380_SINGLE_TAP, state);
1386 case IIO_EV_DIR_DOUBLETAP:
1387 return adxl380_tap_config(st, axis, ADXL380_DOUBLE_TAP, state);
1388 default:
1389 return -EINVAL;
1390 }
1391 }
1392
adxl380_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)1393 static int adxl380_read_event_value(struct iio_dev *indio_dev,
1394 const struct iio_chan_spec *chan,
1395 enum iio_event_type type,
1396 enum iio_event_direction dir,
1397 enum iio_event_info info,
1398 int *val, int *val2)
1399 {
1400 struct adxl380_state *st = iio_priv(indio_dev);
1401
1402 guard(mutex)(&st->lock);
1403
1404 switch (type) {
1405 case IIO_EV_TYPE_THRESH:
1406 switch (info) {
1407 case IIO_EV_INFO_VALUE: {
1408 switch (dir) {
1409 case IIO_EV_DIR_RISING:
1410 *val = st->act_threshold;
1411 return IIO_VAL_INT;
1412 case IIO_EV_DIR_FALLING:
1413 *val = st->inact_threshold;
1414 return IIO_VAL_INT;
1415 default:
1416 return -EINVAL;
1417 }
1418 }
1419 case IIO_EV_INFO_PERIOD:
1420 switch (dir) {
1421 case IIO_EV_DIR_RISING:
1422 *val = st->act_time_ms;
1423 *val2 = 1000;
1424 return IIO_VAL_FRACTIONAL;
1425 case IIO_EV_DIR_FALLING:
1426 *val = st->inact_time_ms;
1427 *val2 = 1000;
1428 return IIO_VAL_FRACTIONAL;
1429 default:
1430 return -EINVAL;
1431 }
1432 default:
1433 return -EINVAL;
1434 }
1435 case IIO_EV_TYPE_GESTURE:
1436 switch (info) {
1437 case IIO_EV_INFO_VALUE:
1438 *val = st->tap_threshold;
1439 return IIO_VAL_INT;
1440 case IIO_EV_INFO_RESET_TIMEOUT:
1441 *val = st->tap_window_us;
1442 *val2 = 1000000;
1443 return IIO_VAL_FRACTIONAL;
1444 case IIO_EV_INFO_TAP2_MIN_DELAY:
1445 *val = st->tap_latent_us;
1446 *val2 = 1000000;
1447 return IIO_VAL_FRACTIONAL;
1448 default:
1449 return -EINVAL;
1450 }
1451 default:
1452 return -EINVAL;
1453 }
1454 }
1455
adxl380_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1456 static int adxl380_write_event_value(struct iio_dev *indio_dev,
1457 const struct iio_chan_spec *chan,
1458 enum iio_event_type type, enum iio_event_direction dir,
1459 enum iio_event_info info, int val, int val2)
1460 {
1461 struct adxl380_state *st = iio_priv(indio_dev);
1462 u32 val_ms, val_us;
1463
1464 if (chan->type != IIO_ACCEL)
1465 return -EINVAL;
1466
1467 switch (type) {
1468 case IIO_EV_TYPE_THRESH:
1469 switch (info) {
1470 case IIO_EV_INFO_VALUE:
1471 switch (dir) {
1472 case IIO_EV_DIR_RISING:
1473 return adxl380_set_act_inact_threshold(indio_dev,
1474 ADXL380_ACTIVITY, val);
1475 case IIO_EV_DIR_FALLING:
1476 return adxl380_set_act_inact_threshold(indio_dev,
1477 ADXL380_INACTIVITY, val);
1478 default:
1479 return -EINVAL;
1480 }
1481 case IIO_EV_INFO_PERIOD:
1482 val_ms = val * 1000 + DIV_ROUND_UP(val2, 1000);
1483 switch (dir) {
1484 case IIO_EV_DIR_RISING:
1485 return adxl380_set_act_inact_time_ms(st,
1486 ADXL380_ACTIVITY, val_ms);
1487 case IIO_EV_DIR_FALLING:
1488 return adxl380_set_act_inact_time_ms(st,
1489 ADXL380_INACTIVITY, val_ms);
1490 default:
1491 return -EINVAL;
1492 }
1493
1494 default:
1495 return -EINVAL;
1496 }
1497 case IIO_EV_TYPE_GESTURE:
1498 switch (info) {
1499 case IIO_EV_INFO_VALUE:
1500 return adxl380_set_tap_threshold_value(indio_dev, val);
1501 case IIO_EV_INFO_RESET_TIMEOUT:
1502 val_us = val * 1000000 + val2;
1503 return adxl380_write_tap_time_us(st,
1504 ADXL380_TAP_TIME_WINDOW,
1505 val_us);
1506 case IIO_EV_INFO_TAP2_MIN_DELAY:
1507 val_us = val * 1000000 + val2;
1508 return adxl380_write_tap_time_us(st,
1509 ADXL380_TAP_TIME_LATENT,
1510 val_us);
1511 default:
1512 return -EINVAL;
1513 }
1514 default:
1515 return -EINVAL;
1516 }
1517 }
1518
in_accel_gesture_tap_maxtomin_time_show(struct device * dev,struct device_attribute * attr,char * buf)1519 static ssize_t in_accel_gesture_tap_maxtomin_time_show(struct device *dev,
1520 struct device_attribute *attr,
1521 char *buf)
1522 {
1523 int vals[2];
1524 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1525 struct adxl380_state *st = iio_priv(indio_dev);
1526
1527 guard(mutex)(&st->lock);
1528
1529 vals[0] = st->tap_duration_us;
1530 vals[1] = MICRO;
1531
1532 return iio_format_value(buf, IIO_VAL_FRACTIONAL, 2, vals);
1533 }
1534
in_accel_gesture_tap_maxtomin_time_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)1535 static ssize_t in_accel_gesture_tap_maxtomin_time_store(struct device *dev,
1536 struct device_attribute *attr,
1537 const char *buf, size_t len)
1538 {
1539 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1540 struct adxl380_state *st = iio_priv(indio_dev);
1541 int ret, val_int, val_fract_us;
1542
1543 guard(mutex)(&st->lock);
1544
1545 ret = iio_str_to_fixpoint(buf, 100000, &val_int, &val_fract_us);
1546 if (ret)
1547 return ret;
1548
1549 /* maximum value is 255 * 625 us = 0.159375 seconds */
1550 if (val_int || val_fract_us > 159375 || val_fract_us < 0)
1551 return -EINVAL;
1552
1553 ret = adxl380_write_tap_dur_us(indio_dev, val_fract_us);
1554 if (ret)
1555 return ret;
1556
1557 return len;
1558 }
1559
1560 static IIO_DEVICE_ATTR_RW(in_accel_gesture_tap_maxtomin_time, 0);
1561
1562 static struct attribute *adxl380_event_attributes[] = {
1563 &iio_dev_attr_in_accel_gesture_tap_maxtomin_time.dev_attr.attr,
1564 NULL
1565 };
1566
1567 static const struct attribute_group adxl380_event_attribute_group = {
1568 .attrs = adxl380_event_attributes,
1569 };
1570
adxl380_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1571 static int adxl380_reg_access(struct iio_dev *indio_dev,
1572 unsigned int reg,
1573 unsigned int writeval,
1574 unsigned int *readval)
1575 {
1576 struct adxl380_state *st = iio_priv(indio_dev);
1577
1578 if (readval)
1579 return regmap_read(st->regmap, reg, readval);
1580
1581 return regmap_write(st->regmap, reg, writeval);
1582 }
1583
adxl380_set_watermark(struct iio_dev * indio_dev,unsigned int val)1584 static int adxl380_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1585 {
1586 struct adxl380_state *st = iio_priv(indio_dev);
1587
1588 st->watermark = min(val, ADXL380_FIFO_SAMPLES);
1589
1590 return 0;
1591 }
1592
1593 static const struct iio_info adxl318_info = {
1594 .read_raw = adxl380_read_raw,
1595 .read_avail = &adxl380_read_avail,
1596 .write_raw = adxl380_write_raw,
1597 .write_raw_get_fmt = adxl380_write_raw_get_fmt,
1598 .debugfs_reg_access = &adxl380_reg_access,
1599 .hwfifo_set_watermark = adxl380_set_watermark,
1600 };
1601
1602 static const struct iio_info adxl380_info = {
1603 .read_raw = adxl380_read_raw,
1604 .read_avail = &adxl380_read_avail,
1605 .write_raw = adxl380_write_raw,
1606 .write_raw_get_fmt = adxl380_write_raw_get_fmt,
1607 .read_event_config = adxl380_read_event_config,
1608 .write_event_config = adxl380_write_event_config,
1609 .read_event_value = adxl380_read_event_value,
1610 .write_event_value = adxl380_write_event_value,
1611 .event_attrs = &adxl380_event_attribute_group,
1612 .debugfs_reg_access = &adxl380_reg_access,
1613 .hwfifo_set_watermark = adxl380_set_watermark,
1614 };
1615
1616 const struct adxl380_chip_info adxl318_chip_info = {
1617 .name = "adxl318",
1618 .chip_id = ADXL318_ID_VAL,
1619 .scale_tbl = {
1620 [ADXL380_OP_MODE_4G_RANGE] = { 0, 1307226 },
1621 [ADXL380_OP_MODE_8G_RANGE] = { 0, 2615434 },
1622 [ADXL380_OP_MODE_16G_RANGE] = { 0, 5229886 },
1623 },
1624 .samp_freq_tbl = { 8000, 16000, 32000 },
1625 /*
1626 * The datasheet defines an intercept of 550 LSB at 25 degC
1627 * and a sensitivity of 10.2 LSB/C.
1628 */
1629 .temp_offset = 25 * 102 / 10 - 550,
1630 .info = &adxl318_info,
1631 };
1632 EXPORT_SYMBOL_NS_GPL(adxl318_chip_info, "IIO_ADXL380");
1633
1634 const struct adxl380_chip_info adxl319_chip_info = {
1635 .name = "adxl319",
1636 .chip_id = ADXL319_ID_VAL,
1637 .scale_tbl = {
1638 [ADXL382_OP_MODE_15G_RANGE] = { 0, 4903325 },
1639 [ADXL382_OP_MODE_30G_RANGE] = { 0, 9806650 },
1640 [ADXL382_OP_MODE_60G_RANGE] = { 0, 19613300 },
1641 },
1642 .samp_freq_tbl = { 16000, 32000, 64000 },
1643 /*
1644 * The datasheet defines an intercept of 550 LSB at 25 degC
1645 * and a sensitivity of 10.2 LSB/C.
1646 */
1647 .temp_offset = 25 * 102 / 10 - 550,
1648 .info = &adxl318_info,
1649 };
1650 EXPORT_SYMBOL_NS_GPL(adxl319_chip_info, "IIO_ADXL380");
1651
1652 const struct adxl380_chip_info adxl380_chip_info = {
1653 .name = "adxl380",
1654 .chip_id = ADXL380_ID_VAL,
1655 .scale_tbl = {
1656 [ADXL380_OP_MODE_4G_RANGE] = { 0, 1307226 },
1657 [ADXL380_OP_MODE_8G_RANGE] = { 0, 2615434 },
1658 [ADXL380_OP_MODE_16G_RANGE] = { 0, 5229886 },
1659 },
1660 .samp_freq_tbl = { 8000, 16000, 32000 },
1661 /*
1662 * The datasheet defines an intercept of 470 LSB at 25 degC
1663 * and a sensitivity of 10.2 LSB/C.
1664 */
1665 .temp_offset = 25 * 102 / 10 - 470,
1666 .has_low_power = true,
1667 .info = &adxl380_info,
1668
1669 };
1670 EXPORT_SYMBOL_NS_GPL(adxl380_chip_info, "IIO_ADXL380");
1671
1672 const struct adxl380_chip_info adxl382_chip_info = {
1673 .name = "adxl382",
1674 .chip_id = ADXL382_ID_VAL,
1675 .scale_tbl = {
1676 [ADXL382_OP_MODE_15G_RANGE] = { 0, 4903325 },
1677 [ADXL382_OP_MODE_30G_RANGE] = { 0, 9806650 },
1678 [ADXL382_OP_MODE_60G_RANGE] = { 0, 19613300 },
1679 },
1680 .samp_freq_tbl = { 16000, 32000, 64000 },
1681 /*
1682 * The datasheet defines an intercept of 570 LSB at 25 degC
1683 * and a sensitivity of 10.2 LSB/C.
1684 */
1685 .temp_offset = 25 * 102 / 10 - 570,
1686 .has_low_power = true,
1687 .info = &adxl380_info,
1688 };
1689 EXPORT_SYMBOL_NS_GPL(adxl382_chip_info, "IIO_ADXL380");
1690
1691 static const struct iio_event_spec adxl380_events[] = {
1692 {
1693 .type = IIO_EV_TYPE_THRESH,
1694 .dir = IIO_EV_DIR_RISING,
1695 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1696 BIT(IIO_EV_INFO_VALUE) |
1697 BIT(IIO_EV_INFO_PERIOD),
1698 },
1699 {
1700 .type = IIO_EV_TYPE_THRESH,
1701 .dir = IIO_EV_DIR_FALLING,
1702 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1703 BIT(IIO_EV_INFO_VALUE) |
1704 BIT(IIO_EV_INFO_PERIOD),
1705 },
1706 {
1707 .type = IIO_EV_TYPE_GESTURE,
1708 .dir = IIO_EV_DIR_SINGLETAP,
1709 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1710 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1711 BIT(IIO_EV_INFO_RESET_TIMEOUT),
1712 },
1713 {
1714 .type = IIO_EV_TYPE_GESTURE,
1715 .dir = IIO_EV_DIR_DOUBLETAP,
1716 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1717 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1718 BIT(IIO_EV_INFO_RESET_TIMEOUT) |
1719 BIT(IIO_EV_INFO_TAP2_MIN_DELAY),
1720 },
1721 };
1722
1723 #define ADXL380_ACCEL_CHANNEL(index, reg, axis) { \
1724 .type = IIO_ACCEL, \
1725 .address = reg, \
1726 .modified = 1, \
1727 .channel2 = IIO_MOD_##axis, \
1728 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1729 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1730 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1731 .info_mask_shared_by_all_available = \
1732 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1733 .info_mask_shared_by_type = \
1734 BIT(IIO_CHAN_INFO_SCALE) | \
1735 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
1736 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
1737 .info_mask_shared_by_type_available = \
1738 BIT(IIO_CHAN_INFO_SCALE) | \
1739 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
1740 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
1741 .scan_index = index, \
1742 .scan_type = { \
1743 .sign = 's', \
1744 .realbits = 16, \
1745 .storagebits = 16, \
1746 .endianness = IIO_BE, \
1747 }, \
1748 .event_spec = adxl380_events, \
1749 .num_event_specs = ARRAY_SIZE(adxl380_events) \
1750 }
1751
1752 static const struct iio_chan_spec adxl380_channels[] = {
1753 ADXL380_ACCEL_CHANNEL(0, ADXL380_X_DATA_H_REG, X),
1754 ADXL380_ACCEL_CHANNEL(1, ADXL380_Y_DATA_H_REG, Y),
1755 ADXL380_ACCEL_CHANNEL(2, ADXL380_Z_DATA_H_REG, Z),
1756 {
1757 .type = IIO_TEMP,
1758 .address = ADXL380_T_DATA_H_REG,
1759 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1760 BIT(IIO_CHAN_INFO_SCALE) |
1761 BIT(IIO_CHAN_INFO_OFFSET),
1762 .scan_index = 3,
1763 .scan_type = {
1764 .sign = 's',
1765 .realbits = 12,
1766 .storagebits = 16,
1767 .shift = 4,
1768 .endianness = IIO_BE,
1769 },
1770 },
1771 };
1772
adxl380_config_irq(struct iio_dev * indio_dev)1773 static int adxl380_config_irq(struct iio_dev *indio_dev)
1774 {
1775 struct adxl380_state *st = iio_priv(indio_dev);
1776 unsigned long irq_flag;
1777 u32 irq_type;
1778 u8 polarity;
1779 int ret;
1780
1781 st->irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT0");
1782 if (st->irq > 0) {
1783 st->int_map[0] = ADXL380_INT0_MAP0_REG;
1784 st->int_map[1] = ADXL380_INT0_MAP1_REG;
1785 } else {
1786 st->irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT1");
1787 if (st->irq > 0)
1788 return dev_err_probe(st->dev, -ENODEV,
1789 "no interrupt name specified");
1790 st->int_map[0] = ADXL380_INT1_MAP0_REG;
1791 st->int_map[1] = ADXL380_INT1_MAP1_REG;
1792 }
1793
1794 irq_type = irq_get_trigger_type(st->irq);
1795 if (irq_type == IRQ_TYPE_LEVEL_HIGH) {
1796 polarity = 0;
1797 irq_flag = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
1798 } else if (irq_type == IRQ_TYPE_LEVEL_LOW) {
1799 polarity = 1;
1800 irq_flag = IRQF_TRIGGER_LOW | IRQF_ONESHOT;
1801 } else {
1802 return dev_err_probe(st->dev, -EINVAL,
1803 "Invalid interrupt 0x%x. Only level interrupts supported\n",
1804 irq_type);
1805 }
1806
1807 ret = regmap_update_bits(st->regmap, ADXL380_INT0_REG,
1808 ADXL380_INT0_POL_MSK,
1809 FIELD_PREP(ADXL380_INT0_POL_MSK, polarity));
1810 if (ret)
1811 return ret;
1812
1813 return devm_request_threaded_irq(st->dev, st->irq, NULL,
1814 adxl380_irq_handler, irq_flag,
1815 indio_dev->name, indio_dev);
1816 }
1817
adxl380_setup(struct iio_dev * indio_dev)1818 static int adxl380_setup(struct iio_dev *indio_dev)
1819 {
1820 unsigned int reg_val;
1821 u16 part_id, chip_id;
1822 int ret, i;
1823 struct adxl380_state *st = iio_priv(indio_dev);
1824
1825 ret = regmap_read(st->regmap, ADXL380_DEVID_AD_REG, ®_val);
1826 if (ret)
1827 return ret;
1828
1829 if (reg_val != ADXL380_DEVID_AD_VAL)
1830 dev_warn(st->dev, "Unknown chip id %x\n", reg_val);
1831
1832 ret = regmap_bulk_read(st->regmap, ADLX380_PART_ID_REG,
1833 &st->transf_buf, 2);
1834 if (ret)
1835 return ret;
1836
1837 part_id = get_unaligned_be16(st->transf_buf);
1838 part_id >>= 4;
1839
1840 if (part_id != ADXL380_ID_VAL)
1841 dev_warn(st->dev, "Unknown part id %x\n", part_id);
1842
1843 ret = regmap_read(st->regmap, ADXL380_MISC_0_REG, ®_val);
1844 if (ret)
1845 return ret;
1846
1847 /* Bit to differentiate between ADXL380/382. */
1848 if (reg_val & ADXL380_XL382_MSK)
1849 chip_id = ADXL382_ID_VAL;
1850 else
1851 chip_id = ADXL380_ID_VAL;
1852
1853 if (chip_id != st->chip_info->chip_id)
1854 dev_warn(st->dev, "Unknown chip id %x\n", chip_id);
1855
1856 ret = regmap_write(st->regmap, ADXL380_RESET_REG, ADXL380_RESET_CODE);
1857 if (ret)
1858 return ret;
1859
1860 /*
1861 * A latency of approximately 0.5 ms is required after soft reset.
1862 * Stated in the register REG_RESET description.
1863 */
1864 fsleep(500);
1865
1866 for (i = 0; i < indio_dev->num_channels; i++) {
1867 ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG,
1868 ADXL380_CHAN_EN_MSK(i),
1869 1 << (4 + i));
1870 if (ret)
1871 return ret;
1872 }
1873
1874 ret = regmap_update_bits(st->regmap, ADXL380_FIFO_CONFIG_0_REG,
1875 ADXL380_FIFO_MODE_MSK,
1876 FIELD_PREP(ADXL380_FIFO_MODE_MSK, ADXL380_FIFO_STREAMED));
1877 if (ret)
1878 return ret;
1879
1880 /* Select all 3 axis for act/inact detection. */
1881 ret = regmap_update_bits(st->regmap, ADXL380_SNSR_AXIS_EN_REG,
1882 ADXL380_ACT_INACT_AXIS_EN_MSK,
1883 FIELD_PREP(ADXL380_ACT_INACT_AXIS_EN_MSK,
1884 ADXL380_ACT_INACT_AXIS_EN_MSK));
1885 if (ret)
1886 return ret;
1887
1888 ret = adxl380_config_irq(indio_dev);
1889 if (ret)
1890 return ret;
1891
1892 ret = adxl380_fill_lpf_tbl(st);
1893 if (ret)
1894 return ret;
1895
1896 ret = adxl380_fill_hpf_tbl(st);
1897 if (ret)
1898 return ret;
1899
1900 return adxl380_set_measure_en(st, true);
1901 }
1902
adxl380_probe(struct device * dev,struct regmap * regmap,const struct adxl380_chip_info * chip_info)1903 int adxl380_probe(struct device *dev, struct regmap *regmap,
1904 const struct adxl380_chip_info *chip_info)
1905 {
1906 struct iio_dev *indio_dev;
1907 struct adxl380_state *st;
1908 int ret;
1909
1910 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1911 if (!indio_dev)
1912 return -ENOMEM;
1913
1914 st = iio_priv(indio_dev);
1915
1916 st->dev = dev;
1917 st->regmap = regmap;
1918 st->chip_info = chip_info;
1919
1920 mutex_init(&st->lock);
1921
1922 indio_dev->channels = adxl380_channels;
1923 indio_dev->num_channels = ARRAY_SIZE(adxl380_channels);
1924 indio_dev->name = chip_info->name;
1925 indio_dev->info = chip_info->info;
1926 indio_dev->modes = INDIO_DIRECT_MODE;
1927
1928 ret = devm_regulator_get_enable(dev, "vddio");
1929 if (ret)
1930 return dev_err_probe(st->dev, ret,
1931 "Failed to get vddio regulator\n");
1932
1933 ret = devm_regulator_get_enable(st->dev, "vsupply");
1934 if (ret)
1935 return dev_err_probe(st->dev, ret,
1936 "Failed to get vsupply regulator\n");
1937
1938 ret = adxl380_setup(indio_dev);
1939 if (ret)
1940 return ret;
1941
1942 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,
1943 &adxl380_buffer_ops,
1944 adxl380_fifo_attributes);
1945 if (ret)
1946 return ret;
1947
1948 return devm_iio_device_register(dev, indio_dev);
1949 }
1950 EXPORT_SYMBOL_NS_GPL(adxl380_probe, "IIO_ADXL380");
1951
1952 MODULE_AUTHOR("Ramona Gradinariu <ramona.gradinariu@analog.com>");
1953 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>");
1954 MODULE_DESCRIPTION("Analog Devices ADXL380 3-axis accelerometer driver");
1955 MODULE_LICENSE("GPL");
1956