1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ADXL372 3-Axis Digital Accelerometer core driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/module.h>
13 #include <linux/regmap.h>
14 #include <linux/spi/spi.h>
15
16 #include <linux/iio/iio.h>
17 #include <linux/iio/sysfs.h>
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/events.h>
20 #include <linux/iio/trigger.h>
21 #include <linux/iio/trigger_consumer.h>
22 #include <linux/iio/triggered_buffer.h>
23
24 #include "adxl372.h"
25
26 /* ADXL372 registers definition */
27 #define ADXL372_DEVID 0x00
28 #define ADXL372_DEVID_MST 0x01
29 #define ADXL372_PARTID 0x02
30 #define ADXL372_STATUS_1 0x04
31 #define ADXL372_STATUS_2 0x05
32 #define ADXL372_FIFO_ENTRIES_2 0x06
33 #define ADXL372_FIFO_ENTRIES_1 0x07
34 #define ADXL372_X_DATA_H 0x08
35 #define ADXL372_X_DATA_L 0x09
36 #define ADXL372_Y_DATA_H 0x0A
37 #define ADXL372_Y_DATA_L 0x0B
38 #define ADXL372_Z_DATA_H 0x0C
39 #define ADXL372_Z_DATA_L 0x0D
40 #define ADXL372_X_MAXPEAK_H 0x15
41 #define ADXL372_X_MAXPEAK_L 0x16
42 #define ADXL372_Y_MAXPEAK_H 0x17
43 #define ADXL372_Y_MAXPEAK_L 0x18
44 #define ADXL372_Z_MAXPEAK_H 0x19
45 #define ADXL372_Z_MAXPEAK_L 0x1A
46 #define ADXL372_OFFSET_X 0x20
47 #define ADXL372_OFFSET_Y 0x21
48 #define ADXL372_OFFSET_Z 0x22
49 #define ADXL372_X_THRESH_ACT_H 0x23
50 #define ADXL372_X_THRESH_ACT_L 0x24
51 #define ADXL372_Y_THRESH_ACT_H 0x25
52 #define ADXL372_Y_THRESH_ACT_L 0x26
53 #define ADXL372_Z_THRESH_ACT_H 0x27
54 #define ADXL372_Z_THRESH_ACT_L 0x28
55 #define ADXL372_TIME_ACT 0x29
56 #define ADXL372_X_THRESH_INACT_H 0x2A
57 #define ADXL372_X_THRESH_INACT_L 0x2B
58 #define ADXL372_Y_THRESH_INACT_H 0x2C
59 #define ADXL372_Y_THRESH_INACT_L 0x2D
60 #define ADXL372_Z_THRESH_INACT_H 0x2E
61 #define ADXL372_Z_THRESH_INACT_L 0x2F
62 #define ADXL372_TIME_INACT_H 0x30
63 #define ADXL372_TIME_INACT_L 0x31
64 #define ADXL372_X_THRESH_ACT2_H 0x32
65 #define ADXL372_X_THRESH_ACT2_L 0x33
66 #define ADXL372_Y_THRESH_ACT2_H 0x34
67 #define ADXL372_Y_THRESH_ACT2_L 0x35
68 #define ADXL372_Z_THRESH_ACT2_H 0x36
69 #define ADXL372_Z_THRESH_ACT2_L 0x37
70 #define ADXL372_HPF 0x38
71 #define ADXL372_FIFO_SAMPLES 0x39
72 #define ADXL372_FIFO_CTL 0x3A
73 #define ADXL372_INT1_MAP 0x3B
74 #define ADXL372_INT2_MAP 0x3C
75 #define ADXL372_TIMING 0x3D
76 #define ADXL372_MEASURE 0x3E
77 #define ADXL372_POWER_CTL 0x3F
78 #define ADXL372_SELF_TEST 0x40
79 #define ADXL372_RESET 0x41
80 #define ADXL372_FIFO_DATA 0x42
81
82 #define ADXL372_DEVID_VAL 0xAD
83 #define ADXL372_PARTID_VAL 0xFA
84 #define ADXL372_RESET_CODE 0x52
85
86 /* ADXL372_POWER_CTL */
87 #define ADXL372_POWER_CTL_MODE_MSK GENMASK_ULL(1, 0)
88 #define ADXL372_POWER_CTL_MODE(x) (((x) & 0x3) << 0)
89
90 /* ADXL372_MEASURE */
91 #define ADXL372_MEASURE_LINKLOOP_MSK GENMASK_ULL(5, 4)
92 #define ADXL372_MEASURE_LINKLOOP_MODE(x) (((x) & 0x3) << 4)
93 #define ADXL372_MEASURE_BANDWIDTH_MSK GENMASK_ULL(2, 0)
94 #define ADXL372_MEASURE_BANDWIDTH_MODE(x) (((x) & 0x7) << 0)
95
96 /* ADXL372_TIMING */
97 #define ADXL372_TIMING_ODR_MSK GENMASK_ULL(7, 5)
98 #define ADXL372_TIMING_ODR_MODE(x) (((x) & 0x7) << 5)
99
100 /* ADXL372_FIFO_CTL */
101 #define ADXL372_FIFO_CTL_FORMAT_MSK GENMASK(5, 3)
102 #define ADXL372_FIFO_CTL_FORMAT_MODE(x) (((x) & 0x7) << 3)
103 #define ADXL372_FIFO_CTL_MODE_MSK GENMASK(2, 1)
104 #define ADXL372_FIFO_CTL_MODE_MODE(x) (((x) & 0x3) << 1)
105 #define ADXL372_FIFO_CTL_SAMPLES_MSK BIT(1)
106 #define ADXL372_FIFO_CTL_SAMPLES_MODE(x) (((x) > 0xFF) ? 1 : 0)
107
108 /* ADXL372_STATUS_1 */
109 #define ADXL372_STATUS_1_DATA_RDY(x) (((x) >> 0) & 0x1)
110 #define ADXL372_STATUS_1_FIFO_RDY(x) (((x) >> 1) & 0x1)
111 #define ADXL372_STATUS_1_FIFO_FULL(x) (((x) >> 2) & 0x1)
112 #define ADXL372_STATUS_1_FIFO_OVR(x) (((x) >> 3) & 0x1)
113 #define ADXL372_STATUS_1_USR_NVM_BUSY(x) (((x) >> 5) & 0x1)
114 #define ADXL372_STATUS_1_AWAKE(x) (((x) >> 6) & 0x1)
115 #define ADXL372_STATUS_1_ERR_USR_REGS(x) (((x) >> 7) & 0x1)
116
117 /* ADXL372_STATUS_2 */
118 #define ADXL372_STATUS_2_INACT(x) (((x) >> 4) & 0x1)
119 #define ADXL372_STATUS_2_ACT(x) (((x) >> 5) & 0x1)
120 #define ADXL372_STATUS_2_AC2(x) (((x) >> 6) & 0x1)
121
122 /* ADXL372_INT1_MAP */
123 #define ADXL372_INT1_MAP_DATA_RDY_MSK BIT(0)
124 #define ADXL372_INT1_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 0)
125 #define ADXL372_INT1_MAP_FIFO_RDY_MSK BIT(1)
126 #define ADXL372_INT1_MAP_FIFO_RDY_MODE(x) (((x) & 0x1) << 1)
127 #define ADXL372_INT1_MAP_FIFO_FULL_MSK BIT(2)
128 #define ADXL372_INT1_MAP_FIFO_FULL_MODE(x) (((x) & 0x1) << 2)
129 #define ADXL372_INT1_MAP_FIFO_OVR_MSK BIT(3)
130 #define ADXL372_INT1_MAP_FIFO_OVR_MODE(x) (((x) & 0x1) << 3)
131 #define ADXL372_INT1_MAP_INACT_MSK BIT(4)
132 #define ADXL372_INT1_MAP_INACT_MODE(x) (((x) & 0x1) << 4)
133 #define ADXL372_INT1_MAP_ACT_MSK BIT(5)
134 #define ADXL372_INT1_MAP_ACT_MODE(x) (((x) & 0x1) << 5)
135 #define ADXL372_INT1_MAP_AWAKE_MSK BIT(6)
136 #define ADXL372_INT1_MAP_AWAKE_MODE(x) (((x) & 0x1) << 6)
137 #define ADXL372_INT1_MAP_LOW_MSK BIT(7)
138 #define ADXL372_INT1_MAP_LOW_MODE(x) (((x) & 0x1) << 7)
139
140 /* ADX372_THRESH */
141 #define ADXL372_THRESH_VAL_H_MSK GENMASK(10, 3)
142 #define ADXL372_THRESH_VAL_H_SEL(x) FIELD_GET(ADXL372_THRESH_VAL_H_MSK, x)
143 #define ADXL372_THRESH_VAL_L_MSK GENMASK(2, 0)
144 #define ADXL372_THRESH_VAL_L_SEL(x) FIELD_GET(ADXL372_THRESH_VAL_L_MSK, x)
145
146 /* The ADXL372 includes a deep, 512 sample FIFO buffer */
147 #define ADXL372_FIFO_SIZE 512
148 #define ADXL372_X_AXIS_EN(x) ((x) & BIT(0))
149 #define ADXL372_Y_AXIS_EN(x) ((x) & BIT(1))
150 #define ADXL372_Z_AXIS_EN(x) ((x) & BIT(2))
151
152 /*
153 * At +/- 200g with 12-bit resolution, scale is computed as:
154 * (200 + 200) * 9.81 / (2^12 - 1) = 0.958241
155 */
156 #define ADXL372_USCALE 958241
157
158 enum adxl372_op_mode {
159 ADXL372_STANDBY,
160 ADXL372_WAKE_UP,
161 ADXL372_INSTANT_ON,
162 ADXL372_FULL_BW_MEASUREMENT,
163 };
164
165 enum adxl372_act_proc_mode {
166 ADXL372_DEFAULT,
167 ADXL372_LINKED,
168 ADXL372_LOOPED,
169 };
170
171 enum adxl372_th_activity {
172 ADXL372_ACTIVITY,
173 ADXL372_ACTIVITY2,
174 ADXL372_INACTIVITY,
175 };
176
177 enum adxl372_odr {
178 ADXL372_ODR_400HZ,
179 ADXL372_ODR_800HZ,
180 ADXL372_ODR_1600HZ,
181 ADXL372_ODR_3200HZ,
182 ADXL372_ODR_6400HZ,
183 };
184
185 enum adxl372_bandwidth {
186 ADXL372_BW_200HZ,
187 ADXL372_BW_400HZ,
188 ADXL372_BW_800HZ,
189 ADXL372_BW_1600HZ,
190 ADXL372_BW_3200HZ,
191 };
192
193 static const unsigned int adxl372_th_reg_high_addr[3] = {
194 [ADXL372_ACTIVITY] = ADXL372_X_THRESH_ACT_H,
195 [ADXL372_ACTIVITY2] = ADXL372_X_THRESH_ACT2_H,
196 [ADXL372_INACTIVITY] = ADXL372_X_THRESH_INACT_H,
197 };
198
199 enum adxl372_fifo_format {
200 ADXL372_XYZ_FIFO,
201 ADXL372_X_FIFO,
202 ADXL372_Y_FIFO,
203 ADXL372_XY_FIFO,
204 ADXL372_Z_FIFO,
205 ADXL372_XZ_FIFO,
206 ADXL372_YZ_FIFO,
207 ADXL372_XYZ_PEAK_FIFO,
208 };
209
210 enum adxl372_fifo_mode {
211 ADXL372_FIFO_BYPASSED,
212 ADXL372_FIFO_STREAMED,
213 ADXL372_FIFO_TRIGGERED,
214 ADXL372_FIFO_OLD_SAVED
215 };
216
217 static const int adxl372_samp_freq_tbl[5] = {
218 400, 800, 1600, 3200, 6400,
219 };
220
221 static const int adxl372_bw_freq_tbl[5] = {
222 200, 400, 800, 1600, 3200,
223 };
224
225 struct adxl372_axis_lookup {
226 unsigned int bits;
227 enum adxl372_fifo_format fifo_format;
228 };
229
230 static const struct adxl372_axis_lookup adxl372_axis_lookup_table[] = {
231 { BIT(0), ADXL372_X_FIFO },
232 { BIT(1), ADXL372_Y_FIFO },
233 { BIT(2), ADXL372_Z_FIFO },
234 { BIT(0) | BIT(1), ADXL372_XY_FIFO },
235 { BIT(0) | BIT(2), ADXL372_XZ_FIFO },
236 { BIT(1) | BIT(2), ADXL372_YZ_FIFO },
237 { BIT(0) | BIT(1) | BIT(2), ADXL372_XYZ_FIFO },
238 };
239
240 static const struct iio_event_spec adxl372_events[] = {
241 {
242 .type = IIO_EV_TYPE_THRESH,
243 .dir = IIO_EV_DIR_RISING,
244 .mask_separate = BIT(IIO_EV_INFO_VALUE),
245 .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD) | BIT(IIO_EV_INFO_ENABLE),
246 }, {
247 .type = IIO_EV_TYPE_THRESH,
248 .dir = IIO_EV_DIR_FALLING,
249 .mask_separate = BIT(IIO_EV_INFO_VALUE),
250 .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD) | BIT(IIO_EV_INFO_ENABLE),
251 },
252 };
253
254 #define ADXL372_ACCEL_CHANNEL(index, reg, axis) { \
255 .type = IIO_ACCEL, \
256 .address = reg, \
257 .modified = 1, \
258 .channel2 = IIO_MOD_##axis, \
259 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
260 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
261 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
262 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
263 .scan_index = index, \
264 .scan_type = { \
265 .sign = 's', \
266 .realbits = 12, \
267 .storagebits = 16, \
268 .shift = 4, \
269 .endianness = IIO_BE, \
270 }, \
271 .event_spec = adxl372_events, \
272 .num_event_specs = ARRAY_SIZE(adxl372_events) \
273 }
274
275 static const struct iio_chan_spec adxl372_channels[] = {
276 ADXL372_ACCEL_CHANNEL(0, ADXL372_X_DATA_H, X),
277 ADXL372_ACCEL_CHANNEL(1, ADXL372_Y_DATA_H, Y),
278 ADXL372_ACCEL_CHANNEL(2, ADXL372_Z_DATA_H, Z),
279 };
280
281 struct adxl372_state {
282 int irq;
283 struct device *dev;
284 struct regmap *regmap;
285 struct iio_trigger *dready_trig;
286 struct iio_trigger *peak_datardy_trig;
287 enum adxl372_fifo_mode fifo_mode;
288 enum adxl372_fifo_format fifo_format;
289 unsigned int fifo_axis_mask;
290 enum adxl372_op_mode op_mode;
291 enum adxl372_act_proc_mode act_proc_mode;
292 enum adxl372_odr odr;
293 enum adxl372_bandwidth bw;
294 u32 act_time_ms;
295 u32 inact_time_ms;
296 u8 fifo_set_size;
297 unsigned long int1_bitmask;
298 unsigned long int2_bitmask;
299 u16 watermark;
300 __be16 fifo_buf[ADXL372_FIFO_SIZE];
301 bool peak_fifo_mode_en;
302 struct mutex threshold_m; /* lock for threshold */
303 };
304
305 static const unsigned long adxl372_channel_masks[] = {
306 BIT(0), BIT(1), BIT(2),
307 BIT(0) | BIT(1),
308 BIT(0) | BIT(2),
309 BIT(1) | BIT(2),
310 BIT(0) | BIT(1) | BIT(2),
311 0
312 };
313
adxl372_read_threshold_value(struct iio_dev * indio_dev,unsigned int addr,u16 * threshold)314 static ssize_t adxl372_read_threshold_value(struct iio_dev *indio_dev, unsigned int addr,
315 u16 *threshold)
316 {
317 struct adxl372_state *st = iio_priv(indio_dev);
318 __be16 raw_regval;
319 u16 regval;
320 int ret;
321
322 ret = regmap_bulk_read(st->regmap, addr, &raw_regval, sizeof(raw_regval));
323 if (ret < 0)
324 return ret;
325
326 regval = be16_to_cpu(raw_regval);
327 regval >>= 5;
328
329 *threshold = regval;
330
331 return 0;
332 }
333
adxl372_write_threshold_value(struct iio_dev * indio_dev,unsigned int addr,u16 threshold)334 static ssize_t adxl372_write_threshold_value(struct iio_dev *indio_dev, unsigned int addr,
335 u16 threshold)
336 {
337 struct adxl372_state *st = iio_priv(indio_dev);
338 int ret;
339
340 mutex_lock(&st->threshold_m);
341 ret = regmap_write(st->regmap, addr, ADXL372_THRESH_VAL_H_SEL(threshold));
342 if (ret < 0)
343 goto unlock;
344
345 ret = regmap_update_bits(st->regmap, addr + 1, GENMASK(7, 5),
346 ADXL372_THRESH_VAL_L_SEL(threshold) << 5);
347
348 unlock:
349 mutex_unlock(&st->threshold_m);
350
351 return ret;
352 }
353
adxl372_read_axis(struct adxl372_state * st,u8 addr)354 static int adxl372_read_axis(struct adxl372_state *st, u8 addr)
355 {
356 __be16 regval;
357 int ret;
358
359 ret = regmap_bulk_read(st->regmap, addr, ®val, sizeof(regval));
360 if (ret < 0)
361 return ret;
362
363 return be16_to_cpu(regval);
364 }
365
adxl372_set_op_mode(struct adxl372_state * st,enum adxl372_op_mode op_mode)366 static int adxl372_set_op_mode(struct adxl372_state *st,
367 enum adxl372_op_mode op_mode)
368 {
369 int ret;
370
371 ret = regmap_update_bits(st->regmap, ADXL372_POWER_CTL,
372 ADXL372_POWER_CTL_MODE_MSK,
373 ADXL372_POWER_CTL_MODE(op_mode));
374 if (ret < 0)
375 return ret;
376
377 st->op_mode = op_mode;
378
379 return ret;
380 }
381
adxl372_set_odr(struct adxl372_state * st,enum adxl372_odr odr)382 static int adxl372_set_odr(struct adxl372_state *st,
383 enum adxl372_odr odr)
384 {
385 int ret;
386
387 ret = regmap_update_bits(st->regmap, ADXL372_TIMING,
388 ADXL372_TIMING_ODR_MSK,
389 ADXL372_TIMING_ODR_MODE(odr));
390 if (ret < 0)
391 return ret;
392
393 st->odr = odr;
394
395 return ret;
396 }
397
adxl372_find_closest_match(const int * array,unsigned int size,int val)398 static int adxl372_find_closest_match(const int *array,
399 unsigned int size, int val)
400 {
401 int i;
402
403 for (i = 0; i < size; i++) {
404 if (val <= array[i])
405 return i;
406 }
407
408 return size - 1;
409 }
410
adxl372_set_bandwidth(struct adxl372_state * st,enum adxl372_bandwidth bw)411 static int adxl372_set_bandwidth(struct adxl372_state *st,
412 enum adxl372_bandwidth bw)
413 {
414 int ret;
415
416 ret = regmap_update_bits(st->regmap, ADXL372_MEASURE,
417 ADXL372_MEASURE_BANDWIDTH_MSK,
418 ADXL372_MEASURE_BANDWIDTH_MODE(bw));
419 if (ret < 0)
420 return ret;
421
422 st->bw = bw;
423
424 return ret;
425 }
426
adxl372_set_act_proc_mode(struct adxl372_state * st,enum adxl372_act_proc_mode mode)427 static int adxl372_set_act_proc_mode(struct adxl372_state *st,
428 enum adxl372_act_proc_mode mode)
429 {
430 int ret;
431
432 ret = regmap_update_bits(st->regmap,
433 ADXL372_MEASURE,
434 ADXL372_MEASURE_LINKLOOP_MSK,
435 ADXL372_MEASURE_LINKLOOP_MODE(mode));
436 if (ret < 0)
437 return ret;
438
439 st->act_proc_mode = mode;
440
441 return ret;
442 }
443
adxl372_set_activity_threshold(struct adxl372_state * st,enum adxl372_th_activity act,bool ref_en,bool enable,unsigned int threshold)444 static int adxl372_set_activity_threshold(struct adxl372_state *st,
445 enum adxl372_th_activity act,
446 bool ref_en, bool enable,
447 unsigned int threshold)
448 {
449 unsigned char buf[6];
450 unsigned char th_reg_high_val, th_reg_low_val, th_reg_high_addr;
451
452 /* scale factor is 100 mg/code */
453 th_reg_high_val = (threshold / 100) >> 3;
454 th_reg_low_val = ((threshold / 100) << 5) | (ref_en << 1) | enable;
455 th_reg_high_addr = adxl372_th_reg_high_addr[act];
456
457 buf[0] = th_reg_high_val;
458 buf[1] = th_reg_low_val;
459 buf[2] = th_reg_high_val;
460 buf[3] = th_reg_low_val;
461 buf[4] = th_reg_high_val;
462 buf[5] = th_reg_low_val;
463
464 return regmap_bulk_write(st->regmap, th_reg_high_addr,
465 buf, ARRAY_SIZE(buf));
466 }
467
adxl372_set_activity_time_ms(struct adxl372_state * st,unsigned int act_time_ms)468 static int adxl372_set_activity_time_ms(struct adxl372_state *st,
469 unsigned int act_time_ms)
470 {
471 unsigned int reg_val, scale_factor;
472 int ret;
473
474 /*
475 * 3.3 ms per code is the scale factor of the TIME_ACT register for
476 * ODR = 6400 Hz. It is 6.6 ms per code for ODR = 3200 Hz and below.
477 */
478 if (st->odr == ADXL372_ODR_6400HZ)
479 scale_factor = 3300;
480 else
481 scale_factor = 6600;
482
483 reg_val = DIV_ROUND_CLOSEST(act_time_ms * 1000, scale_factor);
484
485 /* TIME_ACT register is 8 bits wide */
486 if (reg_val > 0xFF)
487 reg_val = 0xFF;
488
489 ret = regmap_write(st->regmap, ADXL372_TIME_ACT, reg_val);
490 if (ret < 0)
491 return ret;
492
493 st->act_time_ms = act_time_ms;
494
495 return ret;
496 }
497
adxl372_set_inactivity_time_ms(struct adxl372_state * st,unsigned int inact_time_ms)498 static int adxl372_set_inactivity_time_ms(struct adxl372_state *st,
499 unsigned int inact_time_ms)
500 {
501 unsigned int reg_val_h, reg_val_l, res, scale_factor;
502 int ret;
503
504 /*
505 * 13 ms per code is the scale factor of the TIME_INACT register for
506 * ODR = 6400 Hz. It is 26 ms per code for ODR = 3200 Hz and below.
507 */
508 if (st->odr == ADXL372_ODR_6400HZ)
509 scale_factor = 13;
510 else
511 scale_factor = 26;
512
513 res = DIV_ROUND_CLOSEST(inact_time_ms, scale_factor);
514 reg_val_h = (res >> 8) & 0xFF;
515 reg_val_l = res & 0xFF;
516
517 ret = regmap_write(st->regmap, ADXL372_TIME_INACT_H, reg_val_h);
518 if (ret < 0)
519 return ret;
520
521 ret = regmap_write(st->regmap, ADXL372_TIME_INACT_L, reg_val_l);
522 if (ret < 0)
523 return ret;
524
525 st->inact_time_ms = inact_time_ms;
526
527 return ret;
528 }
529
adxl372_set_interrupts(struct adxl372_state * st,unsigned long int1_bitmask,unsigned long int2_bitmask)530 static int adxl372_set_interrupts(struct adxl372_state *st,
531 unsigned long int1_bitmask,
532 unsigned long int2_bitmask)
533 {
534 int ret;
535
536 ret = regmap_write(st->regmap, ADXL372_INT1_MAP, int1_bitmask);
537 if (ret < 0)
538 return ret;
539
540 return regmap_write(st->regmap, ADXL372_INT2_MAP, int2_bitmask);
541 }
542
adxl372_configure_fifo(struct adxl372_state * st)543 static int adxl372_configure_fifo(struct adxl372_state *st)
544 {
545 unsigned int fifo_samples, fifo_ctl;
546 int ret;
547
548 /* FIFO must be configured while in standby mode */
549 ret = adxl372_set_op_mode(st, ADXL372_STANDBY);
550 if (ret < 0)
551 return ret;
552
553 /*
554 * watermark stores the number of sets; we need to write the FIFO
555 * registers with the number of samples
556 */
557 fifo_samples = (st->watermark * st->fifo_set_size);
558 fifo_ctl = ADXL372_FIFO_CTL_FORMAT_MODE(st->fifo_format) |
559 ADXL372_FIFO_CTL_MODE_MODE(st->fifo_mode) |
560 ADXL372_FIFO_CTL_SAMPLES_MODE(fifo_samples);
561
562 ret = regmap_write(st->regmap,
563 ADXL372_FIFO_SAMPLES, fifo_samples & 0xFF);
564 if (ret < 0)
565 return ret;
566
567 ret = regmap_write(st->regmap, ADXL372_FIFO_CTL, fifo_ctl);
568 if (ret < 0)
569 return ret;
570
571 return adxl372_set_op_mode(st, ADXL372_FULL_BW_MEASUREMENT);
572 }
573
adxl372_get_status(struct adxl372_state * st,u8 * status1,u8 * status2,u16 * fifo_entries)574 static int adxl372_get_status(struct adxl372_state *st,
575 u8 *status1, u8 *status2,
576 u16 *fifo_entries)
577 {
578 __be32 buf;
579 u32 val;
580 int ret;
581
582 /* STATUS1, STATUS2, FIFO_ENTRIES2 and FIFO_ENTRIES are adjacent regs */
583 ret = regmap_bulk_read(st->regmap, ADXL372_STATUS_1,
584 &buf, sizeof(buf));
585 if (ret < 0)
586 return ret;
587
588 val = be32_to_cpu(buf);
589
590 *status1 = (val >> 24) & 0x0F;
591 *status2 = (val >> 16) & 0x0F;
592 /*
593 * FIFO_ENTRIES contains the least significant byte, and FIFO_ENTRIES2
594 * contains the two most significant bits
595 */
596 *fifo_entries = val & 0x3FF;
597
598 return ret;
599 }
600
adxl372_arrange_axis_data(struct adxl372_state * st,__be16 * sample)601 static void adxl372_arrange_axis_data(struct adxl372_state *st, __be16 *sample)
602 {
603 __be16 axis_sample[3] = { };
604 int i = 0;
605
606 if (ADXL372_X_AXIS_EN(st->fifo_axis_mask))
607 axis_sample[i++] = sample[0];
608 if (ADXL372_Y_AXIS_EN(st->fifo_axis_mask))
609 axis_sample[i++] = sample[1];
610 if (ADXL372_Z_AXIS_EN(st->fifo_axis_mask))
611 axis_sample[i++] = sample[2];
612
613 memcpy(sample, axis_sample, 3 * sizeof(__be16));
614 }
615
adxl372_push_event(struct iio_dev * indio_dev,s64 timestamp,u8 status2)616 static void adxl372_push_event(struct iio_dev *indio_dev, s64 timestamp, u8 status2)
617 {
618 unsigned int ev_dir = IIO_EV_DIR_NONE;
619
620 if (ADXL372_STATUS_2_ACT(status2))
621 ev_dir = IIO_EV_DIR_RISING;
622
623 if (ADXL372_STATUS_2_INACT(status2))
624 ev_dir = IIO_EV_DIR_FALLING;
625
626 if (ev_dir != IIO_EV_DIR_NONE)
627 iio_push_event(indio_dev,
628 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
629 IIO_EV_TYPE_THRESH, ev_dir),
630 timestamp);
631 }
632
adxl372_trigger_handler(int irq,void * p)633 static irqreturn_t adxl372_trigger_handler(int irq, void *p)
634 {
635 struct iio_poll_func *pf = p;
636 struct iio_dev *indio_dev = pf->indio_dev;
637 struct adxl372_state *st = iio_priv(indio_dev);
638 u8 status1, status2;
639 u16 fifo_entries;
640 int i, ret;
641
642 ret = adxl372_get_status(st, &status1, &status2, &fifo_entries);
643 if (ret < 0)
644 goto err;
645
646 adxl372_push_event(indio_dev, iio_get_time_ns(indio_dev), status2);
647
648 if (st->fifo_mode != ADXL372_FIFO_BYPASSED &&
649 ADXL372_STATUS_1_FIFO_FULL(status1)) {
650 /*
651 * When reading data from multiple axes from the FIFO,
652 * to ensure that data is not overwritten and stored out
653 * of order at least one sample set must be left in the
654 * FIFO after every read.
655 */
656 fifo_entries -= st->fifo_set_size;
657
658 /* Read data from the FIFO */
659 ret = regmap_noinc_read(st->regmap, ADXL372_FIFO_DATA,
660 st->fifo_buf,
661 fifo_entries * sizeof(u16));
662 if (ret < 0)
663 goto err;
664
665 /* Each sample is 2 bytes */
666 for (i = 0; i < fifo_entries; i += st->fifo_set_size) {
667 /* filter peak detection data */
668 if (st->peak_fifo_mode_en)
669 adxl372_arrange_axis_data(st, &st->fifo_buf[i]);
670 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
671 }
672 }
673 err:
674 iio_trigger_notify_done(indio_dev->trig);
675 return IRQ_HANDLED;
676 }
677
adxl372_setup(struct adxl372_state * st)678 static int adxl372_setup(struct adxl372_state *st)
679 {
680 unsigned int regval;
681 int ret;
682
683 ret = regmap_read(st->regmap, ADXL372_DEVID, ®val);
684 if (ret < 0)
685 return ret;
686
687 if (regval != ADXL372_DEVID_VAL) {
688 dev_err(st->dev, "Invalid chip id %x\n", regval);
689 return -ENODEV;
690 }
691
692 /*
693 * Perform a software reset to make sure the device is in a consistent
694 * state after start up.
695 */
696 ret = regmap_write(st->regmap, ADXL372_RESET, ADXL372_RESET_CODE);
697 if (ret < 0)
698 return ret;
699
700 ret = adxl372_set_op_mode(st, ADXL372_STANDBY);
701 if (ret < 0)
702 return ret;
703
704 /* Set threshold for activity detection to 1g */
705 ret = adxl372_set_activity_threshold(st, ADXL372_ACTIVITY,
706 true, true, 1000);
707 if (ret < 0)
708 return ret;
709
710 /* Set threshold for inactivity detection to 100mg */
711 ret = adxl372_set_activity_threshold(st, ADXL372_INACTIVITY,
712 true, true, 100);
713 if (ret < 0)
714 return ret;
715
716 /* Set activity processing in Looped mode */
717 ret = adxl372_set_act_proc_mode(st, ADXL372_LOOPED);
718 if (ret < 0)
719 return ret;
720
721 ret = adxl372_set_odr(st, ADXL372_ODR_6400HZ);
722 if (ret < 0)
723 return ret;
724
725 ret = adxl372_set_bandwidth(st, ADXL372_BW_3200HZ);
726 if (ret < 0)
727 return ret;
728
729 /* Set activity timer to 1ms */
730 ret = adxl372_set_activity_time_ms(st, 1);
731 if (ret < 0)
732 return ret;
733
734 /* Set inactivity timer to 10s */
735 ret = adxl372_set_inactivity_time_ms(st, 10000);
736 if (ret < 0)
737 return ret;
738
739 /* Set the mode of operation to full bandwidth measurement mode */
740 return adxl372_set_op_mode(st, ADXL372_FULL_BW_MEASUREMENT);
741 }
742
adxl372_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)743 static int adxl372_reg_access(struct iio_dev *indio_dev,
744 unsigned int reg,
745 unsigned int writeval,
746 unsigned int *readval)
747 {
748 struct adxl372_state *st = iio_priv(indio_dev);
749
750 if (readval)
751 return regmap_read(st->regmap, reg, readval);
752 else
753 return regmap_write(st->regmap, reg, writeval);
754 }
755
adxl372_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)756 static int adxl372_read_raw(struct iio_dev *indio_dev,
757 struct iio_chan_spec const *chan,
758 int *val, int *val2, long info)
759 {
760 struct adxl372_state *st = iio_priv(indio_dev);
761 int ret;
762
763 switch (info) {
764 case IIO_CHAN_INFO_RAW:
765 if (!iio_device_claim_direct(indio_dev))
766 return -EBUSY;
767
768 ret = adxl372_read_axis(st, chan->address);
769 iio_device_release_direct(indio_dev);
770 if (ret < 0)
771 return ret;
772
773 *val = sign_extend32(ret >> chan->scan_type.shift,
774 chan->scan_type.realbits - 1);
775 return IIO_VAL_INT;
776 case IIO_CHAN_INFO_SCALE:
777 *val = 0;
778 *val2 = ADXL372_USCALE;
779 return IIO_VAL_INT_PLUS_MICRO;
780 case IIO_CHAN_INFO_SAMP_FREQ:
781 *val = adxl372_samp_freq_tbl[st->odr];
782 return IIO_VAL_INT;
783 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
784 *val = adxl372_bw_freq_tbl[st->bw];
785 return IIO_VAL_INT;
786 }
787
788 return -EINVAL;
789 }
790
adxl372_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)791 static int adxl372_write_raw(struct iio_dev *indio_dev,
792 struct iio_chan_spec const *chan,
793 int val, int val2, long info)
794 {
795 struct adxl372_state *st = iio_priv(indio_dev);
796 int odr_index, bw_index, ret;
797
798 switch (info) {
799 case IIO_CHAN_INFO_SAMP_FREQ:
800 odr_index = adxl372_find_closest_match(adxl372_samp_freq_tbl,
801 ARRAY_SIZE(adxl372_samp_freq_tbl),
802 val);
803 ret = adxl372_set_odr(st, odr_index);
804 if (ret < 0)
805 return ret;
806 /*
807 * The timer period depends on the ODR selected.
808 * At 3200 Hz and below, it is 6.6 ms; at 6400 Hz, it is 3.3 ms
809 */
810 ret = adxl372_set_activity_time_ms(st, st->act_time_ms);
811 if (ret < 0)
812 return ret;
813 /*
814 * The timer period depends on the ODR selected.
815 * At 3200 Hz and below, it is 26 ms; at 6400 Hz, it is 13 ms
816 */
817 ret = adxl372_set_inactivity_time_ms(st, st->inact_time_ms);
818 if (ret < 0)
819 return ret;
820 /*
821 * The maximum bandwidth is constrained to at most half of
822 * the ODR to ensure that the Nyquist criteria is not violated
823 */
824 if (st->bw > odr_index)
825 ret = adxl372_set_bandwidth(st, odr_index);
826
827 return ret;
828 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
829 bw_index = adxl372_find_closest_match(adxl372_bw_freq_tbl,
830 ARRAY_SIZE(adxl372_bw_freq_tbl),
831 val);
832 return adxl372_set_bandwidth(st, bw_index);
833 default:
834 return -EINVAL;
835 }
836 }
837
adxl372_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)838 static int adxl372_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
839 enum iio_event_type type, enum iio_event_direction dir,
840 enum iio_event_info info, int *val, int *val2)
841 {
842 struct adxl372_state *st = iio_priv(indio_dev);
843 unsigned int addr;
844 u16 raw_value;
845 int ret;
846
847 switch (info) {
848 case IIO_EV_INFO_VALUE:
849 switch (dir) {
850 case IIO_EV_DIR_RISING:
851 addr = ADXL372_X_THRESH_ACT_H + 2 * chan->scan_index;
852 ret = adxl372_read_threshold_value(indio_dev, addr, &raw_value);
853 if (ret < 0)
854 return ret;
855 *val = raw_value * ADXL372_USCALE;
856 *val2 = 1000000;
857 return IIO_VAL_FRACTIONAL;
858 case IIO_EV_DIR_FALLING:
859 addr = ADXL372_X_THRESH_INACT_H + 2 * chan->scan_index;
860 ret = adxl372_read_threshold_value(indio_dev, addr, &raw_value);
861 if (ret < 0)
862 return ret;
863 *val = raw_value * ADXL372_USCALE;
864 *val2 = 1000000;
865 return IIO_VAL_FRACTIONAL;
866 default:
867 return -EINVAL;
868 }
869 case IIO_EV_INFO_PERIOD:
870 switch (dir) {
871 case IIO_EV_DIR_RISING:
872 *val = st->act_time_ms;
873 *val2 = 1000;
874 return IIO_VAL_FRACTIONAL;
875 case IIO_EV_DIR_FALLING:
876 *val = st->inact_time_ms;
877 *val2 = 1000;
878 return IIO_VAL_FRACTIONAL;
879 default:
880 return -EINVAL;
881 }
882 default:
883 return -EINVAL;
884 }
885 }
886
adxl372_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)887 static int adxl372_write_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
888 enum iio_event_type type, enum iio_event_direction dir,
889 enum iio_event_info info, int val, int val2)
890 {
891 struct adxl372_state *st = iio_priv(indio_dev);
892 unsigned int val_ms;
893 unsigned int addr;
894 u16 raw_val;
895
896 switch (info) {
897 case IIO_EV_INFO_VALUE:
898 raw_val = DIV_ROUND_UP(val * 1000000, ADXL372_USCALE);
899 switch (dir) {
900 case IIO_EV_DIR_RISING:
901 addr = ADXL372_X_THRESH_ACT_H + 2 * chan->scan_index;
902 return adxl372_write_threshold_value(indio_dev, addr, raw_val);
903 case IIO_EV_DIR_FALLING:
904 addr = ADXL372_X_THRESH_INACT_H + 2 * chan->scan_index;
905 return adxl372_write_threshold_value(indio_dev, addr, raw_val);
906 default:
907 return -EINVAL;
908 }
909 case IIO_EV_INFO_PERIOD:
910 val_ms = val * 1000 + DIV_ROUND_UP(val2, 1000);
911 switch (dir) {
912 case IIO_EV_DIR_RISING:
913 return adxl372_set_activity_time_ms(st, val_ms);
914 case IIO_EV_DIR_FALLING:
915 return adxl372_set_inactivity_time_ms(st, val_ms);
916 default:
917 return -EINVAL;
918 }
919 default:
920 return -EINVAL;
921 }
922 }
923
adxl372_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)924 static int adxl372_read_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
925 enum iio_event_type type, enum iio_event_direction dir)
926 {
927 struct adxl372_state *st = iio_priv(indio_dev);
928
929 switch (dir) {
930 case IIO_EV_DIR_RISING:
931 return FIELD_GET(ADXL372_INT1_MAP_ACT_MSK, st->int1_bitmask);
932 case IIO_EV_DIR_FALLING:
933 return FIELD_GET(ADXL372_INT1_MAP_INACT_MSK, st->int1_bitmask);
934 default:
935 return -EINVAL;
936 }
937 }
938
adxl372_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)939 static int adxl372_write_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan,
940 enum iio_event_type type, enum iio_event_direction dir,
941 bool state)
942 {
943 struct adxl372_state *st = iio_priv(indio_dev);
944
945 switch (dir) {
946 case IIO_EV_DIR_RISING:
947 set_mask_bits(&st->int1_bitmask, ADXL372_INT1_MAP_ACT_MSK,
948 ADXL372_INT1_MAP_ACT_MODE(state));
949 break;
950 case IIO_EV_DIR_FALLING:
951 set_mask_bits(&st->int1_bitmask, ADXL372_INT1_MAP_INACT_MSK,
952 ADXL372_INT1_MAP_INACT_MODE(state));
953 break;
954 default:
955 return -EINVAL;
956 }
957
958 return adxl372_set_interrupts(st, st->int1_bitmask, 0);
959 }
960
adxl372_show_filter_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)961 static ssize_t adxl372_show_filter_freq_avail(struct device *dev,
962 struct device_attribute *attr,
963 char *buf)
964 {
965 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
966 struct adxl372_state *st = iio_priv(indio_dev);
967 int i;
968 size_t len = 0;
969
970 for (i = 0; i <= st->odr; i++)
971 len += scnprintf(buf + len, PAGE_SIZE - len,
972 "%d ", adxl372_bw_freq_tbl[i]);
973
974 buf[len - 1] = '\n';
975
976 return len;
977 }
978
adxl372_get_fifo_enabled(struct device * dev,struct device_attribute * attr,char * buf)979 static ssize_t adxl372_get_fifo_enabled(struct device *dev,
980 struct device_attribute *attr,
981 char *buf)
982 {
983 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
984 struct adxl372_state *st = iio_priv(indio_dev);
985
986 return sprintf(buf, "%d\n", st->fifo_mode);
987 }
988
adxl372_get_fifo_watermark(struct device * dev,struct device_attribute * attr,char * buf)989 static ssize_t adxl372_get_fifo_watermark(struct device *dev,
990 struct device_attribute *attr,
991 char *buf)
992 {
993 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
994 struct adxl372_state *st = iio_priv(indio_dev);
995
996 return sprintf(buf, "%d\n", st->watermark);
997 }
998
999 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1");
1000 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max,
1001 __stringify(ADXL372_FIFO_SIZE));
1002 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1003 adxl372_get_fifo_watermark, NULL, 0);
1004 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1005 adxl372_get_fifo_enabled, NULL, 0);
1006
1007 static const struct iio_dev_attr *adxl372_fifo_attributes[] = {
1008 &iio_dev_attr_hwfifo_watermark_min,
1009 &iio_dev_attr_hwfifo_watermark_max,
1010 &iio_dev_attr_hwfifo_watermark,
1011 &iio_dev_attr_hwfifo_enabled,
1012 NULL,
1013 };
1014
adxl372_set_watermark(struct iio_dev * indio_dev,unsigned int val)1015 static int adxl372_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1016 {
1017 struct adxl372_state *st = iio_priv(indio_dev);
1018
1019 if (val > ADXL372_FIFO_SIZE)
1020 val = ADXL372_FIFO_SIZE;
1021
1022 st->watermark = val;
1023
1024 return 0;
1025 }
1026
adxl372_buffer_postenable(struct iio_dev * indio_dev)1027 static int adxl372_buffer_postenable(struct iio_dev *indio_dev)
1028 {
1029 struct adxl372_state *st = iio_priv(indio_dev);
1030 unsigned int mask;
1031 int i, ret;
1032
1033 st->int1_bitmask |= ADXL372_INT1_MAP_FIFO_FULL_MSK;
1034 ret = adxl372_set_interrupts(st, st->int1_bitmask, 0);
1035 if (ret < 0)
1036 return ret;
1037
1038 mask = *indio_dev->active_scan_mask;
1039
1040 for (i = 0; i < ARRAY_SIZE(adxl372_axis_lookup_table); i++) {
1041 if (mask == adxl372_axis_lookup_table[i].bits)
1042 break;
1043 }
1044
1045 if (i == ARRAY_SIZE(adxl372_axis_lookup_table))
1046 return -EINVAL;
1047
1048 st->fifo_format = adxl372_axis_lookup_table[i].fifo_format;
1049 st->fifo_axis_mask = adxl372_axis_lookup_table[i].bits;
1050 st->fifo_set_size = bitmap_weight(indio_dev->active_scan_mask,
1051 iio_get_masklength(indio_dev));
1052
1053 /* Configure the FIFO to store sets of impact event peak. */
1054 if (st->peak_fifo_mode_en) {
1055 st->fifo_set_size = 3;
1056 st->fifo_format = ADXL372_XYZ_PEAK_FIFO;
1057 }
1058
1059 /*
1060 * The 512 FIFO samples can be allotted in several ways, such as:
1061 * 170 sample sets of concurrent 3-axis data
1062 * 256 sample sets of concurrent 2-axis data (user selectable)
1063 * 512 sample sets of single-axis data
1064 * 170 sets of impact event peak (x, y, z)
1065 */
1066 if ((st->watermark * st->fifo_set_size) > ADXL372_FIFO_SIZE)
1067 st->watermark = (ADXL372_FIFO_SIZE / st->fifo_set_size);
1068
1069 st->fifo_mode = ADXL372_FIFO_STREAMED;
1070
1071 ret = adxl372_configure_fifo(st);
1072 if (ret < 0) {
1073 st->fifo_mode = ADXL372_FIFO_BYPASSED;
1074 st->int1_bitmask &= ~ADXL372_INT1_MAP_FIFO_FULL_MSK;
1075 adxl372_set_interrupts(st, st->int1_bitmask, 0);
1076 return ret;
1077 }
1078
1079 return 0;
1080 }
1081
adxl372_buffer_predisable(struct iio_dev * indio_dev)1082 static int adxl372_buffer_predisable(struct iio_dev *indio_dev)
1083 {
1084 struct adxl372_state *st = iio_priv(indio_dev);
1085
1086 st->int1_bitmask &= ~ADXL372_INT1_MAP_FIFO_FULL_MSK;
1087 adxl372_set_interrupts(st, st->int1_bitmask, 0);
1088 st->fifo_mode = ADXL372_FIFO_BYPASSED;
1089 adxl372_configure_fifo(st);
1090
1091 return 0;
1092 }
1093
1094 static const struct iio_buffer_setup_ops adxl372_buffer_ops = {
1095 .postenable = adxl372_buffer_postenable,
1096 .predisable = adxl372_buffer_predisable,
1097 };
1098
adxl372_dready_trig_set_state(struct iio_trigger * trig,bool state)1099 static int adxl372_dready_trig_set_state(struct iio_trigger *trig,
1100 bool state)
1101 {
1102 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1103 struct adxl372_state *st = iio_priv(indio_dev);
1104
1105 if (state)
1106 st->int1_bitmask |= ADXL372_INT1_MAP_FIFO_FULL_MSK;
1107
1108 return adxl372_set_interrupts(st, st->int1_bitmask, 0);
1109 }
1110
adxl372_validate_trigger(struct iio_dev * indio_dev,struct iio_trigger * trig)1111 static int adxl372_validate_trigger(struct iio_dev *indio_dev,
1112 struct iio_trigger *trig)
1113 {
1114 struct adxl372_state *st = iio_priv(indio_dev);
1115
1116 if (st->dready_trig != trig && st->peak_datardy_trig != trig)
1117 return -EINVAL;
1118
1119 return 0;
1120 }
1121
1122 static const struct iio_trigger_ops adxl372_trigger_ops = {
1123 .validate_device = &iio_trigger_validate_own_device,
1124 .set_trigger_state = adxl372_dready_trig_set_state,
1125 };
1126
adxl372_peak_dready_trig_set_state(struct iio_trigger * trig,bool state)1127 static int adxl372_peak_dready_trig_set_state(struct iio_trigger *trig,
1128 bool state)
1129 {
1130 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1131 struct adxl372_state *st = iio_priv(indio_dev);
1132
1133 if (state)
1134 st->int1_bitmask |= ADXL372_INT1_MAP_FIFO_FULL_MSK;
1135
1136 st->peak_fifo_mode_en = state;
1137
1138 return adxl372_set_interrupts(st, st->int1_bitmask, 0);
1139 }
1140
1141 static const struct iio_trigger_ops adxl372_peak_data_trigger_ops = {
1142 .validate_device = &iio_trigger_validate_own_device,
1143 .set_trigger_state = adxl372_peak_dready_trig_set_state,
1144 };
1145
1146 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("400 800 1600 3200 6400");
1147 static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
1148 0444, adxl372_show_filter_freq_avail, NULL, 0);
1149
1150 static struct attribute *adxl372_attributes[] = {
1151 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1152 &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr,
1153 NULL,
1154 };
1155
1156 static const struct attribute_group adxl372_attrs_group = {
1157 .attrs = adxl372_attributes,
1158 };
1159
1160 static const struct iio_info adxl372_info = {
1161 .validate_trigger = &adxl372_validate_trigger,
1162 .attrs = &adxl372_attrs_group,
1163 .read_raw = adxl372_read_raw,
1164 .write_raw = adxl372_write_raw,
1165 .read_event_config = adxl372_read_event_config,
1166 .write_event_config = adxl372_write_event_config,
1167 .read_event_value = adxl372_read_event_value,
1168 .write_event_value = adxl372_write_event_value,
1169 .debugfs_reg_access = &adxl372_reg_access,
1170 .hwfifo_set_watermark = adxl372_set_watermark,
1171 };
1172
adxl372_readable_noinc_reg(struct device * dev,unsigned int reg)1173 bool adxl372_readable_noinc_reg(struct device *dev, unsigned int reg)
1174 {
1175 return (reg == ADXL372_FIFO_DATA);
1176 }
1177 EXPORT_SYMBOL_NS_GPL(adxl372_readable_noinc_reg, "IIO_ADXL372");
1178
adxl372_probe(struct device * dev,struct regmap * regmap,int irq,const char * name)1179 int adxl372_probe(struct device *dev, struct regmap *regmap,
1180 int irq, const char *name)
1181 {
1182 struct iio_dev *indio_dev;
1183 struct adxl372_state *st;
1184 int ret;
1185
1186 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1187 if (!indio_dev)
1188 return -ENOMEM;
1189
1190 st = iio_priv(indio_dev);
1191 dev_set_drvdata(dev, indio_dev);
1192
1193 st->dev = dev;
1194 st->regmap = regmap;
1195 st->irq = irq;
1196
1197 mutex_init(&st->threshold_m);
1198
1199 indio_dev->channels = adxl372_channels;
1200 indio_dev->num_channels = ARRAY_SIZE(adxl372_channels);
1201 indio_dev->available_scan_masks = adxl372_channel_masks;
1202 indio_dev->name = name;
1203 indio_dev->info = &adxl372_info;
1204 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1205
1206 ret = adxl372_setup(st);
1207 if (ret < 0) {
1208 dev_err(dev, "ADXL372 setup failed\n");
1209 return ret;
1210 }
1211
1212 ret = devm_iio_triggered_buffer_setup_ext(dev,
1213 indio_dev, NULL,
1214 adxl372_trigger_handler,
1215 IIO_BUFFER_DIRECTION_IN,
1216 &adxl372_buffer_ops,
1217 adxl372_fifo_attributes);
1218 if (ret < 0)
1219 return ret;
1220
1221 if (st->irq) {
1222 st->dready_trig = devm_iio_trigger_alloc(dev,
1223 "%s-dev%d",
1224 indio_dev->name,
1225 iio_device_id(indio_dev));
1226 if (st->dready_trig == NULL)
1227 return -ENOMEM;
1228
1229 st->peak_datardy_trig = devm_iio_trigger_alloc(dev,
1230 "%s-dev%d-peak",
1231 indio_dev->name,
1232 iio_device_id(indio_dev));
1233 if (!st->peak_datardy_trig)
1234 return -ENOMEM;
1235
1236 st->dready_trig->ops = &adxl372_trigger_ops;
1237 st->peak_datardy_trig->ops = &adxl372_peak_data_trigger_ops;
1238 iio_trigger_set_drvdata(st->dready_trig, indio_dev);
1239 iio_trigger_set_drvdata(st->peak_datardy_trig, indio_dev);
1240 ret = devm_iio_trigger_register(dev, st->dready_trig);
1241 if (ret < 0)
1242 return ret;
1243
1244 ret = devm_iio_trigger_register(dev, st->peak_datardy_trig);
1245 if (ret < 0)
1246 return ret;
1247
1248 indio_dev->trig = iio_trigger_get(st->dready_trig);
1249
1250 ret = devm_request_threaded_irq(dev, st->irq,
1251 iio_trigger_generic_data_rdy_poll,
1252 NULL,
1253 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1254 indio_dev->name, st->dready_trig);
1255 if (ret < 0)
1256 return ret;
1257 }
1258
1259 return devm_iio_device_register(dev, indio_dev);
1260 }
1261 EXPORT_SYMBOL_NS_GPL(adxl372_probe, "IIO_ADXL372");
1262
1263 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1264 MODULE_DESCRIPTION("Analog Devices ADXL372 3-axis accelerometer driver");
1265 MODULE_LICENSE("GPL");
1266