1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 4 * 5 * Copyright (c) 1995-2000 Advanced System Products, Inc. 6 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc. 7 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx> 8 * Copyright (c) 2014 Hannes Reinecke <hare@suse.de> 9 * All Rights Reserved. 10 */ 11 12 /* 13 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys) 14 * changed its name to ConnectCom Solutions, Inc. 15 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets 16 */ 17 18 #include <linux/module.h> 19 #include <linux/string.h> 20 #include <linux/kernel.h> 21 #include <linux/types.h> 22 #include <linux/ioport.h> 23 #include <linux/interrupt.h> 24 #include <linux/delay.h> 25 #include <linux/slab.h> 26 #include <linux/mm.h> 27 #include <linux/proc_fs.h> 28 #include <linux/init.h> 29 #include <linux/blkdev.h> 30 #include <linux/isa.h> 31 #include <linux/eisa.h> 32 #include <linux/pci.h> 33 #include <linux/spinlock.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/firmware.h> 36 #include <linux/dmapool.h> 37 38 #include <asm/io.h> 39 40 #include <scsi/scsi_cmnd.h> 41 #include <scsi/scsi_device.h> 42 #include <scsi/scsi_tcq.h> 43 #include <scsi/scsi.h> 44 #include <scsi/scsi_host.h> 45 46 #define DRV_NAME "advansys" 47 #define ASC_VERSION "3.5" /* AdvanSys Driver Version */ 48 49 /* FIXME: 50 * 51 * 1. Use scsi_transport_spi 52 * 2. advansys_info is not safe against multiple simultaneous callers 53 * 3. Add module_param to override ISA/VLB ioport array 54 */ 55 56 /* Enable driver /proc statistics. */ 57 #define ADVANSYS_STATS 58 59 /* Enable driver tracing. */ 60 #undef ADVANSYS_DEBUG 61 62 typedef unsigned char uchar; 63 64 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0) 65 66 #define PCI_VENDOR_ID_ASP 0x10cd 67 #define PCI_DEVICE_ID_ASP_1200A 0x1100 68 #define PCI_DEVICE_ID_ASP_ABP940 0x1200 69 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300 70 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 71 #define PCI_DEVICE_ID_38C0800_REV1 0x2500 72 #define PCI_DEVICE_ID_38C1600_REV1 0x2700 73 74 #define PortAddr unsigned int /* port address size */ 75 #define inp(port) inb(port) 76 #define outp(port, byte) outb((byte), (port)) 77 78 #define inpw(port) inw(port) 79 #define outpw(port, word) outw((word), (port)) 80 81 #define ASC_MAX_SG_QUEUE 7 82 #define ASC_MAX_SG_LIST 255 83 84 #define ASC_CS_TYPE unsigned short 85 86 #define ASC_IS_EISA (0x0002) 87 #define ASC_IS_PCI (0x0004) 88 #define ASC_IS_PCI_ULTRA (0x0104) 89 #define ASC_IS_PCMCIA (0x0008) 90 #define ASC_IS_MCA (0x0020) 91 #define ASC_IS_VL (0x0040) 92 #define ASC_IS_WIDESCSI_16 (0x0100) 93 #define ASC_IS_WIDESCSI_32 (0x0200) 94 #define ASC_IS_BIG_ENDIAN (0x8000) 95 96 #define ASC_CHIP_MIN_VER_VL (0x01) 97 #define ASC_CHIP_MAX_VER_VL (0x07) 98 #define ASC_CHIP_MIN_VER_PCI (0x09) 99 #define ASC_CHIP_MAX_VER_PCI (0x0F) 100 #define ASC_CHIP_VER_PCI_BIT (0x08) 101 #define ASC_CHIP_VER_ASYN_BUG (0x21) 102 #define ASC_CHIP_VER_PCI 0x08 103 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02) 104 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03) 105 #define ASC_CHIP_MIN_VER_EISA (0x41) 106 #define ASC_CHIP_MAX_VER_EISA (0x47) 107 #define ASC_CHIP_VER_EISA_BIT (0x40) 108 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3) 109 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL) 110 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL) 111 112 #define ASC_SCSI_ID_BITS 3 113 #define ASC_SCSI_TIX_TYPE uchar 114 #define ASC_ALL_DEVICE_BIT_SET 0xFF 115 #define ASC_SCSI_BIT_ID_TYPE uchar 116 #define ASC_MAX_TID 7 117 #define ASC_MAX_LUN 7 118 #define ASC_SCSI_WIDTH_BIT_SET 0xFF 119 #define ASC_MAX_SENSE_LEN 32 120 #define ASC_MIN_SENSE_LEN 14 121 #define ASC_SCSI_RESET_HOLD_TIME_US 60 122 123 /* 124 * Narrow boards only support 12-byte commands, while wide boards 125 * extend to 16-byte commands. 126 */ 127 #define ASC_MAX_CDB_LEN 12 128 #define ADV_MAX_CDB_LEN 16 129 130 #define MS_SDTR_LEN 0x03 131 #define MS_WDTR_LEN 0x02 132 133 #define ASC_SG_LIST_PER_Q 7 134 #define QS_FREE 0x00 135 #define QS_READY 0x01 136 #define QS_DISC1 0x02 137 #define QS_DISC2 0x04 138 #define QS_BUSY 0x08 139 #define QS_ABORTED 0x40 140 #define QS_DONE 0x80 141 #define QC_NO_CALLBACK 0x01 142 #define QC_SG_SWAP_QUEUE 0x02 143 #define QC_SG_HEAD 0x04 144 #define QC_DATA_IN 0x08 145 #define QC_DATA_OUT 0x10 146 #define QC_URGENT 0x20 147 #define QC_MSG_OUT 0x40 148 #define QC_REQ_SENSE 0x80 149 #define QCSG_SG_XFER_LIST 0x02 150 #define QCSG_SG_XFER_MORE 0x04 151 #define QCSG_SG_XFER_END 0x08 152 #define QD_IN_PROGRESS 0x00 153 #define QD_NO_ERROR 0x01 154 #define QD_ABORTED_BY_HOST 0x02 155 #define QD_WITH_ERROR 0x04 156 #define QD_INVALID_REQUEST 0x80 157 #define QD_INVALID_HOST_NUM 0x81 158 #define QD_INVALID_DEVICE 0x82 159 #define QD_ERR_INTERNAL 0xFF 160 #define QHSTA_NO_ERROR 0x00 161 #define QHSTA_M_SEL_TIMEOUT 0x11 162 #define QHSTA_M_DATA_OVER_RUN 0x12 163 #define QHSTA_M_DATA_UNDER_RUN 0x12 164 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 165 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 166 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 167 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 168 #define QHSTA_D_HOST_ABORT_FAILED 0x23 169 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24 170 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 171 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26 172 #define QHSTA_M_WTM_TIMEOUT 0x41 173 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 174 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 175 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 176 #define QHSTA_M_TARGET_STATUS_BUSY 0x45 177 #define QHSTA_M_BAD_TAG_CODE 0x46 178 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 179 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 180 #define QHSTA_D_LRAM_CMP_ERROR 0x81 181 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 182 #define ASC_FLAG_SCSIQ_REQ 0x01 183 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02 184 #define ASC_FLAG_BIOS_ASYNC_IO 0x04 185 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08 186 #define ASC_FLAG_WIN16 0x10 187 #define ASC_FLAG_WIN32 0x20 188 #define ASC_FLAG_DOS_VM_CALLBACK 0x80 189 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10 190 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04 191 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 192 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 193 #define ASC_SCSIQ_CPY_BEG 4 194 #define ASC_SCSIQ_SGHD_CPY_BEG 2 195 #define ASC_SCSIQ_B_FWD 0 196 #define ASC_SCSIQ_B_BWD 1 197 #define ASC_SCSIQ_B_STATUS 2 198 #define ASC_SCSIQ_B_QNO 3 199 #define ASC_SCSIQ_B_CNTL 4 200 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5 201 #define ASC_SCSIQ_D_DATA_ADDR 8 202 #define ASC_SCSIQ_D_DATA_CNT 12 203 #define ASC_SCSIQ_B_SENSE_LEN 20 204 #define ASC_SCSIQ_DONE_INFO_BEG 22 205 #define ASC_SCSIQ_D_SRBPTR 22 206 #define ASC_SCSIQ_B_TARGET_IX 26 207 #define ASC_SCSIQ_B_CDB_LEN 28 208 #define ASC_SCSIQ_B_TAG_CODE 29 209 #define ASC_SCSIQ_W_VM_ID 30 210 #define ASC_SCSIQ_DONE_STATUS 32 211 #define ASC_SCSIQ_HOST_STATUS 33 212 #define ASC_SCSIQ_SCSI_STATUS 34 213 #define ASC_SCSIQ_CDB_BEG 36 214 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56 215 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60 216 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48 217 #define ASC_SCSIQ_B_SG_WK_QP 49 218 #define ASC_SCSIQ_B_SG_WK_IX 50 219 #define ASC_SCSIQ_W_ALT_DC1 52 220 #define ASC_SCSIQ_B_LIST_CNT 6 221 #define ASC_SCSIQ_B_CUR_LIST_CNT 7 222 #define ASC_SGQ_B_SG_CNTL 4 223 #define ASC_SGQ_B_SG_HEAD_QP 5 224 #define ASC_SGQ_B_SG_LIST_CNT 6 225 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7 226 #define ASC_SGQ_LIST_BEG 8 227 #define ASC_DEF_SCSI1_QNG 4 228 #define ASC_MAX_SCSI1_QNG 4 229 #define ASC_DEF_SCSI2_QNG 16 230 #define ASC_MAX_SCSI2_QNG 32 231 #define ASC_TAG_CODE_MASK 0x23 232 #define ASC_STOP_REQ_RISC_STOP 0x01 233 #define ASC_STOP_ACK_RISC_STOP 0x03 234 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10 235 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20 236 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40 237 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS)) 238 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid)) 239 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID)) 240 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID) 241 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID) 242 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN) 243 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6)) 244 245 typedef struct asc_scsiq_1 { 246 uchar status; 247 uchar q_no; 248 uchar cntl; 249 uchar sg_queue_cnt; 250 uchar target_id; 251 uchar target_lun; 252 __le32 data_addr; 253 __le32 data_cnt; 254 __le32 sense_addr; 255 uchar sense_len; 256 uchar extra_bytes; 257 } ASC_SCSIQ_1; 258 259 typedef struct asc_scsiq_2 { 260 u32 srb_tag; 261 uchar target_ix; 262 uchar flag; 263 uchar cdb_len; 264 uchar tag_code; 265 ushort vm_id; 266 } ASC_SCSIQ_2; 267 268 typedef struct asc_scsiq_3 { 269 uchar done_stat; 270 uchar host_stat; 271 uchar scsi_stat; 272 uchar scsi_msg; 273 } ASC_SCSIQ_3; 274 275 typedef struct asc_scsiq_4 { 276 uchar cdb[ASC_MAX_CDB_LEN]; 277 uchar y_first_sg_list_qp; 278 uchar y_working_sg_qp; 279 uchar y_working_sg_ix; 280 uchar y_res; 281 ushort x_req_count; 282 ushort x_reconnect_rtn; 283 __le32 x_saved_data_addr; 284 __le32 x_saved_data_cnt; 285 } ASC_SCSIQ_4; 286 287 typedef struct asc_q_done_info { 288 ASC_SCSIQ_2 d2; 289 ASC_SCSIQ_3 d3; 290 uchar q_status; 291 uchar q_no; 292 uchar cntl; 293 uchar sense_len; 294 uchar extra_bytes; 295 uchar res; 296 u32 remain_bytes; 297 } ASC_QDONE_INFO; 298 299 typedef struct asc_sg_list { 300 __le32 addr; 301 __le32 bytes; 302 } ASC_SG_LIST; 303 304 typedef struct asc_sg_head { 305 ushort entry_cnt; 306 ushort queue_cnt; 307 ushort entry_to_copy; 308 ushort res; 309 ASC_SG_LIST sg_list[]; 310 } ASC_SG_HEAD; 311 312 typedef struct asc_scsi_q { 313 ASC_SCSIQ_1 q1; 314 ASC_SCSIQ_2 q2; 315 uchar *cdbptr; 316 ASC_SG_HEAD *sg_head; 317 ushort remain_sg_entry_cnt; 318 ushort next_sg_index; 319 } ASC_SCSI_Q; 320 321 typedef struct asc_scsi_bios_req_q { 322 ASC_SCSIQ_1 r1; 323 ASC_SCSIQ_2 r2; 324 uchar *cdbptr; 325 ASC_SG_HEAD *sg_head; 326 uchar *sense_ptr; 327 ASC_SCSIQ_3 r3; 328 uchar cdb[ASC_MAX_CDB_LEN]; 329 uchar sense[ASC_MIN_SENSE_LEN]; 330 } ASC_SCSI_BIOS_REQ_Q; 331 332 typedef struct asc_risc_q { 333 uchar fwd; 334 uchar bwd; 335 ASC_SCSIQ_1 i1; 336 ASC_SCSIQ_2 i2; 337 ASC_SCSIQ_3 i3; 338 ASC_SCSIQ_4 i4; 339 } ASC_RISC_Q; 340 341 typedef struct asc_sg_list_q { 342 uchar seq_no; 343 uchar q_no; 344 uchar cntl; 345 uchar sg_head_qp; 346 uchar sg_list_cnt; 347 uchar sg_cur_list_cnt; 348 } ASC_SG_LIST_Q; 349 350 typedef struct asc_risc_sg_list_q { 351 uchar fwd; 352 uchar bwd; 353 ASC_SG_LIST_Q sg; 354 ASC_SG_LIST sg_list[7]; 355 } ASC_RISC_SG_LIST_Q; 356 357 #define ASCQ_ERR_Q_STATUS 0x0D 358 #define ASCQ_ERR_CUR_QNG 0x17 359 #define ASCQ_ERR_SG_Q_LINKS 0x18 360 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A 361 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B 362 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C 363 364 /* 365 * Warning code values are set in ASC_DVC_VAR 'warn_code'. 366 */ 367 #define ASC_WARN_NO_ERROR 0x0000 368 #define ASC_WARN_IO_PORT_ROTATE 0x0001 369 #define ASC_WARN_EEPROM_CHKSUM 0x0002 370 #define ASC_WARN_IRQ_MODIFIED 0x0004 371 #define ASC_WARN_AUTO_CONFIG 0x0008 372 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010 373 #define ASC_WARN_EEPROM_RECOVER 0x0020 374 #define ASC_WARN_CFG_MSW_RECOVER 0x0040 375 376 /* 377 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'. 378 */ 379 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */ 380 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ 381 #define ASC_IERR_SET_PC_ADDR 0x0004 382 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ 383 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */ 384 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */ 385 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */ 386 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ 387 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */ 388 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ 389 #define ASC_IERR_NO_BUS_TYPE 0x0400 390 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */ 391 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */ 392 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */ 393 394 #define ASC_DEF_MAX_TOTAL_QNG (0xF0) 395 #define ASC_MIN_TAG_Q_PER_DVC (0x04) 396 #define ASC_MIN_FREE_Q (0x02) 397 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q)) 398 #define ASC_MAX_TOTAL_QNG 240 399 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 400 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 401 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20 402 #define ASC_MAX_INRAM_TAG_QNG 16 403 #define ASC_IOADR_GAP 0x10 404 #define ASC_SYN_MAX_OFFSET 0x0F 405 #define ASC_DEF_SDTR_OFFSET 0x0F 406 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02 407 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41 408 409 /* The narrow chip only supports a limited selection of transfer rates. 410 * These are encoded in the range 0..7 or 0..15 depending whether the chip 411 * is Ultra-capable or not. These tables let us convert from one to the other. 412 */ 413 static const unsigned char asc_syn_xfer_period[8] = { 414 25, 30, 35, 40, 50, 60, 70, 85 415 }; 416 417 static const unsigned char asc_syn_ultra_xfer_period[16] = { 418 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107 419 }; 420 421 typedef struct ext_msg { 422 uchar msg_type; 423 uchar msg_len; 424 uchar msg_req; 425 union { 426 struct { 427 uchar sdtr_xfer_period; 428 uchar sdtr_req_ack_offset; 429 } sdtr; 430 struct { 431 uchar wdtr_width; 432 } wdtr; 433 struct { 434 uchar mdp_b3; 435 uchar mdp_b2; 436 uchar mdp_b1; 437 uchar mdp_b0; 438 } mdp; 439 } u_ext_msg; 440 uchar res; 441 } EXT_MSG; 442 443 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period 444 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset 445 #define wdtr_width u_ext_msg.wdtr.wdtr_width 446 #define mdp_b3 u_ext_msg.mdp_b3 447 #define mdp_b2 u_ext_msg.mdp_b2 448 #define mdp_b1 u_ext_msg.mdp_b1 449 #define mdp_b0 u_ext_msg.mdp_b0 450 451 typedef struct asc_dvc_cfg { 452 ASC_SCSI_BIT_ID_TYPE can_tagged_qng; 453 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled; 454 ASC_SCSI_BIT_ID_TYPE disc_enable; 455 ASC_SCSI_BIT_ID_TYPE sdtr_enable; 456 uchar chip_scsi_id; 457 uchar chip_version; 458 ushort mcode_date; 459 ushort mcode_version; 460 uchar max_tag_qng[ASC_MAX_TID + 1]; 461 uchar sdtr_period_offset[ASC_MAX_TID + 1]; 462 uchar adapter_info[6]; 463 } ASC_DVC_CFG; 464 465 #define ASC_DEF_DVC_CNTL 0xFFFF 466 #define ASC_DEF_CHIP_SCSI_ID 7 467 #define ASC_DEF_ISA_DMA_SPEED 4 468 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001 469 #define ASC_INIT_STATE_END_GET_CFG 0x0002 470 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004 471 #define ASC_INIT_STATE_END_SET_CFG 0x0008 472 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010 473 #define ASC_INIT_STATE_END_LOAD_MC 0x0020 474 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040 475 #define ASC_INIT_STATE_END_INQUIRY 0x0080 476 #define ASC_INIT_RESET_SCSI_DONE 0x0100 477 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000 478 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001 479 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002 480 #define ASC_MIN_TAGGED_CMD 7 481 #define ASC_MAX_SCSI_RESET_WAIT 30 482 #define ASC_OVERRUN_BSIZE 64 483 484 struct asc_dvc_var; /* Forward Declaration. */ 485 486 typedef struct asc_dvc_var { 487 PortAddr iop_base; 488 ushort err_code; 489 ushort dvc_cntl; 490 ushort bug_fix_cntl; 491 ushort bus_type; 492 ASC_SCSI_BIT_ID_TYPE init_sdtr; 493 ASC_SCSI_BIT_ID_TYPE sdtr_done; 494 ASC_SCSI_BIT_ID_TYPE use_tagged_qng; 495 ASC_SCSI_BIT_ID_TYPE unit_not_ready; 496 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy; 497 ASC_SCSI_BIT_ID_TYPE start_motor; 498 uchar *overrun_buf; 499 dma_addr_t overrun_dma; 500 uchar scsi_reset_wait; 501 uchar chip_no; 502 bool is_in_int; 503 uchar max_total_qng; 504 uchar cur_total_qng; 505 uchar in_critical_cnt; 506 uchar last_q_shortage; 507 ushort init_state; 508 uchar cur_dvc_qng[ASC_MAX_TID + 1]; 509 uchar max_dvc_qng[ASC_MAX_TID + 1]; 510 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1]; 511 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1]; 512 const uchar *sdtr_period_tbl; 513 ASC_DVC_CFG *cfg; 514 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always; 515 char redo_scam; 516 ushort res2; 517 uchar dos_int13_table[ASC_MAX_TID + 1]; 518 unsigned int max_dma_count; 519 ASC_SCSI_BIT_ID_TYPE no_scam; 520 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer; 521 uchar min_sdtr_index; 522 uchar max_sdtr_index; 523 struct asc_board *drv_ptr; 524 unsigned int uc_break; 525 } ASC_DVC_VAR; 526 527 typedef struct asc_dvc_inq_info { 528 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1]; 529 } ASC_DVC_INQ_INFO; 530 531 typedef struct asc_cap_info { 532 u32 lba; 533 u32 blk_size; 534 } ASC_CAP_INFO; 535 536 typedef struct asc_cap_info_array { 537 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1]; 538 } ASC_CAP_INFO_ARRAY; 539 540 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001 541 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002 542 #define ASC_CNTL_INITIATOR (ushort)0x0001 543 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002 544 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004 545 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008 546 #define ASC_CNTL_NO_SCAM (ushort)0x0010 547 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080 548 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040 549 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100 550 #define ASC_CNTL_RESET_SCSI (ushort)0x0200 551 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400 552 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800 553 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000 554 #define ASC_CNTL_BURST_MODE (ushort)0x2000 555 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000 556 #define ASC_EEP_DVC_CFG_BEG_VL 2 557 #define ASC_EEP_MAX_DVC_ADDR_VL 15 558 #define ASC_EEP_DVC_CFG_BEG 32 559 #define ASC_EEP_MAX_DVC_ADDR 45 560 #define ASC_EEP_MAX_RETRY 20 561 562 /* 563 * These macros keep the chip SCSI id bitfields in board order. C bitfields 564 * aren't portable between big and little-endian platforms so they are not used. 565 */ 566 567 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f) 568 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4) 569 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \ 570 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID)) 571 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \ 572 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4) 573 574 typedef struct asceep_config { 575 ushort cfg_lsw; 576 ushort cfg_msw; 577 uchar init_sdtr; 578 uchar disc_enable; 579 uchar use_cmd_qng; 580 uchar start_motor; 581 uchar max_total_qng; 582 uchar max_tag_qng; 583 uchar bios_scan; 584 uchar power_up_wait; 585 uchar no_scam; 586 uchar id_speed; /* low order 4 bits is chip scsi id */ 587 /* high order 4 bits is isa dma speed */ 588 uchar dos_int13_table[ASC_MAX_TID + 1]; 589 uchar adapter_info[6]; 590 ushort cntl; 591 ushort chksum; 592 } ASCEEP_CONFIG; 593 594 #define ASC_EEP_CMD_READ 0x80 595 #define ASC_EEP_CMD_WRITE 0x40 596 #define ASC_EEP_CMD_WRITE_ABLE 0x30 597 #define ASC_EEP_CMD_WRITE_DISABLE 0x00 598 #define ASCV_MSGOUT_BEG 0x0000 599 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3) 600 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4) 601 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006 602 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8) 603 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3) 604 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4) 605 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8) 606 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8) 607 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020 608 #define ASCV_BREAK_ADDR (ushort)0x0028 609 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A 610 #define ASCV_BREAK_CONTROL (ushort)0x002C 611 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E 612 613 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030 614 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032 615 #define ASCV_MCODE_SIZE_W (ushort)0x0034 616 #define ASCV_STOP_CODE_B (ushort)0x0036 617 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037 618 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038 619 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C 620 #define ASCV_HALTCODE_W (ushort)0x0040 621 #define ASCV_CHKSUM_W (ushort)0x0042 622 #define ASCV_MC_DATE_W (ushort)0x0044 623 #define ASCV_MC_VER_W (ushort)0x0046 624 #define ASCV_NEXTRDY_B (ushort)0x0048 625 #define ASCV_DONENEXT_B (ushort)0x0049 626 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A 627 #define ASCV_SCSIBUSY_B (ushort)0x004B 628 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C 629 #define ASCV_CURCDB_B (ushort)0x004D 630 #define ASCV_RCLUN_B (ushort)0x004E 631 #define ASCV_BUSY_QHEAD_B (ushort)0x004F 632 #define ASCV_DISC1_QHEAD_B (ushort)0x0050 633 #define ASCV_DISC_ENABLE_B (ushort)0x0052 634 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053 635 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055 636 #define ASCV_MCODE_CNTL_B (ushort)0x0056 637 #define ASCV_NULL_TARGET_B (ushort)0x0057 638 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058 639 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A 640 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1) 641 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1) 642 #define ASCV_HOST_FLAG_B (ushort)0x005D 643 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064 644 #define ASCV_VER_SERIAL_B (ushort)0x0065 645 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066 646 #define ASCV_WTM_FLAG_B (ushort)0x0068 647 #define ASCV_RISC_FLAG_B (ushort)0x006A 648 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B 649 #define ASC_HOST_FLAG_IN_ISR 0x01 650 #define ASC_HOST_FLAG_ACK_INT 0x02 651 #define ASC_RISC_FLAG_GEN_INT 0x01 652 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02 653 #define IOP_CTRL (0x0F) 654 #define IOP_STATUS (0x0E) 655 #define IOP_INT_ACK IOP_STATUS 656 #define IOP_REG_IFC (0x0D) 657 #define IOP_SYN_OFFSET (0x0B) 658 #define IOP_EXTRA_CONTROL (0x0D) 659 #define IOP_REG_PC (0x0C) 660 #define IOP_RAM_ADDR (0x0A) 661 #define IOP_RAM_DATA (0x08) 662 #define IOP_EEP_DATA (0x06) 663 #define IOP_EEP_CMD (0x07) 664 #define IOP_VERSION (0x03) 665 #define IOP_CONFIG_HIGH (0x04) 666 #define IOP_CONFIG_LOW (0x02) 667 #define IOP_SIG_BYTE (0x01) 668 #define IOP_SIG_WORD (0x00) 669 #define IOP_REG_DC1 (0x0E) 670 #define IOP_REG_DC0 (0x0C) 671 #define IOP_REG_SB (0x0B) 672 #define IOP_REG_DA1 (0x0A) 673 #define IOP_REG_DA0 (0x08) 674 #define IOP_REG_SC (0x09) 675 #define IOP_DMA_SPEED (0x07) 676 #define IOP_REG_FLAG (0x07) 677 #define IOP_FIFO_H (0x06) 678 #define IOP_FIFO_L (0x04) 679 #define IOP_REG_ID (0x05) 680 #define IOP_REG_QP (0x03) 681 #define IOP_REG_IH (0x02) 682 #define IOP_REG_IX (0x01) 683 #define IOP_REG_AX (0x00) 684 #define IFC_REG_LOCK (0x00) 685 #define IFC_REG_UNLOCK (0x09) 686 #define IFC_WR_EN_FILTER (0x10) 687 #define IFC_RD_NO_EEPROM (0x10) 688 #define IFC_SLEW_RATE (0x20) 689 #define IFC_ACT_NEG (0x40) 690 #define IFC_INP_FILTER (0x80) 691 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK) 692 #define SC_SEL (uchar)(0x80) 693 #define SC_BSY (uchar)(0x40) 694 #define SC_ACK (uchar)(0x20) 695 #define SC_REQ (uchar)(0x10) 696 #define SC_ATN (uchar)(0x08) 697 #define SC_IO (uchar)(0x04) 698 #define SC_CD (uchar)(0x02) 699 #define SC_MSG (uchar)(0x01) 700 #define SEC_SCSI_CTL (uchar)(0x80) 701 #define SEC_ACTIVE_NEGATE (uchar)(0x40) 702 #define SEC_SLEW_RATE (uchar)(0x20) 703 #define SEC_ENABLE_FILTER (uchar)(0x10) 704 #define ASC_HALT_EXTMSG_IN (ushort)0x8000 705 #define ASC_HALT_CHK_CONDITION (ushort)0x8100 706 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200 707 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300 708 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400 709 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000 710 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000 711 #define ASC_MAX_QNO 0xF8 712 #define ASC_DATA_SEC_BEG (ushort)0x0080 713 #define ASC_DATA_SEC_END (ushort)0x0080 714 #define ASC_CODE_SEC_BEG (ushort)0x0080 715 #define ASC_CODE_SEC_END (ushort)0x0080 716 #define ASC_QADR_BEG (0x4000) 717 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64) 718 #define ASC_QADR_END (ushort)0x7FFF 719 #define ASC_QLAST_ADR (ushort)0x7FC0 720 #define ASC_QBLK_SIZE 0x40 721 #define ASC_BIOS_DATA_QBEG 0xF8 722 #define ASC_MIN_ACTIVE_QNO 0x01 723 #define ASC_QLINK_END 0xFF 724 #define ASC_EEPROM_WORDS 0x10 725 #define ASC_MAX_MGS_LEN 0x10 726 #define ASC_BIOS_ADDR_DEF 0xDC00 727 #define ASC_BIOS_SIZE 0x3800 728 #define ASC_BIOS_RAM_OFF 0x3800 729 #define ASC_BIOS_RAM_SIZE 0x800 730 #define ASC_BIOS_MIN_ADDR 0xC000 731 #define ASC_BIOS_MAX_ADDR 0xEC00 732 #define ASC_BIOS_BANK_SIZE 0x0400 733 #define ASC_MCODE_START_ADDR 0x0080 734 #define ASC_CFG0_HOST_INT_ON 0x0020 735 #define ASC_CFG0_BIOS_ON 0x0040 736 #define ASC_CFG0_VERA_BURST_ON 0x0080 737 #define ASC_CFG0_SCSI_PARITY_ON 0x0800 738 #define ASC_CFG1_SCSI_TARGET_ON 0x0080 739 #define ASC_CFG1_LRAM_8BITS_ON 0x0800 740 #define ASC_CFG_MSW_CLR_MASK 0x3080 741 #define CSW_TEST1 (ASC_CS_TYPE)0x8000 742 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000 743 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000 744 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000 745 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800 746 #define CSW_TEST2 (ASC_CS_TYPE)0x0400 747 #define CSW_TEST3 (ASC_CS_TYPE)0x0200 748 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100 749 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080 750 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040 751 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020 752 #define CSW_HALTED (ASC_CS_TYPE)0x0010 753 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008 754 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004 755 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002 756 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001 757 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000 758 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100 759 #define CIW_TEST1 (ASC_CS_TYPE)0x0200 760 #define CIW_TEST2 (ASC_CS_TYPE)0x0400 761 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800 762 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000 763 #define CC_CHIP_RESET (uchar)0x80 764 #define CC_SCSI_RESET (uchar)0x40 765 #define CC_HALT (uchar)0x20 766 #define CC_SINGLE_STEP (uchar)0x10 767 #define CC_DMA_ABLE (uchar)0x08 768 #define CC_TEST (uchar)0x04 769 #define CC_BANK_ONE (uchar)0x02 770 #define CC_DIAG (uchar)0x01 771 #define ASC_1000_ID0W 0x04C1 772 #define ASC_1000_ID0W_FIX 0x00C1 773 #define ASC_1000_ID1B 0x25 774 #define ASC_EISA_REV_IOP_MASK (0x0C83) 775 #define ASC_EISA_CFG_IOP_MASK (0x0C86) 776 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000) 777 #define INS_HALTINT (ushort)0x6281 778 #define INS_HALT (ushort)0x6280 779 #define INS_SINT (ushort)0x6200 780 #define INS_RFLAG_WTM (ushort)0x7380 781 #define ASC_MC_SAVE_CODE_WSIZE 0x500 782 #define ASC_MC_SAVE_DATA_WSIZE 0x40 783 784 typedef struct asc_mc_saved { 785 ushort data[ASC_MC_SAVE_DATA_WSIZE]; 786 ushort code[ASC_MC_SAVE_CODE_WSIZE]; 787 } ASC_MC_SAVED; 788 789 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B) 790 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val) 791 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W) 792 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W) 793 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val) 794 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val) 795 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B) 796 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B) 797 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val) 798 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val) 799 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data)) 800 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id)) 801 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data) 802 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id)) 803 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE) 804 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD) 805 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION) 806 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW) 807 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH) 808 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data) 809 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data) 810 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD) 811 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data) 812 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA) 813 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data) 814 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR)) 815 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr) 816 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA) 817 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data) 818 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC) 819 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data) 820 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS) 821 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val) 822 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL) 823 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val) 824 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET) 825 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data) 826 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data) 827 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC) 828 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH)) 829 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID) 830 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL) 831 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data) 832 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX) 833 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data) 834 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX) 835 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data) 836 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH) 837 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data) 838 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP) 839 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data) 840 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L) 841 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data) 842 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H) 843 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data) 844 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED) 845 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data) 846 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0) 847 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data) 848 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1) 849 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data) 850 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0) 851 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data) 852 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1) 853 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data) 854 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID) 855 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data) 856 857 #define AdvPortAddr void __iomem * /* Virtual memory address size */ 858 859 /* 860 * Define Adv Library required memory access macros. 861 */ 862 #define ADV_MEM_READB(addr) readb(addr) 863 #define ADV_MEM_READW(addr) readw(addr) 864 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr) 865 #define ADV_MEM_WRITEW(addr, word) writew(word, addr) 866 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr) 867 868 /* 869 * Define total number of simultaneous maximum element scatter-gather 870 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the 871 * maximum number of outstanding commands per wide host adapter. Each 872 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather 873 * elements. Allow each command to have at least one ADV_SG_BLOCK structure. 874 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK 875 * structures or 255 scatter-gather elements. 876 */ 877 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG 878 879 /* 880 * Define maximum number of scatter-gather elements per request. 881 */ 882 #define ADV_MAX_SG_LIST 255 883 #define NO_OF_SG_PER_BLOCK 15 884 885 #define ADV_EEP_DVC_CFG_BEGIN (0x00) 886 #define ADV_EEP_DVC_CFG_END (0x15) 887 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */ 888 #define ADV_EEP_MAX_WORD_ADDR (0x1E) 889 890 #define ADV_EEP_DELAY_MS 100 891 892 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 893 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 894 /* 895 * For the ASC3550 Bit 13 is Termination Polarity control bit. 896 * For later ICs Bit 13 controls whether the CIS (Card Information 897 * Service Section) is loaded from EEPROM. 898 */ 899 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 900 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */ 901 /* 902 * ASC38C1600 Bit 11 903 * 904 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify 905 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then 906 * Function 0 will specify INT B. 907 * 908 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify 909 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then 910 * Function 1 will specify INT A. 911 */ 912 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */ 913 914 typedef struct adveep_3550_config { 915 /* Word Offset, Description */ 916 917 ushort cfg_lsw; /* 00 power up initialization */ 918 /* bit 13 set - Term Polarity Control */ 919 /* bit 14 set - BIOS Enable */ 920 /* bit 15 set - Big Endian Mode */ 921 ushort cfg_msw; /* 01 unused */ 922 ushort disc_enable; /* 02 disconnect enable */ 923 ushort wdtr_able; /* 03 Wide DTR able */ 924 ushort sdtr_able; /* 04 Synchronous DTR able */ 925 ushort start_motor; /* 05 send start up motor */ 926 ushort tagqng_able; /* 06 tag queuing able */ 927 ushort bios_scan; /* 07 BIOS device control */ 928 ushort scam_tolerant; /* 08 no scam */ 929 930 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 931 uchar bios_boot_delay; /* power up wait */ 932 933 uchar scsi_reset_delay; /* 10 reset delay */ 934 uchar bios_id_lun; /* first boot device scsi id & lun */ 935 /* high nibble is lun */ 936 /* low nibble is scsi id */ 937 938 uchar termination; /* 11 0 - automatic */ 939 /* 1 - low off / high off */ 940 /* 2 - low off / high on */ 941 /* 3 - low on / high on */ 942 /* There is no low on / high off */ 943 944 uchar reserved1; /* reserved byte (not used) */ 945 946 ushort bios_ctrl; /* 12 BIOS control bits */ 947 /* bit 0 BIOS don't act as initiator. */ 948 /* bit 1 BIOS > 1 GB support */ 949 /* bit 2 BIOS > 2 Disk Support */ 950 /* bit 3 BIOS don't support removables */ 951 /* bit 4 BIOS support bootable CD */ 952 /* bit 5 BIOS scan enabled */ 953 /* bit 6 BIOS support multiple LUNs */ 954 /* bit 7 BIOS display of message */ 955 /* bit 8 SCAM disabled */ 956 /* bit 9 Reset SCSI bus during init. */ 957 /* bit 10 */ 958 /* bit 11 No verbose initialization. */ 959 /* bit 12 SCSI parity enabled */ 960 /* bit 13 */ 961 /* bit 14 */ 962 /* bit 15 */ 963 ushort ultra_able; /* 13 ULTRA speed able */ 964 ushort reserved2; /* 14 reserved */ 965 uchar max_host_qng; /* 15 maximum host queuing */ 966 uchar max_dvc_qng; /* maximum per device queuing */ 967 ushort dvc_cntl; /* 16 control bit for driver */ 968 ushort bug_fix; /* 17 control bit for bug fix */ 969 ushort serial_number_word1; /* 18 Board serial number word 1 */ 970 ushort serial_number_word2; /* 19 Board serial number word 2 */ 971 ushort serial_number_word3; /* 20 Board serial number word 3 */ 972 ushort check_sum; /* 21 EEP check sum */ 973 uchar oem_name[16]; /* 22 OEM name */ 974 ushort dvc_err_code; /* 30 last device driver error code */ 975 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 976 ushort adv_err_addr; /* 32 last uc error address */ 977 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 978 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 979 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 980 ushort num_of_err; /* 36 number of error */ 981 } ADVEEP_3550_CONFIG; 982 983 typedef struct adveep_38C0800_config { 984 /* Word Offset, Description */ 985 986 ushort cfg_lsw; /* 00 power up initialization */ 987 /* bit 13 set - Load CIS */ 988 /* bit 14 set - BIOS Enable */ 989 /* bit 15 set - Big Endian Mode */ 990 ushort cfg_msw; /* 01 unused */ 991 ushort disc_enable; /* 02 disconnect enable */ 992 ushort wdtr_able; /* 03 Wide DTR able */ 993 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 994 ushort start_motor; /* 05 send start up motor */ 995 ushort tagqng_able; /* 06 tag queuing able */ 996 ushort bios_scan; /* 07 BIOS device control */ 997 ushort scam_tolerant; /* 08 no scam */ 998 999 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 1000 uchar bios_boot_delay; /* power up wait */ 1001 1002 uchar scsi_reset_delay; /* 10 reset delay */ 1003 uchar bios_id_lun; /* first boot device scsi id & lun */ 1004 /* high nibble is lun */ 1005 /* low nibble is scsi id */ 1006 1007 uchar termination_se; /* 11 0 - automatic */ 1008 /* 1 - low off / high off */ 1009 /* 2 - low off / high on */ 1010 /* 3 - low on / high on */ 1011 /* There is no low on / high off */ 1012 1013 uchar termination_lvd; /* 11 0 - automatic */ 1014 /* 1 - low off / high off */ 1015 /* 2 - low off / high on */ 1016 /* 3 - low on / high on */ 1017 /* There is no low on / high off */ 1018 1019 ushort bios_ctrl; /* 12 BIOS control bits */ 1020 /* bit 0 BIOS don't act as initiator. */ 1021 /* bit 1 BIOS > 1 GB support */ 1022 /* bit 2 BIOS > 2 Disk Support */ 1023 /* bit 3 BIOS don't support removables */ 1024 /* bit 4 BIOS support bootable CD */ 1025 /* bit 5 BIOS scan enabled */ 1026 /* bit 6 BIOS support multiple LUNs */ 1027 /* bit 7 BIOS display of message */ 1028 /* bit 8 SCAM disabled */ 1029 /* bit 9 Reset SCSI bus during init. */ 1030 /* bit 10 */ 1031 /* bit 11 No verbose initialization. */ 1032 /* bit 12 SCSI parity enabled */ 1033 /* bit 13 */ 1034 /* bit 14 */ 1035 /* bit 15 */ 1036 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 1037 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 1038 uchar max_host_qng; /* 15 maximum host queueing */ 1039 uchar max_dvc_qng; /* maximum per device queuing */ 1040 ushort dvc_cntl; /* 16 control bit for driver */ 1041 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 1042 ushort serial_number_word1; /* 18 Board serial number word 1 */ 1043 ushort serial_number_word2; /* 19 Board serial number word 2 */ 1044 ushort serial_number_word3; /* 20 Board serial number word 3 */ 1045 ushort check_sum; /* 21 EEP check sum */ 1046 uchar oem_name[16]; /* 22 OEM name */ 1047 ushort dvc_err_code; /* 30 last device driver error code */ 1048 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 1049 ushort adv_err_addr; /* 32 last uc error address */ 1050 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 1051 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 1052 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 1053 ushort reserved36; /* 36 reserved */ 1054 ushort reserved37; /* 37 reserved */ 1055 ushort reserved38; /* 38 reserved */ 1056 ushort reserved39; /* 39 reserved */ 1057 ushort reserved40; /* 40 reserved */ 1058 ushort reserved41; /* 41 reserved */ 1059 ushort reserved42; /* 42 reserved */ 1060 ushort reserved43; /* 43 reserved */ 1061 ushort reserved44; /* 44 reserved */ 1062 ushort reserved45; /* 45 reserved */ 1063 ushort reserved46; /* 46 reserved */ 1064 ushort reserved47; /* 47 reserved */ 1065 ushort reserved48; /* 48 reserved */ 1066 ushort reserved49; /* 49 reserved */ 1067 ushort reserved50; /* 50 reserved */ 1068 ushort reserved51; /* 51 reserved */ 1069 ushort reserved52; /* 52 reserved */ 1070 ushort reserved53; /* 53 reserved */ 1071 ushort reserved54; /* 54 reserved */ 1072 ushort reserved55; /* 55 reserved */ 1073 ushort cisptr_lsw; /* 56 CIS PTR LSW */ 1074 ushort cisprt_msw; /* 57 CIS PTR MSW */ 1075 ushort subsysvid; /* 58 SubSystem Vendor ID */ 1076 ushort subsysid; /* 59 SubSystem ID */ 1077 ushort reserved60; /* 60 reserved */ 1078 ushort reserved61; /* 61 reserved */ 1079 ushort reserved62; /* 62 reserved */ 1080 ushort reserved63; /* 63 reserved */ 1081 } ADVEEP_38C0800_CONFIG; 1082 1083 typedef struct adveep_38C1600_config { 1084 /* Word Offset, Description */ 1085 1086 ushort cfg_lsw; /* 00 power up initialization */ 1087 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */ 1088 /* clear - Func. 0 INTA, Func. 1 INTB */ 1089 /* bit 13 set - Load CIS */ 1090 /* bit 14 set - BIOS Enable */ 1091 /* bit 15 set - Big Endian Mode */ 1092 ushort cfg_msw; /* 01 unused */ 1093 ushort disc_enable; /* 02 disconnect enable */ 1094 ushort wdtr_able; /* 03 Wide DTR able */ 1095 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 1096 ushort start_motor; /* 05 send start up motor */ 1097 ushort tagqng_able; /* 06 tag queuing able */ 1098 ushort bios_scan; /* 07 BIOS device control */ 1099 ushort scam_tolerant; /* 08 no scam */ 1100 1101 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 1102 uchar bios_boot_delay; /* power up wait */ 1103 1104 uchar scsi_reset_delay; /* 10 reset delay */ 1105 uchar bios_id_lun; /* first boot device scsi id & lun */ 1106 /* high nibble is lun */ 1107 /* low nibble is scsi id */ 1108 1109 uchar termination_se; /* 11 0 - automatic */ 1110 /* 1 - low off / high off */ 1111 /* 2 - low off / high on */ 1112 /* 3 - low on / high on */ 1113 /* There is no low on / high off */ 1114 1115 uchar termination_lvd; /* 11 0 - automatic */ 1116 /* 1 - low off / high off */ 1117 /* 2 - low off / high on */ 1118 /* 3 - low on / high on */ 1119 /* There is no low on / high off */ 1120 1121 ushort bios_ctrl; /* 12 BIOS control bits */ 1122 /* bit 0 BIOS don't act as initiator. */ 1123 /* bit 1 BIOS > 1 GB support */ 1124 /* bit 2 BIOS > 2 Disk Support */ 1125 /* bit 3 BIOS don't support removables */ 1126 /* bit 4 BIOS support bootable CD */ 1127 /* bit 5 BIOS scan enabled */ 1128 /* bit 6 BIOS support multiple LUNs */ 1129 /* bit 7 BIOS display of message */ 1130 /* bit 8 SCAM disabled */ 1131 /* bit 9 Reset SCSI bus during init. */ 1132 /* bit 10 Basic Integrity Checking disabled */ 1133 /* bit 11 No verbose initialization. */ 1134 /* bit 12 SCSI parity enabled */ 1135 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */ 1136 /* bit 14 */ 1137 /* bit 15 */ 1138 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 1139 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 1140 uchar max_host_qng; /* 15 maximum host queueing */ 1141 uchar max_dvc_qng; /* maximum per device queuing */ 1142 ushort dvc_cntl; /* 16 control bit for driver */ 1143 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 1144 ushort serial_number_word1; /* 18 Board serial number word 1 */ 1145 ushort serial_number_word2; /* 19 Board serial number word 2 */ 1146 ushort serial_number_word3; /* 20 Board serial number word 3 */ 1147 ushort check_sum; /* 21 EEP check sum */ 1148 uchar oem_name[16]; /* 22 OEM name */ 1149 ushort dvc_err_code; /* 30 last device driver error code */ 1150 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 1151 ushort adv_err_addr; /* 32 last uc error address */ 1152 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 1153 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 1154 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 1155 ushort reserved36; /* 36 reserved */ 1156 ushort reserved37; /* 37 reserved */ 1157 ushort reserved38; /* 38 reserved */ 1158 ushort reserved39; /* 39 reserved */ 1159 ushort reserved40; /* 40 reserved */ 1160 ushort reserved41; /* 41 reserved */ 1161 ushort reserved42; /* 42 reserved */ 1162 ushort reserved43; /* 43 reserved */ 1163 ushort reserved44; /* 44 reserved */ 1164 ushort reserved45; /* 45 reserved */ 1165 ushort reserved46; /* 46 reserved */ 1166 ushort reserved47; /* 47 reserved */ 1167 ushort reserved48; /* 48 reserved */ 1168 ushort reserved49; /* 49 reserved */ 1169 ushort reserved50; /* 50 reserved */ 1170 ushort reserved51; /* 51 reserved */ 1171 ushort reserved52; /* 52 reserved */ 1172 ushort reserved53; /* 53 reserved */ 1173 ushort reserved54; /* 54 reserved */ 1174 ushort reserved55; /* 55 reserved */ 1175 ushort cisptr_lsw; /* 56 CIS PTR LSW */ 1176 ushort cisprt_msw; /* 57 CIS PTR MSW */ 1177 ushort subsysvid; /* 58 SubSystem Vendor ID */ 1178 ushort subsysid; /* 59 SubSystem ID */ 1179 ushort reserved60; /* 60 reserved */ 1180 ushort reserved61; /* 61 reserved */ 1181 ushort reserved62; /* 62 reserved */ 1182 ushort reserved63; /* 63 reserved */ 1183 } ADVEEP_38C1600_CONFIG; 1184 1185 /* 1186 * EEPROM Commands 1187 */ 1188 #define ASC_EEP_CMD_DONE 0x0200 1189 1190 /* bios_ctrl */ 1191 #define BIOS_CTRL_BIOS 0x0001 1192 #define BIOS_CTRL_EXTENDED_XLAT 0x0002 1193 #define BIOS_CTRL_GT_2_DISK 0x0004 1194 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008 1195 #define BIOS_CTRL_BOOTABLE_CD 0x0010 1196 #define BIOS_CTRL_MULTIPLE_LUN 0x0040 1197 #define BIOS_CTRL_DISPLAY_MSG 0x0080 1198 #define BIOS_CTRL_NO_SCAM 0x0100 1199 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200 1200 #define BIOS_CTRL_INIT_VERBOSE 0x0800 1201 #define BIOS_CTRL_SCSI_PARITY 0x1000 1202 #define BIOS_CTRL_AIPP_DIS 0x2000 1203 1204 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ 1205 1206 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 1207 1208 /* 1209 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is 1210 * a special 16K Adv Library and Microcode version. After the issue is 1211 * resolved, should restore 32K support. 1212 * 1213 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory * 1214 */ 1215 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 1216 1217 /* 1218 * Byte I/O register address from base of 'iop_base'. 1219 */ 1220 #define IOPB_INTR_STATUS_REG 0x00 1221 #define IOPB_CHIP_ID_1 0x01 1222 #define IOPB_INTR_ENABLES 0x02 1223 #define IOPB_CHIP_TYPE_REV 0x03 1224 #define IOPB_RES_ADDR_4 0x04 1225 #define IOPB_RES_ADDR_5 0x05 1226 #define IOPB_RAM_DATA 0x06 1227 #define IOPB_RES_ADDR_7 0x07 1228 #define IOPB_FLAG_REG 0x08 1229 #define IOPB_RES_ADDR_9 0x09 1230 #define IOPB_RISC_CSR 0x0A 1231 #define IOPB_RES_ADDR_B 0x0B 1232 #define IOPB_RES_ADDR_C 0x0C 1233 #define IOPB_RES_ADDR_D 0x0D 1234 #define IOPB_SOFT_OVER_WR 0x0E 1235 #define IOPB_RES_ADDR_F 0x0F 1236 #define IOPB_MEM_CFG 0x10 1237 #define IOPB_RES_ADDR_11 0x11 1238 #define IOPB_GPIO_DATA 0x12 1239 #define IOPB_RES_ADDR_13 0x13 1240 #define IOPB_FLASH_PAGE 0x14 1241 #define IOPB_RES_ADDR_15 0x15 1242 #define IOPB_GPIO_CNTL 0x16 1243 #define IOPB_RES_ADDR_17 0x17 1244 #define IOPB_FLASH_DATA 0x18 1245 #define IOPB_RES_ADDR_19 0x19 1246 #define IOPB_RES_ADDR_1A 0x1A 1247 #define IOPB_RES_ADDR_1B 0x1B 1248 #define IOPB_RES_ADDR_1C 0x1C 1249 #define IOPB_RES_ADDR_1D 0x1D 1250 #define IOPB_RES_ADDR_1E 0x1E 1251 #define IOPB_RES_ADDR_1F 0x1F 1252 #define IOPB_DMA_CFG0 0x20 1253 #define IOPB_DMA_CFG1 0x21 1254 #define IOPB_TICKLE 0x22 1255 #define IOPB_DMA_REG_WR 0x23 1256 #define IOPB_SDMA_STATUS 0x24 1257 #define IOPB_SCSI_BYTE_CNT 0x25 1258 #define IOPB_HOST_BYTE_CNT 0x26 1259 #define IOPB_BYTE_LEFT_TO_XFER 0x27 1260 #define IOPB_BYTE_TO_XFER_0 0x28 1261 #define IOPB_BYTE_TO_XFER_1 0x29 1262 #define IOPB_BYTE_TO_XFER_2 0x2A 1263 #define IOPB_BYTE_TO_XFER_3 0x2B 1264 #define IOPB_ACC_GRP 0x2C 1265 #define IOPB_RES_ADDR_2D 0x2D 1266 #define IOPB_DEV_ID 0x2E 1267 #define IOPB_RES_ADDR_2F 0x2F 1268 #define IOPB_SCSI_DATA 0x30 1269 #define IOPB_RES_ADDR_31 0x31 1270 #define IOPB_RES_ADDR_32 0x32 1271 #define IOPB_SCSI_DATA_HSHK 0x33 1272 #define IOPB_SCSI_CTRL 0x34 1273 #define IOPB_RES_ADDR_35 0x35 1274 #define IOPB_RES_ADDR_36 0x36 1275 #define IOPB_RES_ADDR_37 0x37 1276 #define IOPB_RAM_BIST 0x38 1277 #define IOPB_PLL_TEST 0x39 1278 #define IOPB_PCI_INT_CFG 0x3A 1279 #define IOPB_RES_ADDR_3B 0x3B 1280 #define IOPB_RFIFO_CNT 0x3C 1281 #define IOPB_RES_ADDR_3D 0x3D 1282 #define IOPB_RES_ADDR_3E 0x3E 1283 #define IOPB_RES_ADDR_3F 0x3F 1284 1285 /* 1286 * Word I/O register address from base of 'iop_base'. 1287 */ 1288 #define IOPW_CHIP_ID_0 0x00 /* CID0 */ 1289 #define IOPW_CTRL_REG 0x02 /* CC */ 1290 #define IOPW_RAM_ADDR 0x04 /* LA */ 1291 #define IOPW_RAM_DATA 0x06 /* LD */ 1292 #define IOPW_RES_ADDR_08 0x08 1293 #define IOPW_RISC_CSR 0x0A /* CSR */ 1294 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */ 1295 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */ 1296 #define IOPW_RES_ADDR_10 0x10 1297 #define IOPW_SEL_MASK 0x12 /* SM */ 1298 #define IOPW_RES_ADDR_14 0x14 1299 #define IOPW_FLASH_ADDR 0x16 /* FA */ 1300 #define IOPW_RES_ADDR_18 0x18 1301 #define IOPW_EE_CMD 0x1A /* EC */ 1302 #define IOPW_EE_DATA 0x1C /* ED */ 1303 #define IOPW_SFIFO_CNT 0x1E /* SFC */ 1304 #define IOPW_RES_ADDR_20 0x20 1305 #define IOPW_Q_BASE 0x22 /* QB */ 1306 #define IOPW_QP 0x24 /* QP */ 1307 #define IOPW_IX 0x26 /* IX */ 1308 #define IOPW_SP 0x28 /* SP */ 1309 #define IOPW_PC 0x2A /* PC */ 1310 #define IOPW_RES_ADDR_2C 0x2C 1311 #define IOPW_RES_ADDR_2E 0x2E 1312 #define IOPW_SCSI_DATA 0x30 /* SD */ 1313 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */ 1314 #define IOPW_SCSI_CTRL 0x34 /* SC */ 1315 #define IOPW_HSHK_CFG 0x36 /* HCFG */ 1316 #define IOPW_SXFR_STATUS 0x36 /* SXS */ 1317 #define IOPW_SXFR_CNTL 0x38 /* SXL */ 1318 #define IOPW_SXFR_CNTH 0x3A /* SXH */ 1319 #define IOPW_RES_ADDR_3C 0x3C 1320 #define IOPW_RFIFO_DATA 0x3E /* RFD */ 1321 1322 /* 1323 * Doubleword I/O register address from base of 'iop_base'. 1324 */ 1325 #define IOPDW_RES_ADDR_0 0x00 1326 #define IOPDW_RAM_DATA 0x04 1327 #define IOPDW_RES_ADDR_8 0x08 1328 #define IOPDW_RES_ADDR_C 0x0C 1329 #define IOPDW_RES_ADDR_10 0x10 1330 #define IOPDW_COMMA 0x14 1331 #define IOPDW_COMMB 0x18 1332 #define IOPDW_RES_ADDR_1C 0x1C 1333 #define IOPDW_SDMA_ADDR0 0x20 1334 #define IOPDW_SDMA_ADDR1 0x24 1335 #define IOPDW_SDMA_COUNT 0x28 1336 #define IOPDW_SDMA_ERROR 0x2C 1337 #define IOPDW_RDMA_ADDR0 0x30 1338 #define IOPDW_RDMA_ADDR1 0x34 1339 #define IOPDW_RDMA_COUNT 0x38 1340 #define IOPDW_RDMA_ERROR 0x3C 1341 1342 #define ADV_CHIP_ID_BYTE 0x25 1343 #define ADV_CHIP_ID_WORD 0x04C1 1344 1345 #define ADV_INTR_ENABLE_HOST_INTR 0x01 1346 #define ADV_INTR_ENABLE_SEL_INTR 0x02 1347 #define ADV_INTR_ENABLE_DPR_INTR 0x04 1348 #define ADV_INTR_ENABLE_RTA_INTR 0x08 1349 #define ADV_INTR_ENABLE_RMA_INTR 0x10 1350 #define ADV_INTR_ENABLE_RST_INTR 0x20 1351 #define ADV_INTR_ENABLE_DPE_INTR 0x40 1352 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80 1353 1354 #define ADV_INTR_STATUS_INTRA 0x01 1355 #define ADV_INTR_STATUS_INTRB 0x02 1356 #define ADV_INTR_STATUS_INTRC 0x04 1357 1358 #define ADV_RISC_CSR_STOP (0x0000) 1359 #define ADV_RISC_TEST_COND (0x2000) 1360 #define ADV_RISC_CSR_RUN (0x4000) 1361 #define ADV_RISC_CSR_SINGLE_STEP (0x8000) 1362 1363 #define ADV_CTRL_REG_HOST_INTR 0x0100 1364 #define ADV_CTRL_REG_SEL_INTR 0x0200 1365 #define ADV_CTRL_REG_DPR_INTR 0x0400 1366 #define ADV_CTRL_REG_RTA_INTR 0x0800 1367 #define ADV_CTRL_REG_RMA_INTR 0x1000 1368 #define ADV_CTRL_REG_RES_BIT14 0x2000 1369 #define ADV_CTRL_REG_DPE_INTR 0x4000 1370 #define ADV_CTRL_REG_POWER_DONE 0x8000 1371 #define ADV_CTRL_REG_ANY_INTR 0xFF00 1372 1373 #define ADV_CTRL_REG_CMD_RESET 0x00C6 1374 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5 1375 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4 1376 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3 1377 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2 1378 1379 #define ADV_TICKLE_NOP 0x00 1380 #define ADV_TICKLE_A 0x01 1381 #define ADV_TICKLE_B 0x02 1382 #define ADV_TICKLE_C 0x03 1383 1384 #define AdvIsIntPending(port) \ 1385 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR) 1386 1387 /* 1388 * SCSI_CFG0 Register bit definitions 1389 */ 1390 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */ 1391 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */ 1392 #define EVEN_PARITY 0x1000 /* Select Even Parity */ 1393 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */ 1394 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */ 1395 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */ 1396 #define SCAM_EN 0x0080 /* Enable SCAM selection */ 1397 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */ 1398 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */ 1399 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */ 1400 #define OUR_ID 0x000F /* SCSI ID */ 1401 1402 /* 1403 * SCSI_CFG1 Register bit definitions 1404 */ 1405 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */ 1406 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */ 1407 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */ 1408 #define FILTER_SEL 0x0C00 /* Filter Period Selection */ 1409 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */ 1410 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */ 1411 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */ 1412 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */ 1413 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */ 1414 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */ 1415 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */ 1416 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */ 1417 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */ 1418 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */ 1419 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */ 1420 1421 /* 1422 * Addendum for ASC-38C0800 Chip 1423 * 1424 * The ASC-38C1600 Chip uses the same definitions except that the 1425 * bus mode override bits [12:10] have been moved to byte register 1426 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in 1427 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV) 1428 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only. 1429 * Also each ASC-38C1600 function or channel uses only cable bits [5:4] 1430 * and [1:0]. Bits [14], [7:6], [3:2] are unused. 1431 */ 1432 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */ 1433 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */ 1434 #define HVD 0x1000 /* HVD Device Detect */ 1435 #define LVD 0x0800 /* LVD Device Detect */ 1436 #define SE 0x0400 /* SE Device Detect */ 1437 #define TERM_LVD 0x00C0 /* LVD Termination Bits */ 1438 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */ 1439 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */ 1440 #define TERM_SE 0x0030 /* SE Termination Bits */ 1441 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */ 1442 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */ 1443 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */ 1444 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */ 1445 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */ 1446 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */ 1447 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */ 1448 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */ 1449 1450 #define CABLE_ILLEGAL_A 0x7 1451 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ 1452 1453 #define CABLE_ILLEGAL_B 0xB 1454 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ 1455 1456 /* 1457 * MEM_CFG Register bit definitions 1458 */ 1459 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */ 1460 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */ 1461 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */ 1462 #define RAM_SZ_2KB 0x00 /* 2 KB */ 1463 #define RAM_SZ_4KB 0x04 /* 4 KB */ 1464 #define RAM_SZ_8KB 0x08 /* 8 KB */ 1465 #define RAM_SZ_16KB 0x0C /* 16 KB */ 1466 #define RAM_SZ_32KB 0x10 /* 32 KB */ 1467 #define RAM_SZ_64KB 0x14 /* 64 KB */ 1468 1469 /* 1470 * DMA_CFG0 Register bit definitions 1471 * 1472 * This register is only accessible to the host. 1473 */ 1474 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */ 1475 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */ 1476 #define FIFO_THRESH_16B 0x00 /* 16 bytes */ 1477 #define FIFO_THRESH_32B 0x20 /* 32 bytes */ 1478 #define FIFO_THRESH_48B 0x30 /* 48 bytes */ 1479 #define FIFO_THRESH_64B 0x40 /* 64 bytes */ 1480 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */ 1481 #define FIFO_THRESH_96B 0x60 /* 96 bytes */ 1482 #define FIFO_THRESH_112B 0x70 /* 112 bytes */ 1483 #define START_CTL 0x0C /* DMA start conditions */ 1484 #define START_CTL_TH 0x00 /* Wait threshold level (default) */ 1485 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */ 1486 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */ 1487 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */ 1488 #define READ_CMD 0x03 /* Memory Read Method */ 1489 #define READ_CMD_MR 0x00 /* Memory Read */ 1490 #define READ_CMD_MRL 0x02 /* Memory Read Long */ 1491 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */ 1492 1493 /* 1494 * ASC-38C0800 RAM BIST Register bit definitions 1495 */ 1496 #define RAM_TEST_MODE 0x80 1497 #define PRE_TEST_MODE 0x40 1498 #define NORMAL_MODE 0x00 1499 #define RAM_TEST_DONE 0x10 1500 #define RAM_TEST_STATUS 0x0F 1501 #define RAM_TEST_HOST_ERROR 0x08 1502 #define RAM_TEST_INTRAM_ERROR 0x04 1503 #define RAM_TEST_RISC_ERROR 0x02 1504 #define RAM_TEST_SCSI_ERROR 0x01 1505 #define RAM_TEST_SUCCESS 0x00 1506 #define PRE_TEST_VALUE 0x05 1507 #define NORMAL_VALUE 0x00 1508 1509 /* 1510 * ASC38C1600 Definitions 1511 * 1512 * IOPB_PCI_INT_CFG Bit Field Definitions 1513 */ 1514 1515 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */ 1516 1517 /* 1518 * Bit 1 can be set to change the interrupt for the Function to operate in 1519 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in 1520 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same 1521 * mode, otherwise the operating mode is undefined. 1522 */ 1523 #define TOTEMPOLE 0x02 1524 1525 /* 1526 * Bit 0 can be used to change the Int Pin for the Function. The value is 1527 * 0 by default for both Functions with Function 0 using INT A and Function 1528 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set, 1529 * INT A is used. 1530 * 1531 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin 1532 * value specified in the PCI Configuration Space. 1533 */ 1534 #define INTAB 0x01 1535 1536 /* 1537 * Adv Library Status Definitions 1538 */ 1539 #define ADV_TRUE 1 1540 #define ADV_FALSE 0 1541 #define ADV_SUCCESS 1 1542 #define ADV_BUSY 0 1543 #define ADV_ERROR (-1) 1544 1545 /* 1546 * ADV_DVC_VAR 'warn_code' values 1547 */ 1548 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ 1549 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ 1550 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ 1551 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */ 1552 1553 #define ADV_MAX_TID 15 /* max. target identifier */ 1554 #define ADV_MAX_LUN 7 /* max. logical unit number */ 1555 1556 /* 1557 * Fixed locations of microcode operating variables. 1558 */ 1559 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 1560 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */ 1561 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 1562 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */ 1563 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */ 1564 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 1565 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 1566 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ 1567 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */ 1568 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ 1569 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ 1570 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ 1571 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ 1572 #define ASC_MC_CHIP_TYPE 0x009A 1573 #define ASC_MC_INTRB_CODE 0x009B 1574 #define ASC_MC_WDTR_ABLE 0x009C 1575 #define ASC_MC_SDTR_ABLE 0x009E 1576 #define ASC_MC_TAGQNG_ABLE 0x00A0 1577 #define ASC_MC_DISC_ENABLE 0x00A2 1578 #define ASC_MC_IDLE_CMD_STATUS 0x00A4 1579 #define ASC_MC_IDLE_CMD 0x00A6 1580 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8 1581 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC 1582 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE 1583 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0 1584 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2 1585 #define ASC_MC_SDTR_DONE 0x00B6 1586 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0 1587 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0 1588 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100 1589 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 1590 #define ASC_MC_WDTR_DONE 0x0124 1591 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ 1592 #define ASC_MC_ICQ 0x0160 1593 #define ASC_MC_IRQ 0x0164 1594 #define ASC_MC_PPR_ABLE 0x017A 1595 1596 /* 1597 * BIOS LRAM variable absolute offsets. 1598 */ 1599 #define BIOS_CODESEG 0x54 1600 #define BIOS_CODELEN 0x56 1601 #define BIOS_SIGNATURE 0x58 1602 #define BIOS_VERSION 0x5A 1603 1604 /* 1605 * Microcode Control Flags 1606 * 1607 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122) 1608 * and handled by the microcode. 1609 */ 1610 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */ 1611 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */ 1612 1613 /* 1614 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format 1615 */ 1616 #define HSHK_CFG_WIDE_XFR 0x8000 1617 #define HSHK_CFG_RATE 0x0F00 1618 #define HSHK_CFG_OFFSET 0x001F 1619 1620 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */ 1621 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */ 1622 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */ 1623 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */ 1624 1625 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */ 1626 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ 1627 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ 1628 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ 1629 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */ 1630 1631 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ 1632 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ 1633 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */ 1634 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ 1635 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */ 1636 /* 1637 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or 1638 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. 1639 */ 1640 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ 1641 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ 1642 1643 /* 1644 * All fields here are accessed by the board microcode and need to be 1645 * little-endian. 1646 */ 1647 typedef struct adv_carr_t { 1648 __le32 carr_va; /* Carrier Virtual Address */ 1649 __le32 carr_pa; /* Carrier Physical Address */ 1650 __le32 areq_vpa; /* ADV_SCSI_REQ_Q Virtual or Physical Address */ 1651 /* 1652 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer 1653 * 1654 * next_vpa [3:1] Reserved Bits 1655 * next_vpa [0] Done Flag set in Response Queue. 1656 */ 1657 __le32 next_vpa; 1658 } ADV_CARR_T; 1659 1660 /* 1661 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field. 1662 */ 1663 #define ADV_NEXT_VPA_MASK 0xFFFFFFF0 1664 1665 #define ADV_RQ_DONE 0x00000001 1666 #define ADV_RQ_GOOD 0x00000002 1667 #define ADV_CQ_STOPPER 0x00000000 1668 1669 #define ADV_GET_CARRP(carrp) ((carrp) & ADV_NEXT_VPA_MASK) 1670 1671 /* 1672 * Each carrier is 64 bytes, and we need three additional 1673 * carrier for icq, irq, and the termination carrier. 1674 */ 1675 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3) 1676 1677 #define ADV_CARRIER_BUFSIZE \ 1678 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) 1679 1680 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ 1681 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ 1682 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ 1683 1684 /* 1685 * Adapter temporary configuration structure 1686 * 1687 * This structure can be discarded after initialization. Don't add 1688 * fields here needed after initialization. 1689 * 1690 * Field naming convention: 1691 * 1692 * *_enable indicates the field enables or disables a feature. The 1693 * value of the field is never reset. 1694 */ 1695 typedef struct adv_dvc_cfg { 1696 ushort disc_enable; /* enable disconnection */ 1697 uchar chip_version; /* chip version */ 1698 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */ 1699 ushort control_flag; /* Microcode Control Flag */ 1700 ushort mcode_date; /* Microcode date */ 1701 ushort mcode_version; /* Microcode version */ 1702 ushort serial1; /* EEPROM serial number word 1 */ 1703 ushort serial2; /* EEPROM serial number word 2 */ 1704 ushort serial3; /* EEPROM serial number word 3 */ 1705 } ADV_DVC_CFG; 1706 1707 struct adv_dvc_var; 1708 struct adv_scsi_req_q; 1709 1710 typedef struct adv_sg_block { 1711 uchar reserved1; 1712 uchar reserved2; 1713 uchar reserved3; 1714 uchar sg_cnt; /* Valid entries in block. */ 1715 __le32 sg_ptr; /* Pointer to next sg block. */ 1716 struct { 1717 __le32 sg_addr; /* SG element address. */ 1718 __le32 sg_count; /* SG element count. */ 1719 } sg_list[NO_OF_SG_PER_BLOCK]; 1720 } ADV_SG_BLOCK; 1721 1722 /* 1723 * ADV_SCSI_REQ_Q - microcode request structure 1724 * 1725 * All fields in this structure up to byte 60 are used by the microcode. 1726 * The microcode makes assumptions about the size and ordering of fields 1727 * in this structure. Do not change the structure definition here without 1728 * coordinating the change with the microcode. 1729 * 1730 * All fields accessed by microcode must be maintained in little_endian 1731 * order. 1732 */ 1733 typedef struct adv_scsi_req_q { 1734 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */ 1735 uchar target_cmd; 1736 uchar target_id; /* Device target identifier. */ 1737 uchar target_lun; /* Device target logical unit number. */ 1738 __le32 data_addr; /* Data buffer physical address. */ 1739 __le32 data_cnt; /* Data count. Ucode sets to residual. */ 1740 __le32 sense_addr; 1741 __le32 carr_pa; 1742 uchar mflag; 1743 uchar sense_len; 1744 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */ 1745 uchar scsi_cntl; 1746 uchar done_status; /* Completion status. */ 1747 uchar scsi_status; /* SCSI status byte. */ 1748 uchar host_status; /* Ucode host status. */ 1749 uchar sg_working_ix; 1750 uchar cdb[12]; /* SCSI CDB bytes 0-11. */ 1751 __le32 sg_real_addr; /* SG list physical address. */ 1752 __le32 scsiq_rptr; 1753 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */ 1754 __le32 scsiq_ptr; 1755 __le32 carr_va; 1756 /* 1757 * End of microcode structure - 60 bytes. The rest of the structure 1758 * is used by the Adv Library and ignored by the microcode. 1759 */ 1760 u32 srb_tag; 1761 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */ 1762 } ADV_SCSI_REQ_Q; 1763 1764 /* 1765 * The following two structures are used to process Wide Board requests. 1766 * 1767 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library 1768 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the 1769 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points 1770 * to the Mid-Level SCSI request structure. 1771 * 1772 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each 1773 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux 1774 * up to 255 scatter-gather elements may be used per request or 1775 * ADV_SCSI_REQ_Q. 1776 * 1777 * Both structures must be 32 byte aligned. 1778 */ 1779 typedef struct adv_sgblk { 1780 ADV_SG_BLOCK sg_block; /* Sgblock structure. */ 1781 dma_addr_t sg_addr; /* Physical address */ 1782 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */ 1783 } adv_sgblk_t; 1784 1785 typedef struct adv_req { 1786 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */ 1787 uchar align[24]; /* Request structure padding. */ 1788 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */ 1789 dma_addr_t req_addr; 1790 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */ 1791 } adv_req_t __aligned(32); 1792 1793 /* 1794 * Adapter operation variable structure. 1795 * 1796 * One structure is required per host adapter. 1797 * 1798 * Field naming convention: 1799 * 1800 * *_able indicates both whether a feature should be enabled or disabled 1801 * and whether a device is capable of the feature. At initialization 1802 * this field may be set, but later if a device is found to be incapable 1803 * of the feature, the field is cleared. 1804 */ 1805 typedef struct adv_dvc_var { 1806 AdvPortAddr iop_base; /* I/O port address */ 1807 ushort err_code; /* fatal error code */ 1808 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */ 1809 ushort wdtr_able; /* try WDTR for a device */ 1810 ushort sdtr_able; /* try SDTR for a device */ 1811 ushort ultra_able; /* try SDTR Ultra speed for a device */ 1812 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */ 1813 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */ 1814 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */ 1815 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */ 1816 ushort tagqng_able; /* try tagged queuing with a device */ 1817 ushort ppr_able; /* PPR message capable per TID bitmask. */ 1818 uchar max_dvc_qng; /* maximum number of tagged commands per device */ 1819 ushort start_motor; /* start motor command allowed */ 1820 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */ 1821 uchar chip_no; /* should be assigned by caller */ 1822 uchar max_host_qng; /* maximum number of Q'ed command allowed */ 1823 ushort no_scam; /* scam_tolerant of EEPROM */ 1824 struct asc_board *drv_ptr; /* driver pointer to private structure */ 1825 uchar chip_scsi_id; /* chip SCSI target ID */ 1826 uchar chip_type; 1827 uchar bist_err_code; 1828 ADV_CARR_T *carrier; 1829 ADV_CARR_T *carr_freelist; /* Carrier free list. */ 1830 dma_addr_t carrier_addr; 1831 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */ 1832 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */ 1833 ushort carr_pending_cnt; /* Count of pending carriers. */ 1834 /* 1835 * Note: The following fields will not be used after initialization. The 1836 * driver may discard the buffer after initialization is done. 1837 */ 1838 ADV_DVC_CFG *cfg; /* temporary configuration structure */ 1839 } ADV_DVC_VAR; 1840 1841 /* 1842 * Microcode idle loop commands 1843 */ 1844 #define IDLE_CMD_COMPLETED 0 1845 #define IDLE_CMD_STOP_CHIP 0x0001 1846 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002 1847 #define IDLE_CMD_SEND_INT 0x0004 1848 #define IDLE_CMD_ABORT 0x0008 1849 #define IDLE_CMD_DEVICE_RESET 0x0010 1850 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */ 1851 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */ 1852 #define IDLE_CMD_SCSIREQ 0x0080 1853 1854 #define IDLE_CMD_STATUS_SUCCESS 0x0001 1855 #define IDLE_CMD_STATUS_FAILURE 0x0002 1856 1857 /* 1858 * AdvSendIdleCmd() flag definitions. 1859 */ 1860 #define ADV_NOWAIT 0x01 1861 1862 /* 1863 * Wait loop time out values. 1864 */ 1865 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */ 1866 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */ 1867 #define SCSI_MAX_RETRY 10 /* retry count */ 1868 1869 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 1870 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */ 1871 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */ 1872 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */ 1873 1874 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ 1875 1876 /* Read byte from a register. */ 1877 #define AdvReadByteRegister(iop_base, reg_off) \ 1878 (ADV_MEM_READB((iop_base) + (reg_off))) 1879 1880 /* Write byte to a register. */ 1881 #define AdvWriteByteRegister(iop_base, reg_off, byte) \ 1882 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte))) 1883 1884 /* Read word (2 bytes) from a register. */ 1885 #define AdvReadWordRegister(iop_base, reg_off) \ 1886 (ADV_MEM_READW((iop_base) + (reg_off))) 1887 1888 /* Write word (2 bytes) to a register. */ 1889 #define AdvWriteWordRegister(iop_base, reg_off, word) \ 1890 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word))) 1891 1892 /* Write dword (4 bytes) to a register. */ 1893 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \ 1894 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword))) 1895 1896 /* Read byte from LRAM. */ 1897 #define AdvReadByteLram(iop_base, addr, byte) \ 1898 do { \ 1899 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \ 1900 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \ 1901 } while (0) 1902 1903 /* Write byte to LRAM. */ 1904 #define AdvWriteByteLram(iop_base, addr, byte) \ 1905 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 1906 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte))) 1907 1908 /* Read word (2 bytes) from LRAM. */ 1909 #define AdvReadWordLram(iop_base, addr, word) \ 1910 do { \ 1911 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \ 1912 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \ 1913 } while (0) 1914 1915 /* Write word (2 bytes) to LRAM. */ 1916 #define AdvWriteWordLram(iop_base, addr, word) \ 1917 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 1918 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word))) 1919 1920 /* Write little-endian double word (4 bytes) to LRAM */ 1921 /* Because of unspecified C language ordering don't use auto-increment. */ 1922 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \ 1923 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 1924 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \ 1925 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \ 1926 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \ 1927 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \ 1928 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF))))) 1929 1930 /* Read word (2 bytes) from LRAM assuming that the address is already set. */ 1931 #define AdvReadWordAutoIncLram(iop_base) \ 1932 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)) 1933 1934 /* Write word (2 bytes) to LRAM assuming that the address is already set. */ 1935 #define AdvWriteWordAutoIncLram(iop_base, word) \ 1936 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word))) 1937 1938 /* 1939 * Define macro to check for Condor signature. 1940 * 1941 * Evaluate to ADV_TRUE if a Condor chip is found the specified port 1942 * address 'iop_base'. Otherwise evalue to ADV_FALSE. 1943 */ 1944 #define AdvFindSignature(iop_base) \ 1945 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \ 1946 ADV_CHIP_ID_BYTE) && \ 1947 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \ 1948 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE) 1949 1950 /* 1951 * Define macro to Return the version number of the chip at 'iop_base'. 1952 * 1953 * The second parameter 'bus_type' is currently unused. 1954 */ 1955 #define AdvGetChipVersion(iop_base, bus_type) \ 1956 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV) 1957 1958 /* 1959 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must 1960 * match the ADV_SCSI_REQ_Q 'srb_tag' field. 1961 * 1962 * If the request has not yet been sent to the device it will simply be 1963 * aborted from RISC memory. If the request is disconnected it will be 1964 * aborted on reselection by sending an Abort Message to the target ID. 1965 * 1966 * Return value: 1967 * ADV_TRUE(1) - Queue was successfully aborted. 1968 * ADV_FALSE(0) - Queue was not found on the active queue list. 1969 */ 1970 #define AdvAbortQueue(asc_dvc, srb_tag) \ 1971 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \ 1972 (ADV_DCNT) (srb_tag)) 1973 1974 /* 1975 * Send a Bus Device Reset Message to the specified target ID. 1976 * 1977 * All outstanding commands will be purged if sending the 1978 * Bus Device Reset Message is successful. 1979 * 1980 * Return Value: 1981 * ADV_TRUE(1) - All requests on the target are purged. 1982 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests 1983 * are not purged. 1984 */ 1985 #define AdvResetDevice(asc_dvc, target_id) \ 1986 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \ 1987 (ADV_DCNT) (target_id)) 1988 1989 /* 1990 * SCSI Wide Type definition. 1991 */ 1992 #define ADV_SCSI_BIT_ID_TYPE ushort 1993 1994 /* 1995 * AdvInitScsiTarget() 'cntl_flag' options. 1996 */ 1997 #define ADV_SCAN_LUN 0x01 1998 #define ADV_CAPINFO_NOLUN 0x02 1999 2000 /* 2001 * Convert target id to target id bit mask. 2002 */ 2003 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID)) 2004 2005 /* 2006 * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values. 2007 */ 2008 2009 #define QD_NO_STATUS 0x00 /* Request not completed yet. */ 2010 #define QD_NO_ERROR 0x01 2011 #define QD_ABORTED_BY_HOST 0x02 2012 #define QD_WITH_ERROR 0x04 2013 2014 #define QHSTA_NO_ERROR 0x00 2015 #define QHSTA_M_SEL_TIMEOUT 0x11 2016 #define QHSTA_M_DATA_OVER_RUN 0x12 2017 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 2018 #define QHSTA_M_QUEUE_ABORTED 0x15 2019 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ 2020 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ 2021 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ 2022 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ 2023 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ 2024 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ 2025 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ 2026 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ 2027 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ 2028 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ 2029 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ 2030 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ 2031 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ 2032 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ 2033 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ 2034 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ 2035 #define QHSTA_M_WTM_TIMEOUT 0x41 2036 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 2037 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 2038 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 2039 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ 2040 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ 2041 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ 2042 2043 /* Return the address that is aligned at the next doubleword >= to 'addr'. */ 2044 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F) 2045 2046 /* 2047 * Total contiguous memory needed for driver SG blocks. 2048 * 2049 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum 2050 * number of scatter-gather elements the driver supports in a 2051 * single request. 2052 */ 2053 2054 #define ADV_SG_LIST_MAX_BYTE_SIZE \ 2055 (sizeof(ADV_SG_BLOCK) * \ 2056 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)) 2057 2058 /* struct asc_board flags */ 2059 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */ 2060 2061 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0) 2062 2063 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */ 2064 2065 #define ASC_INFO_SIZE 128 /* advansys_info() line size */ 2066 2067 /* Asc Library return codes */ 2068 #define ASC_TRUE 1 2069 #define ASC_FALSE 0 2070 #define ASC_NOERROR 1 2071 #define ASC_BUSY 0 2072 #define ASC_ERROR (-1) 2073 2074 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1) 2075 #ifndef ADVANSYS_STATS 2076 #define ASC_STATS_ADD(shost, counter, count) 2077 #else /* ADVANSYS_STATS */ 2078 #define ASC_STATS_ADD(shost, counter, count) \ 2079 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count)) 2080 #endif /* ADVANSYS_STATS */ 2081 2082 /* If the result wraps when calculating tenths, return 0. */ 2083 #define ASC_TENTHS(num, den) \ 2084 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \ 2085 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den))))) 2086 2087 /* 2088 * Display a message to the console. 2089 */ 2090 #define ASC_PRINT(s) \ 2091 { \ 2092 printk("advansys: "); \ 2093 printk(s); \ 2094 } 2095 2096 #define ASC_PRINT1(s, a1) \ 2097 { \ 2098 printk("advansys: "); \ 2099 printk((s), (a1)); \ 2100 } 2101 2102 #define ASC_PRINT2(s, a1, a2) \ 2103 { \ 2104 printk("advansys: "); \ 2105 printk((s), (a1), (a2)); \ 2106 } 2107 2108 #define ASC_PRINT3(s, a1, a2, a3) \ 2109 { \ 2110 printk("advansys: "); \ 2111 printk((s), (a1), (a2), (a3)); \ 2112 } 2113 2114 #define ASC_PRINT4(s, a1, a2, a3, a4) \ 2115 { \ 2116 printk("advansys: "); \ 2117 printk((s), (a1), (a2), (a3), (a4)); \ 2118 } 2119 2120 #ifndef ADVANSYS_DEBUG 2121 2122 #define ASC_DBG(lvl, s...) 2123 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) 2124 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) 2125 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) 2126 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) 2127 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) 2128 #define ASC_DBG_PRT_HEX(lvl, name, start, length) 2129 #define ASC_DBG_PRT_CDB(lvl, cdb, len) 2130 #define ASC_DBG_PRT_SENSE(lvl, sense, len) 2131 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) 2132 2133 #else /* ADVANSYS_DEBUG */ 2134 2135 /* 2136 * Debugging Message Levels: 2137 * 0: Errors Only 2138 * 1: High-Level Tracing 2139 * 2-N: Verbose Tracing 2140 */ 2141 2142 #define ASC_DBG(lvl, format, arg...) { \ 2143 if (asc_dbglvl >= (lvl)) \ 2144 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \ 2145 __func__ , ## arg); \ 2146 } 2147 2148 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \ 2149 { \ 2150 if (asc_dbglvl >= (lvl)) { \ 2151 asc_prt_scsi_host(s); \ 2152 } \ 2153 } 2154 2155 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \ 2156 { \ 2157 if (asc_dbglvl >= (lvl)) { \ 2158 asc_prt_asc_scsi_q(scsiqp); \ 2159 } \ 2160 } 2161 2162 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \ 2163 { \ 2164 if (asc_dbglvl >= (lvl)) { \ 2165 asc_prt_asc_qdone_info(qdone); \ 2166 } \ 2167 } 2168 2169 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \ 2170 { \ 2171 if (asc_dbglvl >= (lvl)) { \ 2172 asc_prt_adv_scsi_req_q(scsiqp); \ 2173 } \ 2174 } 2175 2176 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \ 2177 { \ 2178 if (asc_dbglvl >= (lvl)) { \ 2179 asc_prt_hex((name), (start), (length)); \ 2180 } \ 2181 } 2182 2183 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \ 2184 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len)); 2185 2186 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \ 2187 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len)); 2188 2189 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \ 2190 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len)); 2191 #endif /* ADVANSYS_DEBUG */ 2192 2193 #ifdef ADVANSYS_STATS 2194 2195 /* Per board statistics structure */ 2196 struct asc_stats { 2197 /* Driver Entrypoint Statistics */ 2198 unsigned int queuecommand; /* # calls to advansys_queuecommand() */ 2199 unsigned int reset; /* # calls to advansys_eh_bus_reset() */ 2200 unsigned int biosparam; /* # calls to advansys_biosparam() */ 2201 unsigned int interrupt; /* # advansys_interrupt() calls */ 2202 unsigned int callback; /* # calls to asc/adv_isr_callback() */ 2203 unsigned int done; /* # calls to request's scsi_done function */ 2204 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */ 2205 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */ 2206 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */ 2207 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */ 2208 unsigned int exe_noerror; /* # ASC_NOERROR returns. */ 2209 unsigned int exe_busy; /* # ASC_BUSY returns. */ 2210 unsigned int exe_error; /* # ASC_ERROR returns. */ 2211 unsigned int exe_unknown; /* # unknown returns. */ 2212 /* Data Transfer Statistics */ 2213 unsigned int xfer_cnt; /* # I/O requests received */ 2214 unsigned int xfer_elem; /* # scatter-gather elements */ 2215 unsigned int xfer_sect; /* # 512-byte blocks */ 2216 }; 2217 #endif /* ADVANSYS_STATS */ 2218 2219 /* 2220 * Structure allocated for each board. 2221 * 2222 * This structure is allocated by scsi_host_alloc() at the end 2223 * of the 'Scsi_Host' structure starting at the 'hostdata' 2224 * field. It is guaranteed to be allocated from DMA-able memory. 2225 */ 2226 struct asc_board { 2227 struct device *dev; 2228 struct Scsi_Host *shost; 2229 uint flags; /* Board flags */ 2230 unsigned int irq; 2231 union { 2232 ASC_DVC_VAR asc_dvc_var; /* Narrow board */ 2233 ADV_DVC_VAR adv_dvc_var; /* Wide board */ 2234 } dvc_var; 2235 union { 2236 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */ 2237 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */ 2238 } dvc_cfg; 2239 ushort asc_n_io_port; /* Number I/O ports. */ 2240 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */ 2241 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */ 2242 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */ 2243 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */ 2244 union { 2245 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */ 2246 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */ 2247 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */ 2248 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */ 2249 } eep_config; 2250 /* /proc/scsi/advansys/[0...] */ 2251 #ifdef ADVANSYS_STATS 2252 struct asc_stats asc_stats; /* Board statistics */ 2253 #endif /* ADVANSYS_STATS */ 2254 /* 2255 * The following fields are used only for Narrow Boards. 2256 */ 2257 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */ 2258 /* 2259 * The following fields are used only for Wide Boards. 2260 */ 2261 void __iomem *ioremap_addr; /* I/O Memory remap address. */ 2262 ushort ioport; /* I/O Port address. */ 2263 adv_req_t *adv_reqp; /* Request structures. */ 2264 dma_addr_t adv_reqp_addr; 2265 size_t adv_reqp_size; 2266 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */ 2267 ushort bios_signature; /* BIOS Signature. */ 2268 ushort bios_version; /* BIOS Version. */ 2269 ushort bios_codeseg; /* BIOS Code Segment. */ 2270 ushort bios_codelen; /* BIOS Code Segment Length. */ 2271 }; 2272 2273 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \ 2274 dvc_var.asc_dvc_var) 2275 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \ 2276 dvc_var.adv_dvc_var) 2277 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev) 2278 2279 struct advansys_cmd { 2280 dma_addr_t dma_handle; 2281 }; 2282 2283 static struct advansys_cmd *advansys_cmd(struct scsi_cmnd *cmd) 2284 { 2285 return scsi_cmd_priv(cmd); 2286 } 2287 2288 #ifdef ADVANSYS_DEBUG 2289 static int asc_dbglvl = 3; 2290 2291 /* 2292 * asc_prt_asc_dvc_var() 2293 */ 2294 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h) 2295 { 2296 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h); 2297 2298 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl " 2299 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl); 2300 2301 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type, 2302 (unsigned)h->init_sdtr); 2303 2304 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, " 2305 "chip_no 0x%x,\n", (unsigned)h->sdtr_done, 2306 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready, 2307 (unsigned)h->chip_no); 2308 2309 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait " 2310 "%u,\n", (unsigned)h->queue_full_or_busy, 2311 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait); 2312 2313 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, " 2314 "in_critical_cnt %u,\n", (unsigned)h->is_in_int, 2315 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng, 2316 (unsigned)h->in_critical_cnt); 2317 2318 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, " 2319 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage, 2320 (unsigned)h->init_state, (unsigned)h->no_scam, 2321 (unsigned)h->pci_fix_asyn_xfer); 2322 2323 printk(" cfg 0x%lx\n", (ulong)h->cfg); 2324 } 2325 2326 /* 2327 * asc_prt_asc_dvc_cfg() 2328 */ 2329 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h) 2330 { 2331 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h); 2332 2333 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n", 2334 h->can_tagged_qng, h->cmd_qng_enabled); 2335 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n", 2336 h->disc_enable, h->sdtr_enable); 2337 2338 printk(" chip_scsi_id %d, chip_version %d,\n", 2339 h->chip_scsi_id, h->chip_version); 2340 2341 printk(" mcode_date 0x%x, mcode_version %d\n", 2342 h->mcode_date, h->mcode_version); 2343 } 2344 2345 /* 2346 * asc_prt_adv_dvc_var() 2347 * 2348 * Display an ADV_DVC_VAR structure. 2349 */ 2350 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h) 2351 { 2352 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h); 2353 2354 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n", 2355 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able); 2356 2357 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n", 2358 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able); 2359 2360 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n", 2361 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait); 2362 2363 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n", 2364 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng, 2365 h->carr_freelist); 2366 2367 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp); 2368 2369 printk(" no_scam 0x%x, tagqng_able 0x%x\n", 2370 (unsigned)h->no_scam, (unsigned)h->tagqng_able); 2371 2372 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n", 2373 (unsigned)h->chip_scsi_id, (ulong)h->cfg); 2374 } 2375 2376 /* 2377 * asc_prt_adv_dvc_cfg() 2378 * 2379 * Display an ADV_DVC_CFG structure. 2380 */ 2381 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h) 2382 { 2383 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h); 2384 2385 printk(" disc_enable 0x%x, termination 0x%x\n", 2386 h->disc_enable, h->termination); 2387 2388 printk(" chip_version 0x%x, mcode_date 0x%x\n", 2389 h->chip_version, h->mcode_date); 2390 2391 printk(" mcode_version 0x%x, control_flag 0x%x\n", 2392 h->mcode_version, h->control_flag); 2393 } 2394 2395 /* 2396 * asc_prt_scsi_host() 2397 */ 2398 static void asc_prt_scsi_host(struct Scsi_Host *s) 2399 { 2400 struct asc_board *boardp = shost_priv(s); 2401 2402 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev)); 2403 printk(" host_no %d,\n", s->host_no); 2404 2405 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n", 2406 (ulong)s->base, (ulong)s->io_port, boardp->irq); 2407 2408 printk(" dma_channel %d, this_id %d, can_queue %d,\n", 2409 s->dma_channel, s->this_id, s->can_queue); 2410 2411 printk(" cmd_per_lun %d, sg_tablesize %d\n", 2412 s->cmd_per_lun, s->sg_tablesize); 2413 2414 if (ASC_NARROW_BOARD(boardp)) { 2415 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var); 2416 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg); 2417 } else { 2418 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var); 2419 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg); 2420 } 2421 } 2422 2423 /* 2424 * asc_prt_hex() 2425 * 2426 * Print hexadecimal output in 4 byte groupings 32 bytes 2427 * or 8 double-words per line. 2428 */ 2429 static void asc_prt_hex(char *f, uchar *s, int l) 2430 { 2431 int i; 2432 int j; 2433 int k; 2434 int m; 2435 2436 printk("%s: (%d bytes)\n", f, l); 2437 2438 for (i = 0; i < l; i += 32) { 2439 2440 /* Display a maximum of 8 double-words per line. */ 2441 if ((k = (l - i) / 4) >= 8) { 2442 k = 8; 2443 m = 0; 2444 } else { 2445 m = (l - i) % 4; 2446 } 2447 2448 for (j = 0; j < k; j++) { 2449 printk(" %2.2X%2.2X%2.2X%2.2X", 2450 (unsigned)s[i + (j * 4)], 2451 (unsigned)s[i + (j * 4) + 1], 2452 (unsigned)s[i + (j * 4) + 2], 2453 (unsigned)s[i + (j * 4) + 3]); 2454 } 2455 2456 switch (m) { 2457 case 0: 2458 default: 2459 break; 2460 case 1: 2461 printk(" %2.2X", (unsigned)s[i + (j * 4)]); 2462 break; 2463 case 2: 2464 printk(" %2.2X%2.2X", 2465 (unsigned)s[i + (j * 4)], 2466 (unsigned)s[i + (j * 4) + 1]); 2467 break; 2468 case 3: 2469 printk(" %2.2X%2.2X%2.2X", 2470 (unsigned)s[i + (j * 4) + 1], 2471 (unsigned)s[i + (j * 4) + 2], 2472 (unsigned)s[i + (j * 4) + 3]); 2473 break; 2474 } 2475 2476 printk("\n"); 2477 } 2478 } 2479 2480 /* 2481 * asc_prt_asc_scsi_q() 2482 */ 2483 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q) 2484 { 2485 ASC_SG_HEAD *sgp; 2486 int i; 2487 2488 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q); 2489 2490 printk 2491 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n", 2492 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag, 2493 q->q2.tag_code); 2494 2495 printk 2496 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", 2497 (ulong)le32_to_cpu(q->q1.data_addr), 2498 (ulong)le32_to_cpu(q->q1.data_cnt), 2499 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len); 2500 2501 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n", 2502 (ulong)q->cdbptr, q->q2.cdb_len, 2503 (ulong)q->sg_head, q->q1.sg_queue_cnt); 2504 2505 if (q->sg_head) { 2506 sgp = q->sg_head; 2507 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp); 2508 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, 2509 sgp->queue_cnt); 2510 for (i = 0; i < sgp->entry_cnt; i++) { 2511 printk(" [%u]: addr 0x%lx, bytes %lu\n", 2512 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr), 2513 (ulong)le32_to_cpu(sgp->sg_list[i].bytes)); 2514 } 2515 2516 } 2517 } 2518 2519 /* 2520 * asc_prt_asc_qdone_info() 2521 */ 2522 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q) 2523 { 2524 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q); 2525 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n", 2526 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len, 2527 q->d2.tag_code); 2528 printk 2529 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n", 2530 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg); 2531 } 2532 2533 /* 2534 * asc_prt_adv_sgblock() 2535 * 2536 * Display an ADV_SG_BLOCK structure. 2537 */ 2538 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b) 2539 { 2540 int i; 2541 2542 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n", 2543 (ulong)b, sgblockno); 2544 printk(" sg_cnt %u, sg_ptr 0x%x\n", 2545 b->sg_cnt, (u32)le32_to_cpu(b->sg_ptr)); 2546 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK); 2547 if (b->sg_ptr != 0) 2548 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK); 2549 for (i = 0; i < b->sg_cnt; i++) { 2550 printk(" [%u]: sg_addr 0x%x, sg_count 0x%x\n", 2551 i, (u32)le32_to_cpu(b->sg_list[i].sg_addr), 2552 (u32)le32_to_cpu(b->sg_list[i].sg_count)); 2553 } 2554 } 2555 2556 /* 2557 * asc_prt_adv_scsi_req_q() 2558 * 2559 * Display an ADV_SCSI_REQ_Q structure. 2560 */ 2561 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q) 2562 { 2563 int sg_blk_cnt; 2564 struct adv_sg_block *sg_ptr; 2565 adv_sgblk_t *sgblkp; 2566 2567 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q); 2568 2569 printk(" target_id %u, target_lun %u, srb_tag 0x%x\n", 2570 q->target_id, q->target_lun, q->srb_tag); 2571 2572 printk(" cntl 0x%x, data_addr 0x%lx\n", 2573 q->cntl, (ulong)le32_to_cpu(q->data_addr)); 2574 2575 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", 2576 (ulong)le32_to_cpu(q->data_cnt), 2577 (ulong)le32_to_cpu(q->sense_addr), q->sense_len); 2578 2579 printk 2580 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n", 2581 q->cdb_len, q->done_status, q->host_status, q->scsi_status); 2582 2583 printk(" sg_working_ix 0x%x, target_cmd %u\n", 2584 q->sg_working_ix, q->target_cmd); 2585 2586 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n", 2587 (ulong)le32_to_cpu(q->scsiq_rptr), 2588 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr); 2589 2590 /* Display the request's ADV_SG_BLOCK structures. */ 2591 if (q->sg_list_ptr != NULL) { 2592 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block); 2593 sg_blk_cnt = 0; 2594 while (sgblkp) { 2595 sg_ptr = &sgblkp->sg_block; 2596 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr); 2597 if (sg_ptr->sg_ptr == 0) { 2598 break; 2599 } 2600 sgblkp = sgblkp->next_sgblkp; 2601 sg_blk_cnt++; 2602 } 2603 } 2604 } 2605 #endif /* ADVANSYS_DEBUG */ 2606 2607 /* 2608 * advansys_info() 2609 * 2610 * Return suitable for printing on the console with the argument 2611 * adapter's configuration information. 2612 * 2613 * Note: The information line should not exceed ASC_INFO_SIZE bytes, 2614 * otherwise the static 'info' array will be overrun. 2615 */ 2616 static const char *advansys_info(struct Scsi_Host *shost) 2617 { 2618 static char info[ASC_INFO_SIZE]; 2619 struct asc_board *boardp = shost_priv(shost); 2620 ASC_DVC_VAR *asc_dvc_varp; 2621 ADV_DVC_VAR *adv_dvc_varp; 2622 char *busname; 2623 char *widename = NULL; 2624 2625 if (ASC_NARROW_BOARD(boardp)) { 2626 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; 2627 ASC_DBG(1, "begin\n"); 2628 2629 if (asc_dvc_varp->bus_type & ASC_IS_VL) { 2630 busname = "VL"; 2631 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) { 2632 busname = "EISA"; 2633 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) { 2634 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA) 2635 == ASC_IS_PCI_ULTRA) { 2636 busname = "PCI Ultra"; 2637 } else { 2638 busname = "PCI"; 2639 } 2640 } else { 2641 busname = "?"; 2642 shost_printk(KERN_ERR, shost, "unknown bus " 2643 "type %d\n", asc_dvc_varp->bus_type); 2644 } 2645 sprintf(info, 2646 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X", 2647 ASC_VERSION, busname, (ulong)shost->io_port, 2648 (ulong)shost->io_port + ASC_IOADR_GAP - 1, 2649 boardp->irq); 2650 } else { 2651 /* 2652 * Wide Adapter Information 2653 * 2654 * Memory-mapped I/O is used instead of I/O space to access 2655 * the adapter, but display the I/O Port range. The Memory 2656 * I/O address is displayed through the driver /proc file. 2657 */ 2658 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 2659 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2660 widename = "Ultra-Wide"; 2661 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2662 widename = "Ultra2-Wide"; 2663 } else { 2664 widename = "Ultra3-Wide"; 2665 } 2666 sprintf(info, 2667 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X", 2668 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base, 2669 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq); 2670 } 2671 BUG_ON(strlen(info) >= ASC_INFO_SIZE); 2672 ASC_DBG(1, "end\n"); 2673 return info; 2674 } 2675 2676 #ifdef CONFIG_PROC_FS 2677 2678 /* 2679 * asc_prt_board_devices() 2680 * 2681 * Print driver information for devices attached to the board. 2682 */ 2683 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost) 2684 { 2685 struct asc_board *boardp = shost_priv(shost); 2686 int chip_scsi_id; 2687 int i; 2688 2689 seq_printf(m, 2690 "\nDevice Information for AdvanSys SCSI Host %d:\n", 2691 shost->host_no); 2692 2693 if (ASC_NARROW_BOARD(boardp)) { 2694 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id; 2695 } else { 2696 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id; 2697 } 2698 2699 seq_puts(m, "Target IDs Detected:"); 2700 for (i = 0; i <= ADV_MAX_TID; i++) { 2701 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) 2702 seq_printf(m, " %X,", i); 2703 } 2704 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id); 2705 } 2706 2707 /* 2708 * Display Wide Board BIOS Information. 2709 */ 2710 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost) 2711 { 2712 struct asc_board *boardp = shost_priv(shost); 2713 ushort major, minor, letter; 2714 2715 seq_puts(m, "\nROM BIOS Version: "); 2716 2717 /* 2718 * If the BIOS saved a valid signature, then fill in 2719 * the BIOS code segment base address. 2720 */ 2721 if (boardp->bios_signature != 0x55AA) { 2722 seq_puts(m, "Disabled or Pre-3.1\n" 2723 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n" 2724 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n"); 2725 } else { 2726 major = (boardp->bios_version >> 12) & 0xF; 2727 minor = (boardp->bios_version >> 8) & 0xF; 2728 letter = (boardp->bios_version & 0xFF); 2729 2730 seq_printf(m, "%d.%d%c\n", 2731 major, minor, 2732 letter >= 26 ? '?' : letter + 'A'); 2733 /* 2734 * Current available ROM BIOS release is 3.1I for UW 2735 * and 3.2I for U2W. This code doesn't differentiate 2736 * UW and U2W boards. 2737 */ 2738 if (major < 3 || (major <= 3 && minor < 1) || 2739 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) { 2740 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n" 2741 "ftp://ftp.connectcom.net/pub\n"); 2742 } 2743 } 2744 } 2745 2746 /* 2747 * Add serial number to information bar if signature AAh 2748 * is found in at bit 15-9 (7 bits) of word 1. 2749 * 2750 * Serial Number consists fo 12 alpha-numeric digits. 2751 * 2752 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits) 2753 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits) 2754 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits) 2755 * 5 - Product revision (A-J) Word0: " " 2756 * 2757 * Signature Word1: 15-9 (7 bits) 2758 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit) 2759 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits) 2760 * 2761 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits) 2762 * 2763 * Note 1: Only production cards will have a serial number. 2764 * 2765 * Note 2: Signature is most significant 7 bits (0xFE). 2766 * 2767 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE. 2768 */ 2769 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp) 2770 { 2771 ushort w, num; 2772 2773 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) { 2774 return ASC_FALSE; 2775 } else { 2776 /* 2777 * First word - 6 digits. 2778 */ 2779 w = serialnum[0]; 2780 2781 /* Product type - 1st digit. */ 2782 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') { 2783 /* Product type is P=Prototype */ 2784 *cp += 0x8; 2785 } 2786 cp++; 2787 2788 /* Manufacturing location - 2nd digit. */ 2789 *cp++ = 'A' + ((w & 0x1C00) >> 10); 2790 2791 /* Product ID - 3rd, 4th digits. */ 2792 num = w & 0x3FF; 2793 *cp++ = '0' + (num / 100); 2794 num %= 100; 2795 *cp++ = '0' + (num / 10); 2796 2797 /* Product revision - 5th digit. */ 2798 *cp++ = 'A' + (num % 10); 2799 2800 /* 2801 * Second word 2802 */ 2803 w = serialnum[1]; 2804 2805 /* 2806 * Year - 6th digit. 2807 * 2808 * If bit 15 of third word is set, then the 2809 * last digit of the year is greater than 7. 2810 */ 2811 if (serialnum[2] & 0x8000) { 2812 *cp++ = '8' + ((w & 0x1C0) >> 6); 2813 } else { 2814 *cp++ = '0' + ((w & 0x1C0) >> 6); 2815 } 2816 2817 /* Week of year - 7th, 8th digits. */ 2818 num = w & 0x003F; 2819 *cp++ = '0' + num / 10; 2820 num %= 10; 2821 *cp++ = '0' + num; 2822 2823 /* 2824 * Third word 2825 */ 2826 w = serialnum[2] & 0x7FFF; 2827 2828 /* Serial number - 9th digit. */ 2829 *cp++ = 'A' + (w / 1000); 2830 2831 /* 10th, 11th, 12th digits. */ 2832 num = w % 1000; 2833 *cp++ = '0' + num / 100; 2834 num %= 100; 2835 *cp++ = '0' + num / 10; 2836 num %= 10; 2837 *cp++ = '0' + num; 2838 2839 *cp = '\0'; /* Null Terminate the string. */ 2840 return ASC_TRUE; 2841 } 2842 } 2843 2844 /* 2845 * asc_prt_asc_board_eeprom() 2846 * 2847 * Print board EEPROM configuration. 2848 */ 2849 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost) 2850 { 2851 struct asc_board *boardp = shost_priv(shost); 2852 ASCEEP_CONFIG *ep; 2853 int i; 2854 uchar serialstr[13]; 2855 2856 ep = &boardp->eep_config.asc_eep; 2857 2858 seq_printf(m, 2859 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", 2860 shost->host_no); 2861 2862 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr) 2863 == ASC_TRUE) 2864 seq_printf(m, " Serial Number: %s\n", serialstr); 2865 else if (ep->adapter_info[5] == 0xBB) 2866 seq_puts(m, 2867 " Default Settings Used for EEPROM-less Adapter.\n"); 2868 else 2869 seq_puts(m, " Serial Number Signature Not Present.\n"); 2870 2871 seq_printf(m, 2872 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2873 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng, 2874 ep->max_tag_qng); 2875 2876 seq_printf(m, 2877 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam); 2878 2879 seq_puts(m, " Target ID: "); 2880 for (i = 0; i <= ASC_MAX_TID; i++) 2881 seq_printf(m, " %d", i); 2882 2883 seq_puts(m, "\n Disconnects: "); 2884 for (i = 0; i <= ASC_MAX_TID; i++) 2885 seq_printf(m, " %c", 2886 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2887 2888 seq_puts(m, "\n Command Queuing: "); 2889 for (i = 0; i <= ASC_MAX_TID; i++) 2890 seq_printf(m, " %c", 2891 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2892 2893 seq_puts(m, "\n Start Motor: "); 2894 for (i = 0; i <= ASC_MAX_TID; i++) 2895 seq_printf(m, " %c", 2896 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2897 2898 seq_puts(m, "\n Synchronous Transfer:"); 2899 for (i = 0; i <= ASC_MAX_TID; i++) 2900 seq_printf(m, " %c", 2901 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2902 seq_putc(m, '\n'); 2903 } 2904 2905 /* 2906 * asc_prt_adv_board_eeprom() 2907 * 2908 * Print board EEPROM configuration. 2909 */ 2910 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost) 2911 { 2912 struct asc_board *boardp = shost_priv(shost); 2913 ADV_DVC_VAR *adv_dvc_varp; 2914 int i; 2915 char *termstr; 2916 uchar serialstr[13]; 2917 ADVEEP_3550_CONFIG *ep_3550 = NULL; 2918 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL; 2919 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL; 2920 ushort word; 2921 ushort *wordp; 2922 ushort sdtr_speed = 0; 2923 2924 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 2925 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2926 ep_3550 = &boardp->eep_config.adv_3550_eep; 2927 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2928 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep; 2929 } else { 2930 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep; 2931 } 2932 2933 seq_printf(m, 2934 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", 2935 shost->host_no); 2936 2937 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2938 wordp = &ep_3550->serial_number_word1; 2939 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2940 wordp = &ep_38C0800->serial_number_word1; 2941 } else { 2942 wordp = &ep_38C1600->serial_number_word1; 2943 } 2944 2945 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) 2946 seq_printf(m, " Serial Number: %s\n", serialstr); 2947 else 2948 seq_puts(m, " Serial Number Signature Not Present.\n"); 2949 2950 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) 2951 seq_printf(m, 2952 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2953 ep_3550->adapter_scsi_id, 2954 ep_3550->max_host_qng, ep_3550->max_dvc_qng); 2955 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) 2956 seq_printf(m, 2957 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2958 ep_38C0800->adapter_scsi_id, 2959 ep_38C0800->max_host_qng, 2960 ep_38C0800->max_dvc_qng); 2961 else 2962 seq_printf(m, 2963 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2964 ep_38C1600->adapter_scsi_id, 2965 ep_38C1600->max_host_qng, 2966 ep_38C1600->max_dvc_qng); 2967 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2968 word = ep_3550->termination; 2969 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2970 word = ep_38C0800->termination_lvd; 2971 } else { 2972 word = ep_38C1600->termination_lvd; 2973 } 2974 switch (word) { 2975 case 1: 2976 termstr = "Low Off/High Off"; 2977 break; 2978 case 2: 2979 termstr = "Low Off/High On"; 2980 break; 2981 case 3: 2982 termstr = "Low On/High On"; 2983 break; 2984 default: 2985 case 0: 2986 termstr = "Automatic"; 2987 break; 2988 } 2989 2990 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) 2991 seq_printf(m, 2992 " termination: %u (%s), bios_ctrl: 0x%x\n", 2993 ep_3550->termination, termstr, 2994 ep_3550->bios_ctrl); 2995 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) 2996 seq_printf(m, 2997 " termination: %u (%s), bios_ctrl: 0x%x\n", 2998 ep_38C0800->termination_lvd, termstr, 2999 ep_38C0800->bios_ctrl); 3000 else 3001 seq_printf(m, 3002 " termination: %u (%s), bios_ctrl: 0x%x\n", 3003 ep_38C1600->termination_lvd, termstr, 3004 ep_38C1600->bios_ctrl); 3005 3006 seq_puts(m, " Target ID: "); 3007 for (i = 0; i <= ADV_MAX_TID; i++) 3008 seq_printf(m, " %X", i); 3009 seq_putc(m, '\n'); 3010 3011 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3012 word = ep_3550->disc_enable; 3013 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3014 word = ep_38C0800->disc_enable; 3015 } else { 3016 word = ep_38C1600->disc_enable; 3017 } 3018 seq_puts(m, " Disconnects: "); 3019 for (i = 0; i <= ADV_MAX_TID; i++) 3020 seq_printf(m, " %c", 3021 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3022 seq_putc(m, '\n'); 3023 3024 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3025 word = ep_3550->tagqng_able; 3026 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3027 word = ep_38C0800->tagqng_able; 3028 } else { 3029 word = ep_38C1600->tagqng_able; 3030 } 3031 seq_puts(m, " Command Queuing: "); 3032 for (i = 0; i <= ADV_MAX_TID; i++) 3033 seq_printf(m, " %c", 3034 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3035 seq_putc(m, '\n'); 3036 3037 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3038 word = ep_3550->start_motor; 3039 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3040 word = ep_38C0800->start_motor; 3041 } else { 3042 word = ep_38C1600->start_motor; 3043 } 3044 seq_puts(m, " Start Motor: "); 3045 for (i = 0; i <= ADV_MAX_TID; i++) 3046 seq_printf(m, " %c", 3047 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3048 seq_putc(m, '\n'); 3049 3050 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3051 seq_puts(m, " Synchronous Transfer:"); 3052 for (i = 0; i <= ADV_MAX_TID; i++) 3053 seq_printf(m, " %c", 3054 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 3055 'Y' : 'N'); 3056 seq_putc(m, '\n'); 3057 } 3058 3059 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3060 seq_puts(m, " Ultra Transfer: "); 3061 for (i = 0; i <= ADV_MAX_TID; i++) 3062 seq_printf(m, " %c", 3063 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i)) 3064 ? 'Y' : 'N'); 3065 seq_putc(m, '\n'); 3066 } 3067 3068 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3069 word = ep_3550->wdtr_able; 3070 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3071 word = ep_38C0800->wdtr_able; 3072 } else { 3073 word = ep_38C1600->wdtr_able; 3074 } 3075 seq_puts(m, " Wide Transfer: "); 3076 for (i = 0; i <= ADV_MAX_TID; i++) 3077 seq_printf(m, " %c", 3078 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3079 seq_putc(m, '\n'); 3080 3081 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 || 3082 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) { 3083 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n "); 3084 for (i = 0; i <= ADV_MAX_TID; i++) { 3085 char *speed_str; 3086 3087 if (i == 0) { 3088 sdtr_speed = adv_dvc_varp->sdtr_speed1; 3089 } else if (i == 4) { 3090 sdtr_speed = adv_dvc_varp->sdtr_speed2; 3091 } else if (i == 8) { 3092 sdtr_speed = adv_dvc_varp->sdtr_speed3; 3093 } else if (i == 12) { 3094 sdtr_speed = adv_dvc_varp->sdtr_speed4; 3095 } 3096 switch (sdtr_speed & ADV_MAX_TID) { 3097 case 0: 3098 speed_str = "Off"; 3099 break; 3100 case 1: 3101 speed_str = " 5"; 3102 break; 3103 case 2: 3104 speed_str = " 10"; 3105 break; 3106 case 3: 3107 speed_str = " 20"; 3108 break; 3109 case 4: 3110 speed_str = " 40"; 3111 break; 3112 case 5: 3113 speed_str = " 80"; 3114 break; 3115 default: 3116 speed_str = "Unk"; 3117 break; 3118 } 3119 seq_printf(m, "%X:%s ", i, speed_str); 3120 if (i == 7) 3121 seq_puts(m, "\n "); 3122 sdtr_speed >>= 4; 3123 } 3124 seq_putc(m, '\n'); 3125 } 3126 } 3127 3128 /* 3129 * asc_prt_driver_conf() 3130 */ 3131 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost) 3132 { 3133 struct asc_board *boardp = shost_priv(shost); 3134 3135 seq_printf(m, 3136 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n", 3137 shost->host_no); 3138 3139 seq_printf(m, 3140 " host_busy %d, max_id %u, max_lun %llu, max_channel %u\n", 3141 scsi_host_busy(shost), shost->max_id, 3142 shost->max_lun, shost->max_channel); 3143 3144 seq_printf(m, 3145 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n", 3146 shost->unique_id, shost->can_queue, shost->this_id, 3147 shost->sg_tablesize, shost->cmd_per_lun); 3148 3149 seq_printf(m, 3150 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n", 3151 boardp->flags, shost->last_reset, jiffies, 3152 boardp->asc_n_io_port); 3153 3154 seq_printf(m, " io_port 0x%lx\n", shost->io_port); 3155 } 3156 3157 /* 3158 * asc_prt_asc_board_info() 3159 * 3160 * Print dynamic board configuration information. 3161 */ 3162 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost) 3163 { 3164 struct asc_board *boardp = shost_priv(shost); 3165 int chip_scsi_id; 3166 ASC_DVC_VAR *v; 3167 ASC_DVC_CFG *c; 3168 int i; 3169 int renegotiate = 0; 3170 3171 v = &boardp->dvc_var.asc_dvc_var; 3172 c = &boardp->dvc_cfg.asc_dvc_cfg; 3173 chip_scsi_id = c->chip_scsi_id; 3174 3175 seq_printf(m, 3176 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n", 3177 shost->host_no); 3178 3179 seq_printf(m, " chip_version %u, mcode_date 0x%x, " 3180 "mcode_version 0x%x, err_code %u\n", 3181 c->chip_version, c->mcode_date, c->mcode_version, 3182 v->err_code); 3183 3184 /* Current number of commands waiting for the host. */ 3185 seq_printf(m, 3186 " Total Command Pending: %d\n", v->cur_total_qng); 3187 3188 seq_puts(m, " Command Queuing:"); 3189 for (i = 0; i <= ASC_MAX_TID; i++) { 3190 if ((chip_scsi_id == i) || 3191 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3192 continue; 3193 } 3194 seq_printf(m, " %X:%c", 3195 i, 3196 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3197 } 3198 3199 /* Current number of commands waiting for a device. */ 3200 seq_puts(m, "\n Command Queue Pending:"); 3201 for (i = 0; i <= ASC_MAX_TID; i++) { 3202 if ((chip_scsi_id == i) || 3203 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3204 continue; 3205 } 3206 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]); 3207 } 3208 3209 /* Current limit on number of commands that can be sent to a device. */ 3210 seq_puts(m, "\n Command Queue Limit:"); 3211 for (i = 0; i <= ASC_MAX_TID; i++) { 3212 if ((chip_scsi_id == i) || 3213 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3214 continue; 3215 } 3216 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]); 3217 } 3218 3219 /* Indicate whether the device has returned queue full status. */ 3220 seq_puts(m, "\n Command Queue Full:"); 3221 for (i = 0; i <= ASC_MAX_TID; i++) { 3222 if ((chip_scsi_id == i) || 3223 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3224 continue; 3225 } 3226 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) 3227 seq_printf(m, " %X:Y-%d", 3228 i, boardp->queue_full_cnt[i]); 3229 else 3230 seq_printf(m, " %X:N", i); 3231 } 3232 3233 seq_puts(m, "\n Synchronous Transfer:"); 3234 for (i = 0; i <= ASC_MAX_TID; i++) { 3235 if ((chip_scsi_id == i) || 3236 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3237 continue; 3238 } 3239 seq_printf(m, " %X:%c", 3240 i, 3241 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3242 } 3243 seq_putc(m, '\n'); 3244 3245 for (i = 0; i <= ASC_MAX_TID; i++) { 3246 uchar syn_period_ix; 3247 3248 if ((chip_scsi_id == i) || 3249 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) || 3250 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) { 3251 continue; 3252 } 3253 3254 seq_printf(m, " %X:", i); 3255 3256 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) { 3257 seq_puts(m, " Asynchronous"); 3258 } else { 3259 syn_period_ix = 3260 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index - 3261 1); 3262 3263 seq_printf(m, 3264 " Transfer Period Factor: %d (%d.%d Mhz),", 3265 v->sdtr_period_tbl[syn_period_ix], 3266 250 / v->sdtr_period_tbl[syn_period_ix], 3267 ASC_TENTHS(250, 3268 v->sdtr_period_tbl[syn_period_ix])); 3269 3270 seq_printf(m, " REQ/ACK Offset: %d", 3271 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET); 3272 } 3273 3274 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3275 seq_puts(m, "*\n"); 3276 renegotiate = 1; 3277 } else { 3278 seq_putc(m, '\n'); 3279 } 3280 } 3281 3282 if (renegotiate) { 3283 seq_puts(m, " * = Re-negotiation pending before next command.\n"); 3284 } 3285 } 3286 3287 /* 3288 * asc_prt_adv_board_info() 3289 * 3290 * Print dynamic board configuration information. 3291 */ 3292 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost) 3293 { 3294 struct asc_board *boardp = shost_priv(shost); 3295 int i; 3296 ADV_DVC_VAR *v; 3297 ADV_DVC_CFG *c; 3298 AdvPortAddr iop_base; 3299 ushort chip_scsi_id; 3300 ushort lramword; 3301 uchar lrambyte; 3302 ushort tagqng_able; 3303 ushort sdtr_able, wdtr_able; 3304 ushort wdtr_done, sdtr_done; 3305 ushort period = 0; 3306 int renegotiate = 0; 3307 3308 v = &boardp->dvc_var.adv_dvc_var; 3309 c = &boardp->dvc_cfg.adv_dvc_cfg; 3310 iop_base = v->iop_base; 3311 chip_scsi_id = v->chip_scsi_id; 3312 3313 seq_printf(m, 3314 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n", 3315 shost->host_no); 3316 3317 seq_printf(m, 3318 " iop_base 0x%p, cable_detect: %X, err_code %u\n", 3319 v->iop_base, 3320 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT, 3321 v->err_code); 3322 3323 seq_printf(m, " chip_version %u, mcode_date 0x%x, " 3324 "mcode_version 0x%x\n", c->chip_version, 3325 c->mcode_date, c->mcode_version); 3326 3327 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 3328 seq_puts(m, " Queuing Enabled:"); 3329 for (i = 0; i <= ADV_MAX_TID; i++) { 3330 if ((chip_scsi_id == i) || 3331 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3332 continue; 3333 } 3334 3335 seq_printf(m, " %X:%c", 3336 i, 3337 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3338 } 3339 3340 seq_puts(m, "\n Queue Limit:"); 3341 for (i = 0; i <= ADV_MAX_TID; i++) { 3342 if ((chip_scsi_id == i) || 3343 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3344 continue; 3345 } 3346 3347 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i, 3348 lrambyte); 3349 3350 seq_printf(m, " %X:%d", i, lrambyte); 3351 } 3352 3353 seq_puts(m, "\n Command Pending:"); 3354 for (i = 0; i <= ADV_MAX_TID; i++) { 3355 if ((chip_scsi_id == i) || 3356 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3357 continue; 3358 } 3359 3360 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i, 3361 lrambyte); 3362 3363 seq_printf(m, " %X:%d", i, lrambyte); 3364 } 3365 seq_putc(m, '\n'); 3366 3367 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 3368 seq_puts(m, " Wide Enabled:"); 3369 for (i = 0; i <= ADV_MAX_TID; i++) { 3370 if ((chip_scsi_id == i) || 3371 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3372 continue; 3373 } 3374 3375 seq_printf(m, " %X:%c", 3376 i, 3377 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3378 } 3379 seq_putc(m, '\n'); 3380 3381 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done); 3382 seq_puts(m, " Transfer Bit Width:"); 3383 for (i = 0; i <= ADV_MAX_TID; i++) { 3384 if ((chip_scsi_id == i) || 3385 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3386 continue; 3387 } 3388 3389 AdvReadWordLram(iop_base, 3390 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i), 3391 lramword); 3392 3393 seq_printf(m, " %X:%d", 3394 i, (lramword & 0x8000) ? 16 : 8); 3395 3396 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) && 3397 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3398 seq_putc(m, '*'); 3399 renegotiate = 1; 3400 } 3401 } 3402 seq_putc(m, '\n'); 3403 3404 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 3405 seq_puts(m, " Synchronous Enabled:"); 3406 for (i = 0; i <= ADV_MAX_TID; i++) { 3407 if ((chip_scsi_id == i) || 3408 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3409 continue; 3410 } 3411 3412 seq_printf(m, " %X:%c", 3413 i, 3414 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3415 } 3416 seq_putc(m, '\n'); 3417 3418 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done); 3419 for (i = 0; i <= ADV_MAX_TID; i++) { 3420 3421 AdvReadWordLram(iop_base, 3422 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i), 3423 lramword); 3424 lramword &= ~0x8000; 3425 3426 if ((chip_scsi_id == i) || 3427 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) || 3428 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) { 3429 continue; 3430 } 3431 3432 seq_printf(m, " %X:", i); 3433 3434 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */ 3435 seq_puts(m, " Asynchronous"); 3436 } else { 3437 seq_puts(m, " Transfer Period Factor: "); 3438 3439 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */ 3440 seq_puts(m, "9 (80.0 Mhz),"); 3441 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */ 3442 seq_puts(m, "10 (40.0 Mhz),"); 3443 } else { /* 20 Mhz or below. */ 3444 3445 period = (((lramword >> 8) * 25) + 50) / 4; 3446 3447 if (period == 0) { /* Should never happen. */ 3448 seq_printf(m, "%d (? Mhz), ", period); 3449 } else { 3450 seq_printf(m, 3451 "%d (%d.%d Mhz),", 3452 period, 250 / period, 3453 ASC_TENTHS(250, period)); 3454 } 3455 } 3456 3457 seq_printf(m, " REQ/ACK Offset: %d", 3458 lramword & 0x1F); 3459 } 3460 3461 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3462 seq_puts(m, "*\n"); 3463 renegotiate = 1; 3464 } else { 3465 seq_putc(m, '\n'); 3466 } 3467 } 3468 3469 if (renegotiate) { 3470 seq_puts(m, " * = Re-negotiation pending before next command.\n"); 3471 } 3472 } 3473 3474 #ifdef ADVANSYS_STATS 3475 /* 3476 * asc_prt_board_stats() 3477 */ 3478 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost) 3479 { 3480 struct asc_board *boardp = shost_priv(shost); 3481 struct asc_stats *s = &boardp->asc_stats; 3482 3483 seq_printf(m, 3484 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n", 3485 shost->host_no); 3486 3487 seq_printf(m, 3488 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n", 3489 s->queuecommand, s->reset, s->biosparam, 3490 s->interrupt); 3491 3492 seq_printf(m, 3493 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n", 3494 s->callback, s->done, s->build_error, 3495 s->adv_build_noreq, s->adv_build_nosg); 3496 3497 seq_printf(m, 3498 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n", 3499 s->exe_noerror, s->exe_busy, s->exe_error, 3500 s->exe_unknown); 3501 3502 /* 3503 * Display data transfer statistics. 3504 */ 3505 if (s->xfer_cnt > 0) { 3506 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ", 3507 s->xfer_cnt, s->xfer_elem); 3508 3509 seq_printf(m, "xfer_bytes %u.%01u kb\n", 3510 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2)); 3511 3512 /* Scatter gather transfer statistics */ 3513 seq_printf(m, " avg_num_elem %u.%01u, ", 3514 s->xfer_elem / s->xfer_cnt, 3515 ASC_TENTHS(s->xfer_elem, s->xfer_cnt)); 3516 3517 seq_printf(m, "avg_elem_size %u.%01u kb, ", 3518 (s->xfer_sect / 2) / s->xfer_elem, 3519 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem)); 3520 3521 seq_printf(m, "avg_xfer_size %u.%01u kb\n", 3522 (s->xfer_sect / 2) / s->xfer_cnt, 3523 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt)); 3524 } 3525 } 3526 #endif /* ADVANSYS_STATS */ 3527 3528 /* 3529 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...} 3530 * 3531 * m: seq_file to print into 3532 * shost: Scsi_Host 3533 * 3534 * Return the number of bytes read from or written to a 3535 * /proc/scsi/advansys/[0...] file. 3536 */ 3537 static int 3538 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost) 3539 { 3540 struct asc_board *boardp = shost_priv(shost); 3541 3542 ASC_DBG(1, "begin\n"); 3543 3544 /* 3545 * User read of /proc/scsi/advansys/[0...] file. 3546 */ 3547 3548 /* 3549 * Get board configuration information. 3550 * 3551 * advansys_info() returns the board string from its own static buffer. 3552 */ 3553 /* Copy board information. */ 3554 seq_printf(m, "%s\n", (char *)advansys_info(shost)); 3555 /* 3556 * Display Wide Board BIOS Information. 3557 */ 3558 if (!ASC_NARROW_BOARD(boardp)) 3559 asc_prt_adv_bios(m, shost); 3560 3561 /* 3562 * Display driver information for each device attached to the board. 3563 */ 3564 asc_prt_board_devices(m, shost); 3565 3566 /* 3567 * Display EEPROM configuration for the board. 3568 */ 3569 if (ASC_NARROW_BOARD(boardp)) 3570 asc_prt_asc_board_eeprom(m, shost); 3571 else 3572 asc_prt_adv_board_eeprom(m, shost); 3573 3574 /* 3575 * Display driver configuration and information for the board. 3576 */ 3577 asc_prt_driver_conf(m, shost); 3578 3579 #ifdef ADVANSYS_STATS 3580 /* 3581 * Display driver statistics for the board. 3582 */ 3583 asc_prt_board_stats(m, shost); 3584 #endif /* ADVANSYS_STATS */ 3585 3586 /* 3587 * Display Asc Library dynamic configuration information 3588 * for the board. 3589 */ 3590 if (ASC_NARROW_BOARD(boardp)) 3591 asc_prt_asc_board_info(m, shost); 3592 else 3593 asc_prt_adv_board_info(m, shost); 3594 return 0; 3595 } 3596 #endif /* CONFIG_PROC_FS */ 3597 3598 static void asc_scsi_done(struct scsi_cmnd *scp) 3599 { 3600 scsi_dma_unmap(scp); 3601 ASC_STATS(scp->device->host, done); 3602 scsi_done(scp); 3603 } 3604 3605 static void AscSetBank(PortAddr iop_base, uchar bank) 3606 { 3607 uchar val; 3608 3609 val = AscGetChipControl(iop_base) & 3610 (~ 3611 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET | 3612 CC_CHIP_RESET)); 3613 if (bank == 1) { 3614 val |= CC_BANK_ONE; 3615 } else if (bank == 2) { 3616 val |= CC_DIAG | CC_BANK_ONE; 3617 } else { 3618 val &= ~CC_BANK_ONE; 3619 } 3620 AscSetChipControl(iop_base, val); 3621 } 3622 3623 static void AscSetChipIH(PortAddr iop_base, ushort ins_code) 3624 { 3625 AscSetBank(iop_base, 1); 3626 AscWriteChipIH(iop_base, ins_code); 3627 AscSetBank(iop_base, 0); 3628 } 3629 3630 static int AscStartChip(PortAddr iop_base) 3631 { 3632 AscSetChipControl(iop_base, 0); 3633 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) { 3634 return (0); 3635 } 3636 return (1); 3637 } 3638 3639 static bool AscStopChip(PortAddr iop_base) 3640 { 3641 uchar cc_val; 3642 3643 cc_val = 3644 AscGetChipControl(iop_base) & 3645 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG)); 3646 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT)); 3647 AscSetChipIH(iop_base, INS_HALT); 3648 AscSetChipIH(iop_base, INS_RFLAG_WTM); 3649 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) { 3650 return false; 3651 } 3652 return true; 3653 } 3654 3655 static bool AscIsChipHalted(PortAddr iop_base) 3656 { 3657 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) { 3658 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) { 3659 return true; 3660 } 3661 } 3662 return false; 3663 } 3664 3665 static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc) 3666 { 3667 PortAddr iop_base; 3668 int i = 10; 3669 3670 iop_base = asc_dvc->iop_base; 3671 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) 3672 && (i-- > 0)) { 3673 mdelay(100); 3674 } 3675 AscStopChip(iop_base); 3676 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT); 3677 udelay(60); 3678 AscSetChipIH(iop_base, INS_RFLAG_WTM); 3679 AscSetChipIH(iop_base, INS_HALT); 3680 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT); 3681 AscSetChipControl(iop_base, CC_HALT); 3682 mdelay(200); 3683 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); 3684 AscSetChipStatus(iop_base, 0); 3685 return (AscIsChipHalted(iop_base)); 3686 } 3687 3688 static int AscFindSignature(PortAddr iop_base) 3689 { 3690 ushort sig_word; 3691 3692 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n", 3693 iop_base, AscGetChipSignatureByte(iop_base)); 3694 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) { 3695 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n", 3696 iop_base, AscGetChipSignatureWord(iop_base)); 3697 sig_word = AscGetChipSignatureWord(iop_base); 3698 if ((sig_word == (ushort)ASC_1000_ID0W) || 3699 (sig_word == (ushort)ASC_1000_ID0W_FIX)) { 3700 return (1); 3701 } 3702 } 3703 return (0); 3704 } 3705 3706 static void AscEnableInterrupt(PortAddr iop_base) 3707 { 3708 ushort cfg; 3709 3710 cfg = AscGetChipCfgLsw(iop_base); 3711 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON); 3712 } 3713 3714 static void AscDisableInterrupt(PortAddr iop_base) 3715 { 3716 ushort cfg; 3717 3718 cfg = AscGetChipCfgLsw(iop_base); 3719 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON)); 3720 } 3721 3722 static uchar AscReadLramByte(PortAddr iop_base, ushort addr) 3723 { 3724 unsigned char byte_data; 3725 unsigned short word_data; 3726 3727 if (isodd_word(addr)) { 3728 AscSetChipLramAddr(iop_base, addr - 1); 3729 word_data = AscGetChipLramData(iop_base); 3730 byte_data = (word_data >> 8) & 0xFF; 3731 } else { 3732 AscSetChipLramAddr(iop_base, addr); 3733 word_data = AscGetChipLramData(iop_base); 3734 byte_data = word_data & 0xFF; 3735 } 3736 return byte_data; 3737 } 3738 3739 static ushort AscReadLramWord(PortAddr iop_base, ushort addr) 3740 { 3741 ushort word_data; 3742 3743 AscSetChipLramAddr(iop_base, addr); 3744 word_data = AscGetChipLramData(iop_base); 3745 return (word_data); 3746 } 3747 3748 static void 3749 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words) 3750 { 3751 int i; 3752 3753 AscSetChipLramAddr(iop_base, s_addr); 3754 for (i = 0; i < words; i++) { 3755 AscSetChipLramData(iop_base, set_wval); 3756 } 3757 } 3758 3759 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val) 3760 { 3761 AscSetChipLramAddr(iop_base, addr); 3762 AscSetChipLramData(iop_base, word_val); 3763 } 3764 3765 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val) 3766 { 3767 ushort word_data; 3768 3769 if (isodd_word(addr)) { 3770 addr--; 3771 word_data = AscReadLramWord(iop_base, addr); 3772 word_data &= 0x00FF; 3773 word_data |= (((ushort)byte_val << 8) & 0xFF00); 3774 } else { 3775 word_data = AscReadLramWord(iop_base, addr); 3776 word_data &= 0xFF00; 3777 word_data |= ((ushort)byte_val & 0x00FF); 3778 } 3779 AscWriteLramWord(iop_base, addr, word_data); 3780 } 3781 3782 /* 3783 * Copy 2 bytes to LRAM. 3784 * 3785 * The source data is assumed to be in little-endian order in memory 3786 * and is maintained in little-endian order when written to LRAM. 3787 */ 3788 static void 3789 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr, 3790 const uchar *s_buffer, int words) 3791 { 3792 int i; 3793 3794 AscSetChipLramAddr(iop_base, s_addr); 3795 for (i = 0; i < 2 * words; i += 2) { 3796 /* 3797 * On a little-endian system the second argument below 3798 * produces a little-endian ushort which is written to 3799 * LRAM in little-endian order. On a big-endian system 3800 * the second argument produces a big-endian ushort which 3801 * is "transparently" byte-swapped by outpw() and written 3802 * in little-endian order to LRAM. 3803 */ 3804 outpw(iop_base + IOP_RAM_DATA, 3805 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); 3806 } 3807 } 3808 3809 /* 3810 * Copy 4 bytes to LRAM. 3811 * 3812 * The source data is assumed to be in little-endian order in memory 3813 * and is maintained in little-endian order when written to LRAM. 3814 */ 3815 static void 3816 AscMemDWordCopyPtrToLram(PortAddr iop_base, 3817 ushort s_addr, uchar *s_buffer, int dwords) 3818 { 3819 int i; 3820 3821 AscSetChipLramAddr(iop_base, s_addr); 3822 for (i = 0; i < 4 * dwords; i += 4) { 3823 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */ 3824 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */ 3825 } 3826 } 3827 3828 /* 3829 * Copy 2 bytes from LRAM. 3830 * 3831 * The source data is assumed to be in little-endian order in LRAM 3832 * and is maintained in little-endian order when written to memory. 3833 */ 3834 static void 3835 AscMemWordCopyPtrFromLram(PortAddr iop_base, 3836 ushort s_addr, uchar *d_buffer, int words) 3837 { 3838 int i; 3839 ushort word; 3840 3841 AscSetChipLramAddr(iop_base, s_addr); 3842 for (i = 0; i < 2 * words; i += 2) { 3843 word = inpw(iop_base + IOP_RAM_DATA); 3844 d_buffer[i] = word & 0xff; 3845 d_buffer[i + 1] = (word >> 8) & 0xff; 3846 } 3847 } 3848 3849 static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words) 3850 { 3851 u32 sum = 0; 3852 int i; 3853 3854 for (i = 0; i < words; i++, s_addr += 2) { 3855 sum += AscReadLramWord(iop_base, s_addr); 3856 } 3857 return (sum); 3858 } 3859 3860 static void AscInitLram(ASC_DVC_VAR *asc_dvc) 3861 { 3862 uchar i; 3863 ushort s_addr; 3864 PortAddr iop_base; 3865 3866 iop_base = asc_dvc->iop_base; 3867 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0, 3868 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) * 3869 64) >> 1)); 3870 i = ASC_MIN_ACTIVE_QNO; 3871 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 3872 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 3873 (uchar)(i + 1)); 3874 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 3875 (uchar)(asc_dvc->max_total_qng)); 3876 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 3877 (uchar)i); 3878 i++; 3879 s_addr += ASC_QBLK_SIZE; 3880 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 3881 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 3882 (uchar)(i + 1)); 3883 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 3884 (uchar)(i - 1)); 3885 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 3886 (uchar)i); 3887 } 3888 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 3889 (uchar)ASC_QLINK_END); 3890 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 3891 (uchar)(asc_dvc->max_total_qng - 1)); 3892 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 3893 (uchar)asc_dvc->max_total_qng); 3894 i++; 3895 s_addr += ASC_QBLK_SIZE; 3896 for (; i <= (uchar)(asc_dvc->max_total_qng + 3); 3897 i++, s_addr += ASC_QBLK_SIZE) { 3898 AscWriteLramByte(iop_base, 3899 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i); 3900 AscWriteLramByte(iop_base, 3901 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i); 3902 AscWriteLramByte(iop_base, 3903 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i); 3904 } 3905 } 3906 3907 static u32 3908 AscLoadMicroCode(PortAddr iop_base, ushort s_addr, 3909 const uchar *mcode_buf, ushort mcode_size) 3910 { 3911 u32 chksum; 3912 ushort mcode_word_size; 3913 ushort mcode_chksum; 3914 3915 /* Write the microcode buffer starting at LRAM address 0. */ 3916 mcode_word_size = (ushort)(mcode_size >> 1); 3917 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size); 3918 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size); 3919 3920 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size); 3921 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum); 3922 mcode_chksum = (ushort)AscMemSumLramWord(iop_base, 3923 (ushort)ASC_CODE_SEC_BEG, 3924 (ushort)((mcode_size - 3925 s_addr - (ushort) 3926 ASC_CODE_SEC_BEG) / 3927 2)); 3928 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum); 3929 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum); 3930 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size); 3931 return chksum; 3932 } 3933 3934 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc) 3935 { 3936 PortAddr iop_base; 3937 int i; 3938 ushort lram_addr; 3939 3940 iop_base = asc_dvc->iop_base; 3941 AscPutRiscVarFreeQHead(iop_base, 1); 3942 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng); 3943 AscPutVarFreeQHead(iop_base, 1); 3944 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng); 3945 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B, 3946 (uchar)((int)asc_dvc->max_total_qng + 1)); 3947 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B, 3948 (uchar)((int)asc_dvc->max_total_qng + 2)); 3949 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B, 3950 asc_dvc->max_total_qng); 3951 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0); 3952 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 3953 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0); 3954 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0); 3955 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0); 3956 AscPutQDoneInProgress(iop_base, 0); 3957 lram_addr = ASC_QADR_BEG; 3958 for (i = 0; i < 32; i++, lram_addr += 2) { 3959 AscWriteLramWord(iop_base, lram_addr, 0); 3960 } 3961 } 3962 3963 static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc) 3964 { 3965 int i; 3966 int warn_code; 3967 PortAddr iop_base; 3968 __le32 phy_addr; 3969 __le32 phy_size; 3970 struct asc_board *board = asc_dvc_to_board(asc_dvc); 3971 3972 iop_base = asc_dvc->iop_base; 3973 warn_code = 0; 3974 for (i = 0; i <= ASC_MAX_TID; i++) { 3975 AscPutMCodeInitSDTRAtID(iop_base, i, 3976 asc_dvc->cfg->sdtr_period_offset[i]); 3977 } 3978 3979 AscInitQLinkVar(asc_dvc); 3980 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B, 3981 asc_dvc->cfg->disc_enable); 3982 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B, 3983 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id)); 3984 3985 /* Ensure overrun buffer is aligned on an 8 byte boundary. */ 3986 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7); 3987 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf, 3988 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 3989 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) { 3990 warn_code = -ENOMEM; 3991 goto err_dma_map; 3992 } 3993 phy_addr = cpu_to_le32(asc_dvc->overrun_dma); 3994 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D, 3995 (uchar *)&phy_addr, 1); 3996 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE); 3997 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D, 3998 (uchar *)&phy_size, 1); 3999 4000 asc_dvc->cfg->mcode_date = 4001 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W); 4002 asc_dvc->cfg->mcode_version = 4003 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W); 4004 4005 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR); 4006 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) { 4007 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR; 4008 warn_code = -EINVAL; 4009 goto err_mcode_start; 4010 } 4011 if (AscStartChip(iop_base) != 1) { 4012 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; 4013 warn_code = -EIO; 4014 goto err_mcode_start; 4015 } 4016 4017 return warn_code; 4018 4019 err_mcode_start: 4020 dma_unmap_single(board->dev, asc_dvc->overrun_dma, 4021 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 4022 err_dma_map: 4023 asc_dvc->overrun_dma = 0; 4024 return warn_code; 4025 } 4026 4027 static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc) 4028 { 4029 const struct firmware *fw; 4030 const char fwname[] = "advansys/mcode.bin"; 4031 int err; 4032 unsigned long chksum; 4033 int warn_code; 4034 PortAddr iop_base; 4035 4036 iop_base = asc_dvc->iop_base; 4037 warn_code = 0; 4038 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) && 4039 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) { 4040 AscResetChipAndScsiBus(asc_dvc); 4041 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ 4042 } 4043 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC; 4044 if (asc_dvc->err_code != 0) 4045 return ASC_ERROR; 4046 if (!AscFindSignature(asc_dvc->iop_base)) { 4047 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 4048 return warn_code; 4049 } 4050 AscDisableInterrupt(iop_base); 4051 AscInitLram(asc_dvc); 4052 4053 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 4054 if (err) { 4055 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 4056 fwname, err); 4057 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4058 return err; 4059 } 4060 if (fw->size < 4) { 4061 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 4062 fw->size, fwname); 4063 release_firmware(fw); 4064 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4065 return -EINVAL; 4066 } 4067 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 4068 (fw->data[1] << 8) | fw->data[0]; 4069 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum); 4070 if (AscLoadMicroCode(iop_base, 0, &fw->data[4], 4071 fw->size - 4) != chksum) { 4072 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4073 release_firmware(fw); 4074 return warn_code; 4075 } 4076 release_firmware(fw); 4077 warn_code |= AscInitMicroCodeVar(asc_dvc); 4078 if (!asc_dvc->overrun_dma) 4079 return warn_code; 4080 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC; 4081 AscEnableInterrupt(iop_base); 4082 return warn_code; 4083 } 4084 4085 /* 4086 * Load the Microcode 4087 * 4088 * Write the microcode image to RISC memory starting at address 0. 4089 * 4090 * The microcode is stored compressed in the following format: 4091 * 4092 * 254 word (508 byte) table indexed by byte code followed 4093 * by the following byte codes: 4094 * 4095 * 1-Byte Code: 4096 * 00: Emit word 0 in table. 4097 * 01: Emit word 1 in table. 4098 * . 4099 * FD: Emit word 253 in table. 4100 * 4101 * Multi-Byte Code: 4102 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 4103 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 4104 * 4105 * Returns 0 or an error if the checksum doesn't match 4106 */ 4107 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf, 4108 int size, int memsize, int chksum) 4109 { 4110 int i, j, end, len = 0; 4111 u32 sum; 4112 4113 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0); 4114 4115 for (i = 253 * 2; i < size; i++) { 4116 if (buf[i] == 0xff) { 4117 unsigned short word = (buf[i + 3] << 8) | buf[i + 2]; 4118 for (j = 0; j < buf[i + 1]; j++) { 4119 AdvWriteWordAutoIncLram(iop_base, word); 4120 len += 2; 4121 } 4122 i += 3; 4123 } else if (buf[i] == 0xfe) { 4124 unsigned short word = (buf[i + 2] << 8) | buf[i + 1]; 4125 AdvWriteWordAutoIncLram(iop_base, word); 4126 i += 2; 4127 len += 2; 4128 } else { 4129 unsigned int off = buf[i] * 2; 4130 unsigned short word = (buf[off + 1] << 8) | buf[off]; 4131 AdvWriteWordAutoIncLram(iop_base, word); 4132 len += 2; 4133 } 4134 } 4135 4136 end = len; 4137 4138 while (len < memsize) { 4139 AdvWriteWordAutoIncLram(iop_base, 0); 4140 len += 2; 4141 } 4142 4143 /* Verify the microcode checksum. */ 4144 sum = 0; 4145 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0); 4146 4147 for (len = 0; len < end; len += 2) { 4148 sum += AdvReadWordAutoIncLram(iop_base); 4149 } 4150 4151 if (sum != chksum) 4152 return ASC_IERR_MCODE_CHKSUM; 4153 4154 return 0; 4155 } 4156 4157 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc) 4158 { 4159 off_t carr_offset = 0, next_offset; 4160 dma_addr_t carr_paddr; 4161 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i; 4162 4163 for (i = 0; i < carr_num; i++) { 4164 carr_offset = i * sizeof(ADV_CARR_T); 4165 /* Get physical address of the carrier 'carrp'. */ 4166 carr_paddr = adv_dvc->carrier_addr + carr_offset; 4167 4168 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr); 4169 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset); 4170 adv_dvc->carrier[i].areq_vpa = 0; 4171 next_offset = carr_offset + sizeof(ADV_CARR_T); 4172 if (i == carr_num) 4173 next_offset = ~0; 4174 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset); 4175 } 4176 /* 4177 * We cannot have a carrier with 'carr_va' of '0', as 4178 * a reference to this carrier would be interpreted as 4179 * list termination. 4180 * So start at carrier 1 with the freelist. 4181 */ 4182 adv_dvc->carr_freelist = &adv_dvc->carrier[1]; 4183 } 4184 4185 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset) 4186 { 4187 int index; 4188 4189 BUG_ON(offset > ADV_CARRIER_BUFSIZE); 4190 4191 index = offset / sizeof(ADV_CARR_T); 4192 return &adv_dvc->carrier[index]; 4193 } 4194 4195 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc) 4196 { 4197 ADV_CARR_T *carrp = adv_dvc->carr_freelist; 4198 u32 next_vpa = le32_to_cpu(carrp->next_vpa); 4199 4200 if (next_vpa == 0 || next_vpa == ~0) { 4201 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa); 4202 return NULL; 4203 } 4204 4205 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa); 4206 /* 4207 * insert stopper carrier to terminate list 4208 */ 4209 carrp->next_vpa = cpu_to_le32(ADV_CQ_STOPPER); 4210 4211 return carrp; 4212 } 4213 4214 /* 4215 * 'offset' is the index in the request pointer array 4216 */ 4217 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset) 4218 { 4219 struct asc_board *boardp = adv_dvc->drv_ptr; 4220 4221 BUG_ON(offset > adv_dvc->max_host_qng); 4222 return &boardp->adv_reqp[offset]; 4223 } 4224 4225 /* 4226 * Send an idle command to the chip and wait for completion. 4227 * 4228 * Command completion is polled for once per microsecond. 4229 * 4230 * The function can be called from anywhere including an interrupt handler. 4231 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical() 4232 * functions to prevent reentrancy. 4233 * 4234 * Return Values: 4235 * ADV_TRUE - command completed successfully 4236 * ADV_FALSE - command failed 4237 * ADV_ERROR - command timed out 4238 */ 4239 static int 4240 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc, 4241 ushort idle_cmd, u32 idle_cmd_parameter) 4242 { 4243 int result, i, j; 4244 AdvPortAddr iop_base; 4245 4246 iop_base = asc_dvc->iop_base; 4247 4248 /* 4249 * Clear the idle command status which is set by the microcode 4250 * to a non-zero value to indicate when the command is completed. 4251 * The non-zero result is one of the IDLE_CMD_STATUS_* values 4252 */ 4253 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0); 4254 4255 /* 4256 * Write the idle command value after the idle command parameter 4257 * has been written to avoid a race condition. If the order is not 4258 * followed, the microcode may process the idle command before the 4259 * parameters have been written to LRAM. 4260 */ 4261 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER, 4262 cpu_to_le32(idle_cmd_parameter)); 4263 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd); 4264 4265 /* 4266 * Tickle the RISC to tell it to process the idle command. 4267 */ 4268 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B); 4269 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 4270 /* 4271 * Clear the tickle value. In the ASC-3550 the RISC flag 4272 * command 'clr_tickle_b' does not work unless the host 4273 * value is cleared. 4274 */ 4275 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP); 4276 } 4277 4278 /* Wait for up to 100 millisecond for the idle command to timeout. */ 4279 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 4280 /* Poll once each microsecond for command completion. */ 4281 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 4282 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, 4283 result); 4284 if (result != 0) 4285 return result; 4286 udelay(1); 4287 } 4288 } 4289 4290 BUG(); /* The idle command should never timeout. */ 4291 return ADV_ERROR; 4292 } 4293 4294 /* 4295 * Reset SCSI Bus and purge all outstanding requests. 4296 * 4297 * Return Value: 4298 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset. 4299 * ADV_FALSE(0) - Microcode command failed. 4300 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC 4301 * may be hung which requires driver recovery. 4302 */ 4303 static int AdvResetSB(ADV_DVC_VAR *asc_dvc) 4304 { 4305 int status; 4306 4307 /* 4308 * Send the SCSI Bus Reset idle start idle command which asserts 4309 * the SCSI Bus Reset signal. 4310 */ 4311 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L); 4312 if (status != ADV_TRUE) { 4313 return status; 4314 } 4315 4316 /* 4317 * Delay for the specified SCSI Bus Reset hold time. 4318 * 4319 * The hold time delay is done on the host because the RISC has no 4320 * microsecond accurate timer. 4321 */ 4322 udelay(ASC_SCSI_RESET_HOLD_TIME_US); 4323 4324 /* 4325 * Send the SCSI Bus Reset end idle command which de-asserts 4326 * the SCSI Bus Reset signal and purges any pending requests. 4327 */ 4328 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L); 4329 if (status != ADV_TRUE) { 4330 return status; 4331 } 4332 4333 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ 4334 4335 return status; 4336 } 4337 4338 /* 4339 * Initialize the ASC-3550. 4340 * 4341 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 4342 * 4343 * For a non-fatal error return a warning code. If there are no warnings 4344 * then 0 is returned. 4345 * 4346 * Needed after initialization for error recovery. 4347 */ 4348 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc) 4349 { 4350 const struct firmware *fw; 4351 const char fwname[] = "advansys/3550.bin"; 4352 AdvPortAddr iop_base; 4353 ushort warn_code; 4354 int begin_addr; 4355 int end_addr; 4356 ushort code_sum; 4357 int word; 4358 int i; 4359 int err; 4360 unsigned long chksum; 4361 ushort scsi_cfg1; 4362 uchar tid; 4363 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 4364 ushort wdtr_able = 0, sdtr_able, tagqng_able; 4365 uchar max_cmd[ADV_MAX_TID + 1]; 4366 4367 /* If there is already an error, don't continue. */ 4368 if (asc_dvc->err_code != 0) 4369 return ADV_ERROR; 4370 4371 /* 4372 * The caller must set 'chip_type' to ADV_CHIP_ASC3550. 4373 */ 4374 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) { 4375 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 4376 return ADV_ERROR; 4377 } 4378 4379 warn_code = 0; 4380 iop_base = asc_dvc->iop_base; 4381 4382 /* 4383 * Save the RISC memory BIOS region before writing the microcode. 4384 * The BIOS may already be loaded and using its RISC LRAM region 4385 * so its region must be saved and restored. 4386 * 4387 * Note: This code makes the assumption, which is currently true, 4388 * that a chip reset does not clear RISC LRAM. 4389 */ 4390 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4391 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4392 bios_mem[i]); 4393 } 4394 4395 /* 4396 * Save current per TID negotiated values. 4397 */ 4398 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) { 4399 ushort bios_version, major, minor; 4400 4401 bios_version = 4402 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2]; 4403 major = (bios_version >> 12) & 0xF; 4404 minor = (bios_version >> 8) & 0xF; 4405 if (major < 3 || (major == 3 && minor == 1)) { 4406 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */ 4407 AdvReadWordLram(iop_base, 0x120, wdtr_able); 4408 } else { 4409 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 4410 } 4411 } 4412 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 4413 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 4414 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4415 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 4416 max_cmd[tid]); 4417 } 4418 4419 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 4420 if (err) { 4421 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 4422 fwname, err); 4423 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4424 return err; 4425 } 4426 if (fw->size < 4) { 4427 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 4428 fw->size, fwname); 4429 release_firmware(fw); 4430 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4431 return -EINVAL; 4432 } 4433 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 4434 (fw->data[1] << 8) | fw->data[0]; 4435 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 4436 fw->size - 4, ADV_3550_MEMSIZE, 4437 chksum); 4438 release_firmware(fw); 4439 if (asc_dvc->err_code) 4440 return ADV_ERROR; 4441 4442 /* 4443 * Restore the RISC memory BIOS region. 4444 */ 4445 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4446 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4447 bios_mem[i]); 4448 } 4449 4450 /* 4451 * Calculate and write the microcode code checksum to the microcode 4452 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 4453 */ 4454 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 4455 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 4456 code_sum = 0; 4457 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 4458 for (word = begin_addr; word < end_addr; word += 2) { 4459 code_sum += AdvReadWordAutoIncLram(iop_base); 4460 } 4461 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 4462 4463 /* 4464 * Read and save microcode version and date. 4465 */ 4466 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 4467 asc_dvc->cfg->mcode_date); 4468 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 4469 asc_dvc->cfg->mcode_version); 4470 4471 /* 4472 * Set the chip type to indicate the ASC3550. 4473 */ 4474 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550); 4475 4476 /* 4477 * If the PCI Configuration Command Register "Parity Error Response 4478 * Control" Bit was clear (0), then set the microcode variable 4479 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 4480 * to ignore DMA parity errors. 4481 */ 4482 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 4483 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 4484 word |= CONTROL_FLAG_IGNORE_PERR; 4485 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 4486 } 4487 4488 /* 4489 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO 4490 * threshold of 128 bytes. This register is only accessible to the host. 4491 */ 4492 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 4493 START_CTL_EMFU | READ_CMD_MRM); 4494 4495 /* 4496 * Microcode operating variables for WDTR, SDTR, and command tag 4497 * queuing will be set in sdev_configure() based on what a 4498 * device reports it is capable of in Inquiry byte 7. 4499 * 4500 * If SCSI Bus Resets have been disabled, then directly set 4501 * SDTR and WDTR from the EEPROM configuration. This will allow 4502 * the BIOS and warm boot to work without a SCSI bus hang on 4503 * the Inquiry caused by host and target mismatched DTR values. 4504 * Without the SCSI Bus Reset, before an Inquiry a device can't 4505 * be assumed to be in Asynchronous, Narrow mode. 4506 */ 4507 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 4508 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 4509 asc_dvc->wdtr_able); 4510 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 4511 asc_dvc->sdtr_able); 4512 } 4513 4514 /* 4515 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 4516 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 4517 * bitmask. These values determine the maximum SDTR speed negotiated 4518 * with a device. 4519 * 4520 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 4521 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 4522 * without determining here whether the device supports SDTR. 4523 * 4524 * 4-bit speed SDTR speed name 4525 * =========== =============== 4526 * 0000b (0x0) SDTR disabled 4527 * 0001b (0x1) 5 Mhz 4528 * 0010b (0x2) 10 Mhz 4529 * 0011b (0x3) 20 Mhz (Ultra) 4530 * 0100b (0x4) 40 Mhz (LVD/Ultra2) 4531 * 0101b (0x5) 80 Mhz (LVD2/Ultra3) 4532 * 0110b (0x6) Undefined 4533 * . 4534 * 1111b (0xF) Undefined 4535 */ 4536 word = 0; 4537 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4538 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) { 4539 /* Set Ultra speed for TID 'tid'. */ 4540 word |= (0x3 << (4 * (tid % 4))); 4541 } else { 4542 /* Set Fast speed for TID 'tid'. */ 4543 word |= (0x2 << (4 * (tid % 4))); 4544 } 4545 if (tid == 3) { /* Check if done with sdtr_speed1. */ 4546 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word); 4547 word = 0; 4548 } else if (tid == 7) { /* Check if done with sdtr_speed2. */ 4549 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word); 4550 word = 0; 4551 } else if (tid == 11) { /* Check if done with sdtr_speed3. */ 4552 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word); 4553 word = 0; 4554 } else if (tid == 15) { /* Check if done with sdtr_speed4. */ 4555 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word); 4556 /* End of loop. */ 4557 } 4558 } 4559 4560 /* 4561 * Set microcode operating variable for the disconnect per TID bitmask. 4562 */ 4563 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 4564 asc_dvc->cfg->disc_enable); 4565 4566 /* 4567 * Set SCSI_CFG0 Microcode Default Value. 4568 * 4569 * The microcode will set the SCSI_CFG0 register using this value 4570 * after it is started below. 4571 */ 4572 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 4573 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 4574 asc_dvc->chip_scsi_id); 4575 4576 /* 4577 * Determine SCSI_CFG1 Microcode Default Value. 4578 * 4579 * The microcode will set the SCSI_CFG1 register using this value 4580 * after it is started below. 4581 */ 4582 4583 /* Read current SCSI_CFG1 Register value. */ 4584 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 4585 4586 /* 4587 * If all three connectors are in use, return an error. 4588 */ 4589 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 4590 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 4591 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION; 4592 return ADV_ERROR; 4593 } 4594 4595 /* 4596 * If the internal narrow cable is reversed all of the SCSI_CTRL 4597 * register signals will be set. Check for and return an error if 4598 * this condition is found. 4599 */ 4600 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 4601 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 4602 return ADV_ERROR; 4603 } 4604 4605 /* 4606 * If this is a differential board and a single-ended device 4607 * is attached to one of the connectors, return an error. 4608 */ 4609 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) { 4610 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE; 4611 return ADV_ERROR; 4612 } 4613 4614 /* 4615 * If automatic termination control is enabled, then set the 4616 * termination value based on a table listed in a_condor.h. 4617 * 4618 * If manual termination was specified with an EEPROM setting 4619 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and 4620 * is ready to be 'ored' into SCSI_CFG1. 4621 */ 4622 if (asc_dvc->cfg->termination == 0) { 4623 /* 4624 * The software always controls termination by setting TERM_CTL_SEL. 4625 * If TERM_CTL_SEL were set to 0, the hardware would set termination. 4626 */ 4627 asc_dvc->cfg->termination |= TERM_CTL_SEL; 4628 4629 switch (scsi_cfg1 & CABLE_DETECT) { 4630 /* TERM_CTL_H: on, TERM_CTL_L: on */ 4631 case 0x3: 4632 case 0x7: 4633 case 0xB: 4634 case 0xD: 4635 case 0xE: 4636 case 0xF: 4637 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L); 4638 break; 4639 4640 /* TERM_CTL_H: on, TERM_CTL_L: off */ 4641 case 0x1: 4642 case 0x5: 4643 case 0x9: 4644 case 0xA: 4645 case 0xC: 4646 asc_dvc->cfg->termination |= TERM_CTL_H; 4647 break; 4648 4649 /* TERM_CTL_H: off, TERM_CTL_L: off */ 4650 case 0x2: 4651 case 0x6: 4652 break; 4653 } 4654 } 4655 4656 /* 4657 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 4658 */ 4659 scsi_cfg1 &= ~TERM_CTL; 4660 4661 /* 4662 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 4663 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 4664 * referenced, because the hardware internally inverts 4665 * the Termination High and Low bits if TERM_POL is set. 4666 */ 4667 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL)); 4668 4669 /* 4670 * Set SCSI_CFG1 Microcode Default Value 4671 * 4672 * Set filter value and possibly modified termination control 4673 * bits in the Microcode SCSI_CFG1 Register Value. 4674 * 4675 * The microcode will set the SCSI_CFG1 register using this value 4676 * after it is started below. 4677 */ 4678 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, 4679 FLTR_DISABLE | scsi_cfg1); 4680 4681 /* 4682 * Set MEM_CFG Microcode Default Value 4683 * 4684 * The microcode will set the MEM_CFG register using this value 4685 * after it is started below. 4686 * 4687 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 4688 * are defined. 4689 * 4690 * ASC-3550 has 8KB internal memory. 4691 */ 4692 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 4693 BIOS_EN | RAM_SZ_8KB); 4694 4695 /* 4696 * Set SEL_MASK Microcode Default Value 4697 * 4698 * The microcode will set the SEL_MASK register using this value 4699 * after it is started below. 4700 */ 4701 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 4702 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 4703 4704 AdvBuildCarrierFreelist(asc_dvc); 4705 4706 /* 4707 * Set-up the Host->RISC Initiator Command Queue (ICQ). 4708 */ 4709 4710 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc); 4711 if (!asc_dvc->icq_sp) { 4712 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 4713 return ADV_ERROR; 4714 } 4715 4716 /* 4717 * Set RISC ICQ physical address start value. 4718 */ 4719 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 4720 4721 /* 4722 * Set-up the RISC->Host Initiator Response Queue (IRQ). 4723 */ 4724 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc); 4725 if (!asc_dvc->irq_sp) { 4726 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 4727 return ADV_ERROR; 4728 } 4729 4730 /* 4731 * Set RISC IRQ physical address start value. 4732 */ 4733 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 4734 asc_dvc->carr_pending_cnt = 0; 4735 4736 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 4737 (ADV_INTR_ENABLE_HOST_INTR | 4738 ADV_INTR_ENABLE_GLOBAL_INTR)); 4739 4740 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 4741 AdvWriteWordRegister(iop_base, IOPW_PC, word); 4742 4743 /* finally, finally, gentlemen, start your engine */ 4744 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 4745 4746 /* 4747 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 4748 * Resets should be performed. The RISC has to be running 4749 * to issue a SCSI Bus Reset. 4750 */ 4751 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 4752 /* 4753 * If the BIOS Signature is present in memory, restore the 4754 * BIOS Handshake Configuration Table and do not perform 4755 * a SCSI Bus Reset. 4756 */ 4757 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 4758 0x55AA) { 4759 /* 4760 * Restore per TID negotiated values. 4761 */ 4762 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 4763 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 4764 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 4765 tagqng_able); 4766 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4767 AdvWriteByteLram(iop_base, 4768 ASC_MC_NUMBER_OF_MAX_CMD + tid, 4769 max_cmd[tid]); 4770 } 4771 } else { 4772 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 4773 warn_code = ASC_WARN_BUSRESET_ERROR; 4774 } 4775 } 4776 } 4777 4778 return warn_code; 4779 } 4780 4781 /* 4782 * Initialize the ASC-38C0800. 4783 * 4784 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 4785 * 4786 * For a non-fatal error return a warning code. If there are no warnings 4787 * then 0 is returned. 4788 * 4789 * Needed after initialization for error recovery. 4790 */ 4791 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc) 4792 { 4793 const struct firmware *fw; 4794 const char fwname[] = "advansys/38C0800.bin"; 4795 AdvPortAddr iop_base; 4796 ushort warn_code; 4797 int begin_addr; 4798 int end_addr; 4799 ushort code_sum; 4800 int word; 4801 int i; 4802 int err; 4803 unsigned long chksum; 4804 ushort scsi_cfg1; 4805 uchar byte; 4806 uchar tid; 4807 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 4808 ushort wdtr_able, sdtr_able, tagqng_able; 4809 uchar max_cmd[ADV_MAX_TID + 1]; 4810 4811 /* If there is already an error, don't continue. */ 4812 if (asc_dvc->err_code != 0) 4813 return ADV_ERROR; 4814 4815 /* 4816 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800. 4817 */ 4818 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) { 4819 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 4820 return ADV_ERROR; 4821 } 4822 4823 warn_code = 0; 4824 iop_base = asc_dvc->iop_base; 4825 4826 /* 4827 * Save the RISC memory BIOS region before writing the microcode. 4828 * The BIOS may already be loaded and using its RISC LRAM region 4829 * so its region must be saved and restored. 4830 * 4831 * Note: This code makes the assumption, which is currently true, 4832 * that a chip reset does not clear RISC LRAM. 4833 */ 4834 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4835 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4836 bios_mem[i]); 4837 } 4838 4839 /* 4840 * Save current per TID negotiated values. 4841 */ 4842 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 4843 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 4844 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 4845 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4846 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 4847 max_cmd[tid]); 4848 } 4849 4850 /* 4851 * RAM BIST (RAM Built-In Self Test) 4852 * 4853 * Address : I/O base + offset 0x38h register (byte). 4854 * Function: Bit 7-6(RW) : RAM mode 4855 * Normal Mode : 0x00 4856 * Pre-test Mode : 0x40 4857 * RAM Test Mode : 0x80 4858 * Bit 5 : unused 4859 * Bit 4(RO) : Done bit 4860 * Bit 3-0(RO) : Status 4861 * Host Error : 0x08 4862 * Int_RAM Error : 0x04 4863 * RISC Error : 0x02 4864 * SCSI Error : 0x01 4865 * No Error : 0x00 4866 * 4867 * Note: RAM BIST code should be put right here, before loading the 4868 * microcode and after saving the RISC memory BIOS region. 4869 */ 4870 4871 /* 4872 * LRAM Pre-test 4873 * 4874 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 4875 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 4876 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 4877 * to NORMAL_MODE, return an error too. 4878 */ 4879 for (i = 0; i < 2; i++) { 4880 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); 4881 mdelay(10); /* Wait for 10ms before reading back. */ 4882 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 4883 if ((byte & RAM_TEST_DONE) == 0 4884 || (byte & 0x0F) != PRE_TEST_VALUE) { 4885 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 4886 return ADV_ERROR; 4887 } 4888 4889 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 4890 mdelay(10); /* Wait for 10ms before reading back. */ 4891 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) 4892 != NORMAL_VALUE) { 4893 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 4894 return ADV_ERROR; 4895 } 4896 } 4897 4898 /* 4899 * LRAM Test - It takes about 1.5 ms to run through the test. 4900 * 4901 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 4902 * If Done bit not set or Status not 0, save register byte, set the 4903 * err_code, and return an error. 4904 */ 4905 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); 4906 mdelay(10); /* Wait for 10ms before checking status. */ 4907 4908 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 4909 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 4910 /* Get here if Done bit not set or Status not 0. */ 4911 asc_dvc->bist_err_code = byte; /* for BIOS display message */ 4912 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST; 4913 return ADV_ERROR; 4914 } 4915 4916 /* We need to reset back to normal mode after LRAM test passes. */ 4917 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 4918 4919 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 4920 if (err) { 4921 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 4922 fwname, err); 4923 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4924 return err; 4925 } 4926 if (fw->size < 4) { 4927 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 4928 fw->size, fwname); 4929 release_firmware(fw); 4930 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4931 return -EINVAL; 4932 } 4933 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 4934 (fw->data[1] << 8) | fw->data[0]; 4935 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 4936 fw->size - 4, ADV_38C0800_MEMSIZE, 4937 chksum); 4938 release_firmware(fw); 4939 if (asc_dvc->err_code) 4940 return ADV_ERROR; 4941 4942 /* 4943 * Restore the RISC memory BIOS region. 4944 */ 4945 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4946 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4947 bios_mem[i]); 4948 } 4949 4950 /* 4951 * Calculate and write the microcode code checksum to the microcode 4952 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 4953 */ 4954 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 4955 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 4956 code_sum = 0; 4957 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 4958 for (word = begin_addr; word < end_addr; word += 2) { 4959 code_sum += AdvReadWordAutoIncLram(iop_base); 4960 } 4961 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 4962 4963 /* 4964 * Read microcode version and date. 4965 */ 4966 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 4967 asc_dvc->cfg->mcode_date); 4968 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 4969 asc_dvc->cfg->mcode_version); 4970 4971 /* 4972 * Set the chip type to indicate the ASC38C0800. 4973 */ 4974 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800); 4975 4976 /* 4977 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 4978 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 4979 * cable detection and then we are able to read C_DET[3:0]. 4980 * 4981 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 4982 * Microcode Default Value' section below. 4983 */ 4984 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 4985 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, 4986 scsi_cfg1 | DIS_TERM_DRV); 4987 4988 /* 4989 * If the PCI Configuration Command Register "Parity Error Response 4990 * Control" Bit was clear (0), then set the microcode variable 4991 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 4992 * to ignore DMA parity errors. 4993 */ 4994 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 4995 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 4996 word |= CONTROL_FLAG_IGNORE_PERR; 4997 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 4998 } 4999 5000 /* 5001 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2] 5002 * bits for the default FIFO threshold. 5003 * 5004 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. 5005 * 5006 * For DMA Errata #4 set the BC_THRESH_ENB bit. 5007 */ 5008 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 5009 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | 5010 READ_CMD_MRM); 5011 5012 /* 5013 * Microcode operating variables for WDTR, SDTR, and command tag 5014 * queuing will be set in sdev_configure() based on what a 5015 * device reports it is capable of in Inquiry byte 7. 5016 * 5017 * If SCSI Bus Resets have been disabled, then directly set 5018 * SDTR and WDTR from the EEPROM configuration. This will allow 5019 * the BIOS and warm boot to work without a SCSI bus hang on 5020 * the Inquiry caused by host and target mismatched DTR values. 5021 * Without the SCSI Bus Reset, before an Inquiry a device can't 5022 * be assumed to be in Asynchronous, Narrow mode. 5023 */ 5024 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 5025 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 5026 asc_dvc->wdtr_able); 5027 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 5028 asc_dvc->sdtr_able); 5029 } 5030 5031 /* 5032 * Set microcode operating variables for DISC and SDTR_SPEED1, 5033 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 5034 * configuration values. 5035 * 5036 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 5037 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 5038 * without determining here whether the device supports SDTR. 5039 */ 5040 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 5041 asc_dvc->cfg->disc_enable); 5042 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1); 5043 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2); 5044 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3); 5045 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4); 5046 5047 /* 5048 * Set SCSI_CFG0 Microcode Default Value. 5049 * 5050 * The microcode will set the SCSI_CFG0 register using this value 5051 * after it is started below. 5052 */ 5053 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 5054 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 5055 asc_dvc->chip_scsi_id); 5056 5057 /* 5058 * Determine SCSI_CFG1 Microcode Default Value. 5059 * 5060 * The microcode will set the SCSI_CFG1 register using this value 5061 * after it is started below. 5062 */ 5063 5064 /* Read current SCSI_CFG1 Register value. */ 5065 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5066 5067 /* 5068 * If the internal narrow cable is reversed all of the SCSI_CTRL 5069 * register signals will be set. Check for and return an error if 5070 * this condition is found. 5071 */ 5072 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 5073 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 5074 return ADV_ERROR; 5075 } 5076 5077 /* 5078 * All kind of combinations of devices attached to one of four 5079 * connectors are acceptable except HVD device attached. For example, 5080 * LVD device can be attached to SE connector while SE device attached 5081 * to LVD connector. If LVD device attached to SE connector, it only 5082 * runs up to Ultra speed. 5083 * 5084 * If an HVD device is attached to one of LVD connectors, return an 5085 * error. However, there is no way to detect HVD device attached to 5086 * SE connectors. 5087 */ 5088 if (scsi_cfg1 & HVD) { 5089 asc_dvc->err_code = ASC_IERR_HVD_DEVICE; 5090 return ADV_ERROR; 5091 } 5092 5093 /* 5094 * If either SE or LVD automatic termination control is enabled, then 5095 * set the termination value based on a table listed in a_condor.h. 5096 * 5097 * If manual termination was specified with an EEPROM setting then 5098 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready 5099 * to be 'ored' into SCSI_CFG1. 5100 */ 5101 if ((asc_dvc->cfg->termination & TERM_SE) == 0) { 5102 /* SE automatic termination control is enabled. */ 5103 switch (scsi_cfg1 & C_DET_SE) { 5104 /* TERM_SE_HI: on, TERM_SE_LO: on */ 5105 case 0x1: 5106 case 0x2: 5107 case 0x3: 5108 asc_dvc->cfg->termination |= TERM_SE; 5109 break; 5110 5111 /* TERM_SE_HI: on, TERM_SE_LO: off */ 5112 case 0x0: 5113 asc_dvc->cfg->termination |= TERM_SE_HI; 5114 break; 5115 } 5116 } 5117 5118 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) { 5119 /* LVD automatic termination control is enabled. */ 5120 switch (scsi_cfg1 & C_DET_LVD) { 5121 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 5122 case 0x4: 5123 case 0x8: 5124 case 0xC: 5125 asc_dvc->cfg->termination |= TERM_LVD; 5126 break; 5127 5128 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 5129 case 0x0: 5130 break; 5131 } 5132 } 5133 5134 /* 5135 * Clear any set TERM_SE and TERM_LVD bits. 5136 */ 5137 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD); 5138 5139 /* 5140 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 5141 */ 5142 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0); 5143 5144 /* 5145 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE 5146 * bits and set possibly modified termination control bits in the 5147 * Microcode SCSI_CFG1 Register Value. 5148 */ 5149 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE); 5150 5151 /* 5152 * Set SCSI_CFG1 Microcode Default Value 5153 * 5154 * Set possibly modified termination control and reset DIS_TERM_DRV 5155 * bits in the Microcode SCSI_CFG1 Register Value. 5156 * 5157 * The microcode will set the SCSI_CFG1 register using this value 5158 * after it is started below. 5159 */ 5160 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 5161 5162 /* 5163 * Set MEM_CFG Microcode Default Value 5164 * 5165 * The microcode will set the MEM_CFG register using this value 5166 * after it is started below. 5167 * 5168 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 5169 * are defined. 5170 * 5171 * ASC-38C0800 has 16KB internal memory. 5172 */ 5173 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 5174 BIOS_EN | RAM_SZ_16KB); 5175 5176 /* 5177 * Set SEL_MASK Microcode Default Value 5178 * 5179 * The microcode will set the SEL_MASK register using this value 5180 * after it is started below. 5181 */ 5182 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 5183 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 5184 5185 AdvBuildCarrierFreelist(asc_dvc); 5186 5187 /* 5188 * Set-up the Host->RISC Initiator Command Queue (ICQ). 5189 */ 5190 5191 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc); 5192 if (!asc_dvc->icq_sp) { 5193 ASC_DBG(0, "Failed to get ICQ carrier\n"); 5194 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5195 return ADV_ERROR; 5196 } 5197 5198 /* 5199 * Set RISC ICQ physical address start value. 5200 * carr_pa is LE, must be native before write 5201 */ 5202 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 5203 5204 /* 5205 * Set-up the RISC->Host Initiator Response Queue (IRQ). 5206 */ 5207 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc); 5208 if (!asc_dvc->irq_sp) { 5209 ASC_DBG(0, "Failed to get IRQ carrier\n"); 5210 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5211 return ADV_ERROR; 5212 } 5213 5214 /* 5215 * Set RISC IRQ physical address start value. 5216 * 5217 * carr_pa is LE, must be native before write * 5218 */ 5219 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 5220 asc_dvc->carr_pending_cnt = 0; 5221 5222 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 5223 (ADV_INTR_ENABLE_HOST_INTR | 5224 ADV_INTR_ENABLE_GLOBAL_INTR)); 5225 5226 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 5227 AdvWriteWordRegister(iop_base, IOPW_PC, word); 5228 5229 /* finally, finally, gentlemen, start your engine */ 5230 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 5231 5232 /* 5233 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 5234 * Resets should be performed. The RISC has to be running 5235 * to issue a SCSI Bus Reset. 5236 */ 5237 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 5238 /* 5239 * If the BIOS Signature is present in memory, restore the 5240 * BIOS Handshake Configuration Table and do not perform 5241 * a SCSI Bus Reset. 5242 */ 5243 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 5244 0x55AA) { 5245 /* 5246 * Restore per TID negotiated values. 5247 */ 5248 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5249 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5250 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 5251 tagqng_able); 5252 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5253 AdvWriteByteLram(iop_base, 5254 ASC_MC_NUMBER_OF_MAX_CMD + tid, 5255 max_cmd[tid]); 5256 } 5257 } else { 5258 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 5259 warn_code = ASC_WARN_BUSRESET_ERROR; 5260 } 5261 } 5262 } 5263 5264 return warn_code; 5265 } 5266 5267 /* 5268 * Initialize the ASC-38C1600. 5269 * 5270 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 5271 * 5272 * For a non-fatal error return a warning code. If there are no warnings 5273 * then 0 is returned. 5274 * 5275 * Needed after initialization for error recovery. 5276 */ 5277 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc) 5278 { 5279 const struct firmware *fw; 5280 const char fwname[] = "advansys/38C1600.bin"; 5281 AdvPortAddr iop_base; 5282 ushort warn_code; 5283 int begin_addr; 5284 int end_addr; 5285 ushort code_sum; 5286 long word; 5287 int i; 5288 int err; 5289 unsigned long chksum; 5290 ushort scsi_cfg1; 5291 uchar byte; 5292 uchar tid; 5293 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 5294 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able; 5295 uchar max_cmd[ASC_MAX_TID + 1]; 5296 5297 /* If there is already an error, don't continue. */ 5298 if (asc_dvc->err_code != 0) { 5299 return ADV_ERROR; 5300 } 5301 5302 /* 5303 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600. 5304 */ 5305 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) { 5306 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 5307 return ADV_ERROR; 5308 } 5309 5310 warn_code = 0; 5311 iop_base = asc_dvc->iop_base; 5312 5313 /* 5314 * Save the RISC memory BIOS region before writing the microcode. 5315 * The BIOS may already be loaded and using its RISC LRAM region 5316 * so its region must be saved and restored. 5317 * 5318 * Note: This code makes the assumption, which is currently true, 5319 * that a chip reset does not clear RISC LRAM. 5320 */ 5321 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 5322 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 5323 bios_mem[i]); 5324 } 5325 5326 /* 5327 * Save current per TID negotiated values. 5328 */ 5329 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5330 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5331 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5332 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 5333 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 5334 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 5335 max_cmd[tid]); 5336 } 5337 5338 /* 5339 * RAM BIST (Built-In Self Test) 5340 * 5341 * Address : I/O base + offset 0x38h register (byte). 5342 * Function: Bit 7-6(RW) : RAM mode 5343 * Normal Mode : 0x00 5344 * Pre-test Mode : 0x40 5345 * RAM Test Mode : 0x80 5346 * Bit 5 : unused 5347 * Bit 4(RO) : Done bit 5348 * Bit 3-0(RO) : Status 5349 * Host Error : 0x08 5350 * Int_RAM Error : 0x04 5351 * RISC Error : 0x02 5352 * SCSI Error : 0x01 5353 * No Error : 0x00 5354 * 5355 * Note: RAM BIST code should be put right here, before loading the 5356 * microcode and after saving the RISC memory BIOS region. 5357 */ 5358 5359 /* 5360 * LRAM Pre-test 5361 * 5362 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 5363 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 5364 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 5365 * to NORMAL_MODE, return an error too. 5366 */ 5367 for (i = 0; i < 2; i++) { 5368 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); 5369 mdelay(10); /* Wait for 10ms before reading back. */ 5370 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 5371 if ((byte & RAM_TEST_DONE) == 0 5372 || (byte & 0x0F) != PRE_TEST_VALUE) { 5373 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 5374 return ADV_ERROR; 5375 } 5376 5377 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 5378 mdelay(10); /* Wait for 10ms before reading back. */ 5379 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) 5380 != NORMAL_VALUE) { 5381 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 5382 return ADV_ERROR; 5383 } 5384 } 5385 5386 /* 5387 * LRAM Test - It takes about 1.5 ms to run through the test. 5388 * 5389 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 5390 * If Done bit not set or Status not 0, save register byte, set the 5391 * err_code, and return an error. 5392 */ 5393 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); 5394 mdelay(10); /* Wait for 10ms before checking status. */ 5395 5396 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 5397 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 5398 /* Get here if Done bit not set or Status not 0. */ 5399 asc_dvc->bist_err_code = byte; /* for BIOS display message */ 5400 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST; 5401 return ADV_ERROR; 5402 } 5403 5404 /* We need to reset back to normal mode after LRAM test passes. */ 5405 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 5406 5407 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 5408 if (err) { 5409 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 5410 fwname, err); 5411 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 5412 return err; 5413 } 5414 if (fw->size < 4) { 5415 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 5416 fw->size, fwname); 5417 release_firmware(fw); 5418 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 5419 return -EINVAL; 5420 } 5421 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 5422 (fw->data[1] << 8) | fw->data[0]; 5423 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 5424 fw->size - 4, ADV_38C1600_MEMSIZE, 5425 chksum); 5426 release_firmware(fw); 5427 if (asc_dvc->err_code) 5428 return ADV_ERROR; 5429 5430 /* 5431 * Restore the RISC memory BIOS region. 5432 */ 5433 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 5434 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 5435 bios_mem[i]); 5436 } 5437 5438 /* 5439 * Calculate and write the microcode code checksum to the microcode 5440 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 5441 */ 5442 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 5443 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 5444 code_sum = 0; 5445 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 5446 for (word = begin_addr; word < end_addr; word += 2) { 5447 code_sum += AdvReadWordAutoIncLram(iop_base); 5448 } 5449 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 5450 5451 /* 5452 * Read microcode version and date. 5453 */ 5454 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 5455 asc_dvc->cfg->mcode_date); 5456 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 5457 asc_dvc->cfg->mcode_version); 5458 5459 /* 5460 * Set the chip type to indicate the ASC38C1600. 5461 */ 5462 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600); 5463 5464 /* 5465 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 5466 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 5467 * cable detection and then we are able to read C_DET[3:0]. 5468 * 5469 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 5470 * Microcode Default Value' section below. 5471 */ 5472 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5473 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, 5474 scsi_cfg1 | DIS_TERM_DRV); 5475 5476 /* 5477 * If the PCI Configuration Command Register "Parity Error Response 5478 * Control" Bit was clear (0), then set the microcode variable 5479 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 5480 * to ignore DMA parity errors. 5481 */ 5482 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 5483 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5484 word |= CONTROL_FLAG_IGNORE_PERR; 5485 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5486 } 5487 5488 /* 5489 * If the BIOS control flag AIPP (Asynchronous Information 5490 * Phase Protection) disable bit is not set, then set the firmware 5491 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable 5492 * AIPP checking and encoding. 5493 */ 5494 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 5495 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5496 word |= CONTROL_FLAG_ENABLE_AIPP; 5497 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5498 } 5499 5500 /* 5501 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4], 5502 * and START_CTL_TH [3:2]. 5503 */ 5504 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 5505 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 5506 5507 /* 5508 * Microcode operating variables for WDTR, SDTR, and command tag 5509 * queuing will be set in sdev_configure() based on what a 5510 * device reports it is capable of in Inquiry byte 7. 5511 * 5512 * If SCSI Bus Resets have been disabled, then directly set 5513 * SDTR and WDTR from the EEPROM configuration. This will allow 5514 * the BIOS and warm boot to work without a SCSI bus hang on 5515 * the Inquiry caused by host and target mismatched DTR values. 5516 * Without the SCSI Bus Reset, before an Inquiry a device can't 5517 * be assumed to be in Asynchronous, Narrow mode. 5518 */ 5519 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 5520 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 5521 asc_dvc->wdtr_able); 5522 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 5523 asc_dvc->sdtr_able); 5524 } 5525 5526 /* 5527 * Set microcode operating variables for DISC and SDTR_SPEED1, 5528 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 5529 * configuration values. 5530 * 5531 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 5532 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 5533 * without determining here whether the device supports SDTR. 5534 */ 5535 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 5536 asc_dvc->cfg->disc_enable); 5537 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1); 5538 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2); 5539 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3); 5540 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4); 5541 5542 /* 5543 * Set SCSI_CFG0 Microcode Default Value. 5544 * 5545 * The microcode will set the SCSI_CFG0 register using this value 5546 * after it is started below. 5547 */ 5548 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 5549 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 5550 asc_dvc->chip_scsi_id); 5551 5552 /* 5553 * Calculate SCSI_CFG1 Microcode Default Value. 5554 * 5555 * The microcode will set the SCSI_CFG1 register using this value 5556 * after it is started below. 5557 * 5558 * Each ASC-38C1600 function has only two cable detect bits. 5559 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 5560 */ 5561 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5562 5563 /* 5564 * If the cable is reversed all of the SCSI_CTRL register signals 5565 * will be set. Check for and return an error if this condition is 5566 * found. 5567 */ 5568 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 5569 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 5570 return ADV_ERROR; 5571 } 5572 5573 /* 5574 * Each ASC-38C1600 function has two connectors. Only an HVD device 5575 * can not be connected to either connector. An LVD device or SE device 5576 * may be connected to either connecor. If an SE device is connected, 5577 * then at most Ultra speed (20 Mhz) can be used on both connectors. 5578 * 5579 * If an HVD device is attached, return an error. 5580 */ 5581 if (scsi_cfg1 & HVD) { 5582 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE; 5583 return ADV_ERROR; 5584 } 5585 5586 /* 5587 * Each function in the ASC-38C1600 uses only the SE cable detect and 5588 * termination because there are two connectors for each function. Each 5589 * function may use either LVD or SE mode. Corresponding the SE automatic 5590 * termination control EEPROM bits are used for each function. Each 5591 * function has its own EEPROM. If SE automatic control is enabled for 5592 * the function, then set the termination value based on a table listed 5593 * in a_condor.h. 5594 * 5595 * If manual termination is specified in the EEPROM for the function, 5596 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is 5597 * ready to be 'ored' into SCSI_CFG1. 5598 */ 5599 if ((asc_dvc->cfg->termination & TERM_SE) == 0) { 5600 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc); 5601 /* SE automatic termination control is enabled. */ 5602 switch (scsi_cfg1 & C_DET_SE) { 5603 /* TERM_SE_HI: on, TERM_SE_LO: on */ 5604 case 0x1: 5605 case 0x2: 5606 case 0x3: 5607 asc_dvc->cfg->termination |= TERM_SE; 5608 break; 5609 5610 case 0x0: 5611 if (PCI_FUNC(pdev->devfn) == 0) { 5612 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 5613 } else { 5614 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 5615 asc_dvc->cfg->termination |= TERM_SE_HI; 5616 } 5617 break; 5618 } 5619 } 5620 5621 /* 5622 * Clear any set TERM_SE bits. 5623 */ 5624 scsi_cfg1 &= ~TERM_SE; 5625 5626 /* 5627 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 5628 */ 5629 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE); 5630 5631 /* 5632 * Clear Big Endian and Terminator Polarity bits and set possibly 5633 * modified termination control bits in the Microcode SCSI_CFG1 5634 * Register Value. 5635 * 5636 * Big Endian bit is not used even on big endian machines. 5637 */ 5638 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL); 5639 5640 /* 5641 * Set SCSI_CFG1 Microcode Default Value 5642 * 5643 * Set possibly modified termination control bits in the Microcode 5644 * SCSI_CFG1 Register Value. 5645 * 5646 * The microcode will set the SCSI_CFG1 register using this value 5647 * after it is started below. 5648 */ 5649 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 5650 5651 /* 5652 * Set MEM_CFG Microcode Default Value 5653 * 5654 * The microcode will set the MEM_CFG register using this value 5655 * after it is started below. 5656 * 5657 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 5658 * are defined. 5659 * 5660 * ASC-38C1600 has 32KB internal memory. 5661 * 5662 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come 5663 * out a special 16K Adv Library and Microcode version. After the issue 5664 * resolved, we should turn back to the 32K support. Both a_condor.h and 5665 * mcode.sas files also need to be updated. 5666 * 5667 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 5668 * BIOS_EN | RAM_SZ_32KB); 5669 */ 5670 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 5671 BIOS_EN | RAM_SZ_16KB); 5672 5673 /* 5674 * Set SEL_MASK Microcode Default Value 5675 * 5676 * The microcode will set the SEL_MASK register using this value 5677 * after it is started below. 5678 */ 5679 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 5680 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 5681 5682 AdvBuildCarrierFreelist(asc_dvc); 5683 5684 /* 5685 * Set-up the Host->RISC Initiator Command Queue (ICQ). 5686 */ 5687 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc); 5688 if (!asc_dvc->icq_sp) { 5689 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5690 return ADV_ERROR; 5691 } 5692 5693 /* 5694 * Set RISC ICQ physical address start value. Initialize the 5695 * COMMA register to the same value otherwise the RISC will 5696 * prematurely detect a command is available. 5697 */ 5698 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 5699 AdvWriteDWordRegister(iop_base, IOPDW_COMMA, 5700 le32_to_cpu(asc_dvc->icq_sp->carr_pa)); 5701 5702 /* 5703 * Set-up the RISC->Host Initiator Response Queue (IRQ). 5704 */ 5705 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc); 5706 if (!asc_dvc->irq_sp) { 5707 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5708 return ADV_ERROR; 5709 } 5710 5711 /* 5712 * Set RISC IRQ physical address start value. 5713 */ 5714 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 5715 asc_dvc->carr_pending_cnt = 0; 5716 5717 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 5718 (ADV_INTR_ENABLE_HOST_INTR | 5719 ADV_INTR_ENABLE_GLOBAL_INTR)); 5720 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 5721 AdvWriteWordRegister(iop_base, IOPW_PC, word); 5722 5723 /* finally, finally, gentlemen, start your engine */ 5724 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 5725 5726 /* 5727 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 5728 * Resets should be performed. The RISC has to be running 5729 * to issue a SCSI Bus Reset. 5730 */ 5731 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 5732 /* 5733 * If the BIOS Signature is present in memory, restore the 5734 * per TID microcode operating variables. 5735 */ 5736 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 5737 0x55AA) { 5738 /* 5739 * Restore per TID negotiated values. 5740 */ 5741 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5742 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5743 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5744 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 5745 tagqng_able); 5746 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 5747 AdvWriteByteLram(iop_base, 5748 ASC_MC_NUMBER_OF_MAX_CMD + tid, 5749 max_cmd[tid]); 5750 } 5751 } else { 5752 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 5753 warn_code = ASC_WARN_BUSRESET_ERROR; 5754 } 5755 } 5756 } 5757 5758 return warn_code; 5759 } 5760 5761 /* 5762 * Reset chip and SCSI Bus. 5763 * 5764 * Return Value: 5765 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 5766 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 5767 */ 5768 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc) 5769 { 5770 int status; 5771 ushort wdtr_able, sdtr_able, tagqng_able; 5772 ushort ppr_able = 0; 5773 uchar tid, max_cmd[ADV_MAX_TID + 1]; 5774 AdvPortAddr iop_base; 5775 ushort bios_sig; 5776 5777 iop_base = asc_dvc->iop_base; 5778 5779 /* 5780 * Save current per TID negotiated values. 5781 */ 5782 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5783 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5784 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 5785 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5786 } 5787 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 5788 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5789 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 5790 max_cmd[tid]); 5791 } 5792 5793 /* 5794 * Force the AdvInitAsc3550/38C0800Driver() function to 5795 * perform a SCSI Bus Reset by clearing the BIOS signature word. 5796 * The initialization functions assumes a SCSI Bus Reset is not 5797 * needed if the BIOS signature word is present. 5798 */ 5799 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig); 5800 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0); 5801 5802 /* 5803 * Stop chip and reset it. 5804 */ 5805 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP); 5806 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET); 5807 mdelay(100); 5808 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 5809 ADV_CTRL_REG_CMD_WR_IO_REG); 5810 5811 /* 5812 * Reset Adv Library error code, if any, and try 5813 * re-initializing the chip. 5814 */ 5815 asc_dvc->err_code = 0; 5816 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 5817 status = AdvInitAsc38C1600Driver(asc_dvc); 5818 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 5819 status = AdvInitAsc38C0800Driver(asc_dvc); 5820 } else { 5821 status = AdvInitAsc3550Driver(asc_dvc); 5822 } 5823 5824 /* Translate initialization return value to status value. */ 5825 if (status == 0) { 5826 status = ADV_TRUE; 5827 } else { 5828 status = ADV_FALSE; 5829 } 5830 5831 /* 5832 * Restore the BIOS signature word. 5833 */ 5834 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig); 5835 5836 /* 5837 * Restore per TID negotiated values. 5838 */ 5839 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5840 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5841 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 5842 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5843 } 5844 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 5845 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5846 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 5847 max_cmd[tid]); 5848 } 5849 5850 return status; 5851 } 5852 5853 /* 5854 * adv_async_callback() - Adv Library asynchronous event callback function. 5855 */ 5856 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code) 5857 { 5858 switch (code) { 5859 case ADV_ASYNC_SCSI_BUS_RESET_DET: 5860 /* 5861 * The firmware detected a SCSI Bus reset. 5862 */ 5863 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n"); 5864 break; 5865 5866 case ADV_ASYNC_RDMA_FAILURE: 5867 /* 5868 * Handle RDMA failure by resetting the SCSI Bus and 5869 * possibly the chip if it is unresponsive. Log the error 5870 * with a unique code. 5871 */ 5872 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n"); 5873 AdvResetChipAndSB(adv_dvc_varp); 5874 break; 5875 5876 case ADV_HOST_SCSI_BUS_RESET: 5877 /* 5878 * Host generated SCSI bus reset occurred. 5879 */ 5880 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n"); 5881 break; 5882 5883 default: 5884 ASC_DBG(0, "unknown code 0x%x\n", code); 5885 break; 5886 } 5887 } 5888 5889 /* 5890 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR(). 5891 * 5892 * Callback function for the Wide SCSI Adv Library. 5893 */ 5894 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp) 5895 { 5896 struct asc_board *boardp = adv_dvc_varp->drv_ptr; 5897 adv_req_t *reqp; 5898 adv_sgblk_t *sgblkp; 5899 struct scsi_cmnd *scp; 5900 u32 resid_cnt; 5901 dma_addr_t sense_addr; 5902 5903 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n", 5904 adv_dvc_varp, scsiqp); 5905 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp); 5906 5907 /* 5908 * Get the adv_req_t structure for the command that has been 5909 * completed. The adv_req_t structure actually contains the 5910 * completed ADV_SCSI_REQ_Q structure. 5911 */ 5912 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag); 5913 5914 ASC_DBG(1, "scp 0x%p\n", scp); 5915 if (scp == NULL) { 5916 ASC_PRINT 5917 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n"); 5918 return; 5919 } 5920 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len); 5921 5922 reqp = (adv_req_t *)scp->host_scribble; 5923 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp); 5924 if (reqp == NULL) { 5925 ASC_PRINT("adv_isr_callback: reqp is NULL\n"); 5926 return; 5927 } 5928 /* 5929 * Remove backreferences to avoid duplicate 5930 * command completions. 5931 */ 5932 scp->host_scribble = NULL; 5933 reqp->cmndp = NULL; 5934 5935 ASC_STATS(boardp->shost, callback); 5936 ASC_DBG(1, "shost 0x%p\n", boardp->shost); 5937 5938 sense_addr = le32_to_cpu(scsiqp->sense_addr); 5939 dma_unmap_single(boardp->dev, sense_addr, 5940 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 5941 5942 /* 5943 * 'done_status' contains the command's ending status. 5944 */ 5945 scp->result = 0; 5946 switch (scsiqp->done_status) { 5947 case QD_NO_ERROR: 5948 ASC_DBG(2, "QD_NO_ERROR\n"); 5949 5950 /* 5951 * Check for an underrun condition. 5952 * 5953 * If there was no error and an underrun condition, then 5954 * then return the number of underrun bytes. 5955 */ 5956 resid_cnt = le32_to_cpu(scsiqp->data_cnt); 5957 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 && 5958 resid_cnt <= scsi_bufflen(scp)) { 5959 ASC_DBG(1, "underrun condition %lu bytes\n", 5960 (ulong)resid_cnt); 5961 scsi_set_resid(scp, resid_cnt); 5962 } 5963 break; 5964 5965 case QD_WITH_ERROR: 5966 ASC_DBG(2, "QD_WITH_ERROR\n"); 5967 switch (scsiqp->host_status) { 5968 case QHSTA_NO_ERROR: 5969 set_status_byte(scp, scsiqp->scsi_status); 5970 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) { 5971 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n"); 5972 ASC_DBG_PRT_SENSE(2, scp->sense_buffer, 5973 SCSI_SENSE_BUFFERSIZE); 5974 } 5975 break; 5976 5977 default: 5978 /* Some other QHSTA error occurred. */ 5979 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status); 5980 set_host_byte(scp, DID_BAD_TARGET); 5981 break; 5982 } 5983 break; 5984 5985 case QD_ABORTED_BY_HOST: 5986 ASC_DBG(1, "QD_ABORTED_BY_HOST\n"); 5987 set_status_byte(scp, scsiqp->scsi_status); 5988 set_host_byte(scp, DID_ABORT); 5989 break; 5990 5991 default: 5992 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status); 5993 set_status_byte(scp, scsiqp->scsi_status); 5994 set_host_byte(scp, DID_ERROR); 5995 break; 5996 } 5997 5998 /* 5999 * If the 'init_tidmask' bit isn't already set for the target and the 6000 * current request finished normally, then set the bit for the target 6001 * to indicate that a device is present. 6002 */ 6003 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 && 6004 scsiqp->done_status == QD_NO_ERROR && 6005 scsiqp->host_status == QHSTA_NO_ERROR) { 6006 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id); 6007 } 6008 6009 asc_scsi_done(scp); 6010 6011 /* 6012 * Free all 'adv_sgblk_t' structures allocated for the request. 6013 */ 6014 while ((sgblkp = reqp->sgblkp) != NULL) { 6015 /* Remove 'sgblkp' from the request list. */ 6016 reqp->sgblkp = sgblkp->next_sgblkp; 6017 6018 dma_pool_free(boardp->adv_sgblk_pool, sgblkp, 6019 sgblkp->sg_addr); 6020 } 6021 6022 ASC_DBG(1, "done\n"); 6023 } 6024 6025 /* 6026 * Adv Library Interrupt Service Routine 6027 * 6028 * This function is called by a driver's interrupt service routine. 6029 * The function disables and re-enables interrupts. 6030 * 6031 * When a microcode idle command is completed, the ADV_DVC_VAR 6032 * 'idle_cmd_done' field is set to ADV_TRUE. 6033 * 6034 * Note: AdvISR() can be called when interrupts are disabled or even 6035 * when there is no hardware interrupt condition present. It will 6036 * always check for completed idle commands and microcode requests. 6037 * This is an important feature that shouldn't be changed because it 6038 * allows commands to be completed from polling mode loops. 6039 * 6040 * Return: 6041 * ADV_TRUE(1) - interrupt was pending 6042 * ADV_FALSE(0) - no interrupt was pending 6043 */ 6044 static int AdvISR(ADV_DVC_VAR *asc_dvc) 6045 { 6046 AdvPortAddr iop_base; 6047 uchar int_stat; 6048 ADV_CARR_T *free_carrp; 6049 __le32 irq_next_vpa; 6050 ADV_SCSI_REQ_Q *scsiq; 6051 adv_req_t *reqp; 6052 6053 iop_base = asc_dvc->iop_base; 6054 6055 /* Reading the register clears the interrupt. */ 6056 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG); 6057 6058 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB | 6059 ADV_INTR_STATUS_INTRC)) == 0) { 6060 return ADV_FALSE; 6061 } 6062 6063 /* 6064 * Notify the driver of an asynchronous microcode condition by 6065 * calling the adv_async_callback function. The function 6066 * is passed the microcode ASC_MC_INTRB_CODE byte value. 6067 */ 6068 if (int_stat & ADV_INTR_STATUS_INTRB) { 6069 uchar intrb_code; 6070 6071 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code); 6072 6073 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 || 6074 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 6075 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 6076 asc_dvc->carr_pending_cnt != 0) { 6077 AdvWriteByteRegister(iop_base, IOPB_TICKLE, 6078 ADV_TICKLE_A); 6079 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 6080 AdvWriteByteRegister(iop_base, 6081 IOPB_TICKLE, 6082 ADV_TICKLE_NOP); 6083 } 6084 } 6085 } 6086 6087 adv_async_callback(asc_dvc, intrb_code); 6088 } 6089 6090 /* 6091 * Check if the IRQ stopper carrier contains a completed request. 6092 */ 6093 while (((irq_next_vpa = 6094 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ADV_RQ_DONE) != 0) { 6095 /* 6096 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure. 6097 * The RISC will have set 'areq_vpa' to a virtual address. 6098 * 6099 * The firmware will have copied the ADV_SCSI_REQ_Q.scsiq_ptr 6100 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion 6101 * below complements the conversion of ADV_SCSI_REQ_Q.scsiq_ptr' 6102 * in AdvExeScsiQueue(). 6103 */ 6104 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa); 6105 ASC_DBG(1, "irq_sp %p areq_vpa %u\n", 6106 asc_dvc->irq_sp, pa_offset); 6107 reqp = adv_get_reqp(asc_dvc, pa_offset); 6108 scsiq = &reqp->scsi_req_q; 6109 6110 /* 6111 * Request finished with good status and the queue was not 6112 * DMAed to host memory by the firmware. Set all status fields 6113 * to indicate good status. 6114 */ 6115 if ((irq_next_vpa & ADV_RQ_GOOD) != 0) { 6116 scsiq->done_status = QD_NO_ERROR; 6117 scsiq->host_status = scsiq->scsi_status = 0; 6118 scsiq->data_cnt = 0L; 6119 } 6120 6121 /* 6122 * Advance the stopper pointer to the next carrier 6123 * ignoring the lower four bits. Free the previous 6124 * stopper carrier. 6125 */ 6126 free_carrp = asc_dvc->irq_sp; 6127 asc_dvc->irq_sp = adv_get_carrier(asc_dvc, 6128 ADV_GET_CARRP(irq_next_vpa)); 6129 6130 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va; 6131 asc_dvc->carr_freelist = free_carrp; 6132 asc_dvc->carr_pending_cnt--; 6133 6134 /* 6135 * Clear request microcode control flag. 6136 */ 6137 scsiq->cntl = 0; 6138 6139 /* 6140 * Notify the driver of the completed request by passing 6141 * the ADV_SCSI_REQ_Q pointer to its callback function. 6142 */ 6143 adv_isr_callback(asc_dvc, scsiq); 6144 /* 6145 * Note: After the driver callback function is called, 'scsiq' 6146 * can no longer be referenced. 6147 * 6148 * Fall through and continue processing other completed 6149 * requests... 6150 */ 6151 } 6152 return ADV_TRUE; 6153 } 6154 6155 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code) 6156 { 6157 if (asc_dvc->err_code == 0) { 6158 asc_dvc->err_code = err_code; 6159 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W, 6160 err_code); 6161 } 6162 return err_code; 6163 } 6164 6165 static void AscAckInterrupt(PortAddr iop_base) 6166 { 6167 uchar host_flag; 6168 uchar risc_flag; 6169 ushort loop; 6170 6171 loop = 0; 6172 do { 6173 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B); 6174 if (loop++ > 0x7FFF) { 6175 break; 6176 } 6177 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 6178 host_flag = 6179 AscReadLramByte(iop_base, 6180 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT); 6181 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, 6182 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT)); 6183 AscSetChipStatus(iop_base, CIW_INT_ACK); 6184 loop = 0; 6185 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) { 6186 AscSetChipStatus(iop_base, CIW_INT_ACK); 6187 if (loop++ > 3) { 6188 break; 6189 } 6190 } 6191 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); 6192 } 6193 6194 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time) 6195 { 6196 const uchar *period_table; 6197 int max_index; 6198 int min_index; 6199 int i; 6200 6201 period_table = asc_dvc->sdtr_period_tbl; 6202 max_index = (int)asc_dvc->max_sdtr_index; 6203 min_index = (int)asc_dvc->min_sdtr_index; 6204 if ((syn_time <= period_table[max_index])) { 6205 for (i = min_index; i < (max_index - 1); i++) { 6206 if (syn_time <= period_table[i]) { 6207 return (uchar)i; 6208 } 6209 } 6210 return (uchar)max_index; 6211 } else { 6212 return (uchar)(max_index + 1); 6213 } 6214 } 6215 6216 static uchar 6217 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset) 6218 { 6219 PortAddr iop_base = asc_dvc->iop_base; 6220 uchar sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period); 6221 EXT_MSG sdtr_buf = { 6222 .msg_type = EXTENDED_MESSAGE, 6223 .msg_len = MS_SDTR_LEN, 6224 .msg_req = EXTENDED_SDTR, 6225 .xfer_period = sdtr_period, 6226 .req_ack_offset = sdtr_offset, 6227 }; 6228 sdtr_offset &= ASC_SYN_MAX_OFFSET; 6229 6230 if (sdtr_period_index <= asc_dvc->max_sdtr_index) { 6231 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG, 6232 (uchar *)&sdtr_buf, 6233 sizeof(EXT_MSG) >> 1); 6234 return ((sdtr_period_index << 4) | sdtr_offset); 6235 } else { 6236 sdtr_buf.req_ack_offset = 0; 6237 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG, 6238 (uchar *)&sdtr_buf, 6239 sizeof(EXT_MSG) >> 1); 6240 return 0; 6241 } 6242 } 6243 6244 static uchar 6245 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset) 6246 { 6247 uchar byte; 6248 uchar sdtr_period_ix; 6249 6250 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period); 6251 if (sdtr_period_ix > asc_dvc->max_sdtr_index) 6252 return 0xFF; 6253 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 6254 return byte; 6255 } 6256 6257 static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data) 6258 { 6259 ASC_SCSI_BIT_ID_TYPE org_id; 6260 int i; 6261 bool sta = true; 6262 6263 AscSetBank(iop_base, 1); 6264 org_id = AscReadChipDvcID(iop_base); 6265 for (i = 0; i <= ASC_MAX_TID; i++) { 6266 if (org_id == (0x01 << i)) 6267 break; 6268 } 6269 org_id = (ASC_SCSI_BIT_ID_TYPE) i; 6270 AscWriteChipDvcID(iop_base, id); 6271 if (AscReadChipDvcID(iop_base) == (0x01 << id)) { 6272 AscSetBank(iop_base, 0); 6273 AscSetChipSyn(iop_base, sdtr_data); 6274 if (AscGetChipSyn(iop_base) != sdtr_data) { 6275 sta = false; 6276 } 6277 } else { 6278 sta = false; 6279 } 6280 AscSetBank(iop_base, 1); 6281 AscWriteChipDvcID(iop_base, org_id); 6282 AscSetBank(iop_base, 0); 6283 return (sta); 6284 } 6285 6286 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no) 6287 { 6288 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data); 6289 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data); 6290 } 6291 6292 static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc) 6293 { 6294 EXT_MSG ext_msg; 6295 EXT_MSG out_msg; 6296 ushort halt_q_addr; 6297 bool sdtr_accept; 6298 ushort int_halt_code; 6299 ASC_SCSI_BIT_ID_TYPE scsi_busy; 6300 ASC_SCSI_BIT_ID_TYPE target_id; 6301 PortAddr iop_base; 6302 uchar tag_code; 6303 uchar q_status; 6304 uchar halt_qp; 6305 uchar sdtr_data; 6306 uchar target_ix; 6307 uchar q_cntl, tid_no; 6308 uchar cur_dvc_qng; 6309 uchar asyn_sdtr; 6310 uchar scsi_status; 6311 struct asc_board *boardp; 6312 6313 BUG_ON(!asc_dvc->drv_ptr); 6314 boardp = asc_dvc->drv_ptr; 6315 6316 iop_base = asc_dvc->iop_base; 6317 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W); 6318 6319 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B); 6320 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 6321 target_ix = AscReadLramByte(iop_base, 6322 (ushort)(halt_q_addr + 6323 (ushort)ASC_SCSIQ_B_TARGET_IX)); 6324 q_cntl = AscReadLramByte(iop_base, 6325 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL)); 6326 tid_no = ASC_TIX_TO_TID(target_ix); 6327 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no); 6328 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 6329 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 6330 } else { 6331 asyn_sdtr = 0; 6332 } 6333 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 6334 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 6335 AscSetChipSDTR(iop_base, 0, tid_no); 6336 boardp->sdtr_data[tid_no] = 0; 6337 } 6338 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6339 return; 6340 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 6341 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 6342 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 6343 boardp->sdtr_data[tid_no] = asyn_sdtr; 6344 } 6345 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6346 return; 6347 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 6348 AscMemWordCopyPtrFromLram(iop_base, 6349 ASCV_MSGIN_BEG, 6350 (uchar *)&ext_msg, 6351 sizeof(EXT_MSG) >> 1); 6352 6353 if (ext_msg.msg_type == EXTENDED_MESSAGE && 6354 ext_msg.msg_req == EXTENDED_SDTR && 6355 ext_msg.msg_len == MS_SDTR_LEN) { 6356 sdtr_accept = true; 6357 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) { 6358 6359 sdtr_accept = false; 6360 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 6361 } 6362 if ((ext_msg.xfer_period < 6363 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index]) 6364 || (ext_msg.xfer_period > 6365 asc_dvc->sdtr_period_tbl[asc_dvc-> 6366 max_sdtr_index])) { 6367 sdtr_accept = false; 6368 ext_msg.xfer_period = 6369 asc_dvc->sdtr_period_tbl[asc_dvc-> 6370 min_sdtr_index]; 6371 } 6372 if (sdtr_accept) { 6373 sdtr_data = 6374 AscCalSDTRData(asc_dvc, ext_msg.xfer_period, 6375 ext_msg.req_ack_offset); 6376 if (sdtr_data == 0xFF) { 6377 6378 q_cntl |= QC_MSG_OUT; 6379 asc_dvc->init_sdtr &= ~target_id; 6380 asc_dvc->sdtr_done &= ~target_id; 6381 AscSetChipSDTR(iop_base, asyn_sdtr, 6382 tid_no); 6383 boardp->sdtr_data[tid_no] = asyn_sdtr; 6384 } 6385 } 6386 if (ext_msg.req_ack_offset == 0) { 6387 6388 q_cntl &= ~QC_MSG_OUT; 6389 asc_dvc->init_sdtr &= ~target_id; 6390 asc_dvc->sdtr_done &= ~target_id; 6391 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 6392 } else { 6393 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) { 6394 q_cntl &= ~QC_MSG_OUT; 6395 asc_dvc->sdtr_done |= target_id; 6396 asc_dvc->init_sdtr |= target_id; 6397 asc_dvc->pci_fix_asyn_xfer &= 6398 ~target_id; 6399 sdtr_data = 6400 AscCalSDTRData(asc_dvc, 6401 ext_msg.xfer_period, 6402 ext_msg. 6403 req_ack_offset); 6404 AscSetChipSDTR(iop_base, sdtr_data, 6405 tid_no); 6406 boardp->sdtr_data[tid_no] = sdtr_data; 6407 } else { 6408 q_cntl |= QC_MSG_OUT; 6409 AscMsgOutSDTR(asc_dvc, 6410 ext_msg.xfer_period, 6411 ext_msg.req_ack_offset); 6412 asc_dvc->pci_fix_asyn_xfer &= 6413 ~target_id; 6414 sdtr_data = 6415 AscCalSDTRData(asc_dvc, 6416 ext_msg.xfer_period, 6417 ext_msg. 6418 req_ack_offset); 6419 AscSetChipSDTR(iop_base, sdtr_data, 6420 tid_no); 6421 boardp->sdtr_data[tid_no] = sdtr_data; 6422 asc_dvc->sdtr_done |= target_id; 6423 asc_dvc->init_sdtr |= target_id; 6424 } 6425 } 6426 6427 AscWriteLramByte(iop_base, 6428 (ushort)(halt_q_addr + 6429 (ushort)ASC_SCSIQ_B_CNTL), 6430 q_cntl); 6431 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6432 return; 6433 } else if (ext_msg.msg_type == EXTENDED_MESSAGE && 6434 ext_msg.msg_req == EXTENDED_WDTR && 6435 ext_msg.msg_len == MS_WDTR_LEN) { 6436 6437 ext_msg.wdtr_width = 0; 6438 AscMemWordCopyPtrToLram(iop_base, 6439 ASCV_MSGOUT_BEG, 6440 (uchar *)&ext_msg, 6441 sizeof(EXT_MSG) >> 1); 6442 q_cntl |= QC_MSG_OUT; 6443 AscWriteLramByte(iop_base, 6444 (ushort)(halt_q_addr + 6445 (ushort)ASC_SCSIQ_B_CNTL), 6446 q_cntl); 6447 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6448 return; 6449 } else { 6450 6451 ext_msg.msg_type = MESSAGE_REJECT; 6452 AscMemWordCopyPtrToLram(iop_base, 6453 ASCV_MSGOUT_BEG, 6454 (uchar *)&ext_msg, 6455 sizeof(EXT_MSG) >> 1); 6456 q_cntl |= QC_MSG_OUT; 6457 AscWriteLramByte(iop_base, 6458 (ushort)(halt_q_addr + 6459 (ushort)ASC_SCSIQ_B_CNTL), 6460 q_cntl); 6461 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6462 return; 6463 } 6464 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 6465 6466 q_cntl |= QC_REQ_SENSE; 6467 6468 if ((asc_dvc->init_sdtr & target_id) != 0) { 6469 6470 asc_dvc->sdtr_done &= ~target_id; 6471 6472 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 6473 q_cntl |= QC_MSG_OUT; 6474 AscMsgOutSDTR(asc_dvc, 6475 asc_dvc-> 6476 sdtr_period_tbl[(sdtr_data >> 4) & 6477 (uchar)(asc_dvc-> 6478 max_sdtr_index - 6479 1)], 6480 (uchar)(sdtr_data & (uchar) 6481 ASC_SYN_MAX_OFFSET)); 6482 } 6483 6484 AscWriteLramByte(iop_base, 6485 (ushort)(halt_q_addr + 6486 (ushort)ASC_SCSIQ_B_CNTL), q_cntl); 6487 6488 tag_code = AscReadLramByte(iop_base, 6489 (ushort)(halt_q_addr + (ushort) 6490 ASC_SCSIQ_B_TAG_CODE)); 6491 tag_code &= 0xDC; 6492 if ((asc_dvc->pci_fix_asyn_xfer & target_id) 6493 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id) 6494 ) { 6495 6496 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT 6497 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 6498 6499 } 6500 AscWriteLramByte(iop_base, 6501 (ushort)(halt_q_addr + 6502 (ushort)ASC_SCSIQ_B_TAG_CODE), 6503 tag_code); 6504 6505 q_status = AscReadLramByte(iop_base, 6506 (ushort)(halt_q_addr + (ushort) 6507 ASC_SCSIQ_B_STATUS)); 6508 q_status |= (QS_READY | QS_BUSY); 6509 AscWriteLramByte(iop_base, 6510 (ushort)(halt_q_addr + 6511 (ushort)ASC_SCSIQ_B_STATUS), 6512 q_status); 6513 6514 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B); 6515 scsi_busy &= ~target_id; 6516 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy); 6517 6518 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6519 return; 6520 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 6521 6522 AscMemWordCopyPtrFromLram(iop_base, 6523 ASCV_MSGOUT_BEG, 6524 (uchar *)&out_msg, 6525 sizeof(EXT_MSG) >> 1); 6526 6527 if ((out_msg.msg_type == EXTENDED_MESSAGE) && 6528 (out_msg.msg_len == MS_SDTR_LEN) && 6529 (out_msg.msg_req == EXTENDED_SDTR)) { 6530 6531 asc_dvc->init_sdtr &= ~target_id; 6532 asc_dvc->sdtr_done &= ~target_id; 6533 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 6534 boardp->sdtr_data[tid_no] = asyn_sdtr; 6535 } 6536 q_cntl &= ~QC_MSG_OUT; 6537 AscWriteLramByte(iop_base, 6538 (ushort)(halt_q_addr + 6539 (ushort)ASC_SCSIQ_B_CNTL), q_cntl); 6540 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6541 return; 6542 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 6543 6544 scsi_status = AscReadLramByte(iop_base, 6545 (ushort)((ushort)halt_q_addr + 6546 (ushort) 6547 ASC_SCSIQ_SCSI_STATUS)); 6548 cur_dvc_qng = 6549 AscReadLramByte(iop_base, 6550 (ushort)((ushort)ASC_QADR_BEG + 6551 (ushort)target_ix)); 6552 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) { 6553 6554 scsi_busy = AscReadLramByte(iop_base, 6555 (ushort)ASCV_SCSIBUSY_B); 6556 scsi_busy |= target_id; 6557 AscWriteLramByte(iop_base, 6558 (ushort)ASCV_SCSIBUSY_B, scsi_busy); 6559 asc_dvc->queue_full_or_busy |= target_id; 6560 6561 if (scsi_status == SAM_STAT_TASK_SET_FULL) { 6562 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 6563 cur_dvc_qng -= 1; 6564 asc_dvc->max_dvc_qng[tid_no] = 6565 cur_dvc_qng; 6566 6567 AscWriteLramByte(iop_base, 6568 (ushort)((ushort) 6569 ASCV_MAX_DVC_QNG_BEG 6570 + (ushort) 6571 tid_no), 6572 cur_dvc_qng); 6573 6574 /* 6575 * Set the device queue depth to the 6576 * number of active requests when the 6577 * QUEUE FULL condition was encountered. 6578 */ 6579 boardp->queue_full |= target_id; 6580 boardp->queue_full_cnt[tid_no] = 6581 cur_dvc_qng; 6582 } 6583 } 6584 } 6585 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6586 return; 6587 } 6588 return; 6589 } 6590 6591 /* 6592 * void 6593 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) 6594 * 6595 * Calling/Exit State: 6596 * none 6597 * 6598 * Description: 6599 * Input an ASC_QDONE_INFO structure from the chip 6600 */ 6601 static void 6602 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) 6603 { 6604 int i; 6605 ushort word; 6606 6607 AscSetChipLramAddr(iop_base, s_addr); 6608 for (i = 0; i < 2 * words; i += 2) { 6609 if (i == 10) { 6610 continue; 6611 } 6612 word = inpw(iop_base + IOP_RAM_DATA); 6613 inbuf[i] = word & 0xff; 6614 inbuf[i + 1] = (word >> 8) & 0xff; 6615 } 6616 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words); 6617 } 6618 6619 static uchar 6620 _AscCopyLramScsiDoneQ(PortAddr iop_base, 6621 ushort q_addr, 6622 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count) 6623 { 6624 ushort _val; 6625 uchar sg_queue_cnt; 6626 6627 DvcGetQinfo(iop_base, 6628 q_addr + ASC_SCSIQ_DONE_INFO_BEG, 6629 (uchar *)scsiq, 6630 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2); 6631 6632 _val = AscReadLramWord(iop_base, 6633 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS)); 6634 scsiq->q_status = (uchar)_val; 6635 scsiq->q_no = (uchar)(_val >> 8); 6636 _val = AscReadLramWord(iop_base, 6637 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL)); 6638 scsiq->cntl = (uchar)_val; 6639 sg_queue_cnt = (uchar)(_val >> 8); 6640 _val = AscReadLramWord(iop_base, 6641 (ushort)(q_addr + 6642 (ushort)ASC_SCSIQ_B_SENSE_LEN)); 6643 scsiq->sense_len = (uchar)_val; 6644 scsiq->extra_bytes = (uchar)(_val >> 8); 6645 6646 /* 6647 * Read high word of remain bytes from alternate location. 6648 */ 6649 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base, 6650 (ushort)(q_addr + 6651 (ushort) 6652 ASC_SCSIQ_W_ALT_DC1))) 6653 << 16); 6654 /* 6655 * Read low word of remain bytes from original location. 6656 */ 6657 scsiq->remain_bytes += AscReadLramWord(iop_base, 6658 (ushort)(q_addr + (ushort) 6659 ASC_SCSIQ_DW_REMAIN_XFER_CNT)); 6660 6661 scsiq->remain_bytes &= max_dma_count; 6662 return sg_queue_cnt; 6663 } 6664 6665 /* 6666 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR(). 6667 * 6668 * Interrupt callback function for the Narrow SCSI Asc Library. 6669 */ 6670 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep) 6671 { 6672 struct asc_board *boardp = asc_dvc_varp->drv_ptr; 6673 u32 srb_tag; 6674 struct scsi_cmnd *scp; 6675 6676 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep); 6677 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep); 6678 6679 /* 6680 * Decrease the srb_tag by 1 to find the SCSI command 6681 */ 6682 srb_tag = qdonep->d2.srb_tag - 1; 6683 scp = scsi_host_find_tag(boardp->shost, srb_tag); 6684 if (!scp) 6685 return; 6686 6687 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len); 6688 6689 ASC_STATS(boardp->shost, callback); 6690 6691 dma_unmap_single(boardp->dev, advansys_cmd(scp)->dma_handle, 6692 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 6693 /* 6694 * 'qdonep' contains the command's ending status. 6695 */ 6696 scp->result = 0; 6697 switch (qdonep->d3.done_stat) { 6698 case QD_NO_ERROR: 6699 ASC_DBG(2, "QD_NO_ERROR\n"); 6700 6701 /* 6702 * Check for an underrun condition. 6703 * 6704 * If there was no error and an underrun condition, then 6705 * return the number of underrun bytes. 6706 */ 6707 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 && 6708 qdonep->remain_bytes <= scsi_bufflen(scp)) { 6709 ASC_DBG(1, "underrun condition %u bytes\n", 6710 (unsigned)qdonep->remain_bytes); 6711 scsi_set_resid(scp, qdonep->remain_bytes); 6712 } 6713 break; 6714 6715 case QD_WITH_ERROR: 6716 ASC_DBG(2, "QD_WITH_ERROR\n"); 6717 switch (qdonep->d3.host_stat) { 6718 case QHSTA_NO_ERROR: 6719 set_status_byte(scp, qdonep->d3.scsi_stat); 6720 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) { 6721 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n"); 6722 ASC_DBG_PRT_SENSE(2, scp->sense_buffer, 6723 SCSI_SENSE_BUFFERSIZE); 6724 } 6725 break; 6726 6727 default: 6728 /* QHSTA error occurred */ 6729 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat); 6730 set_host_byte(scp, DID_BAD_TARGET); 6731 break; 6732 } 6733 break; 6734 6735 case QD_ABORTED_BY_HOST: 6736 ASC_DBG(1, "QD_ABORTED_BY_HOST\n"); 6737 set_status_byte(scp, qdonep->d3.scsi_stat); 6738 set_host_byte(scp, DID_ABORT); 6739 break; 6740 6741 default: 6742 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat); 6743 set_status_byte(scp, qdonep->d3.scsi_stat); 6744 set_host_byte(scp, DID_ERROR); 6745 break; 6746 } 6747 6748 /* 6749 * If the 'init_tidmask' bit isn't already set for the target and the 6750 * current request finished normally, then set the bit for the target 6751 * to indicate that a device is present. 6752 */ 6753 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 && 6754 qdonep->d3.done_stat == QD_NO_ERROR && 6755 qdonep->d3.host_stat == QHSTA_NO_ERROR) { 6756 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id); 6757 } 6758 6759 asc_scsi_done(scp); 6760 } 6761 6762 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc) 6763 { 6764 uchar next_qp; 6765 uchar n_q_used; 6766 uchar sg_list_qp; 6767 uchar sg_queue_cnt; 6768 uchar q_cnt; 6769 uchar done_q_tail; 6770 uchar tid_no; 6771 ASC_SCSI_BIT_ID_TYPE scsi_busy; 6772 ASC_SCSI_BIT_ID_TYPE target_id; 6773 PortAddr iop_base; 6774 ushort q_addr; 6775 ushort sg_q_addr; 6776 uchar cur_target_qng; 6777 ASC_QDONE_INFO scsiq_buf; 6778 ASC_QDONE_INFO *scsiq; 6779 bool false_overrun; 6780 6781 iop_base = asc_dvc->iop_base; 6782 n_q_used = 1; 6783 scsiq = (ASC_QDONE_INFO *)&scsiq_buf; 6784 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base); 6785 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 6786 next_qp = AscReadLramByte(iop_base, 6787 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD)); 6788 if (next_qp != ASC_QLINK_END) { 6789 AscPutVarDoneQTail(iop_base, next_qp); 6790 q_addr = ASC_QNO_TO_QADDR(next_qp); 6791 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq, 6792 asc_dvc->max_dma_count); 6793 AscWriteLramByte(iop_base, 6794 (ushort)(q_addr + 6795 (ushort)ASC_SCSIQ_B_STATUS), 6796 (uchar)(scsiq-> 6797 q_status & (uchar)~(QS_READY | 6798 QS_ABORTED))); 6799 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 6800 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 6801 if ((scsiq->cntl & QC_SG_HEAD) != 0) { 6802 sg_q_addr = q_addr; 6803 sg_list_qp = next_qp; 6804 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 6805 sg_list_qp = AscReadLramByte(iop_base, 6806 (ushort)(sg_q_addr 6807 + (ushort) 6808 ASC_SCSIQ_B_FWD)); 6809 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 6810 if (sg_list_qp == ASC_QLINK_END) { 6811 AscSetLibErrorCode(asc_dvc, 6812 ASCQ_ERR_SG_Q_LINKS); 6813 scsiq->d3.done_stat = QD_WITH_ERROR; 6814 scsiq->d3.host_stat = 6815 QHSTA_D_QDONE_SG_LIST_CORRUPTED; 6816 goto FATAL_ERR_QDONE; 6817 } 6818 AscWriteLramByte(iop_base, 6819 (ushort)(sg_q_addr + (ushort) 6820 ASC_SCSIQ_B_STATUS), 6821 QS_FREE); 6822 } 6823 n_q_used = sg_queue_cnt + 1; 6824 AscPutVarDoneQTail(iop_base, sg_list_qp); 6825 } 6826 if (asc_dvc->queue_full_or_busy & target_id) { 6827 cur_target_qng = AscReadLramByte(iop_base, 6828 (ushort)((ushort) 6829 ASC_QADR_BEG 6830 + (ushort) 6831 scsiq->d2. 6832 target_ix)); 6833 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) { 6834 scsi_busy = AscReadLramByte(iop_base, (ushort) 6835 ASCV_SCSIBUSY_B); 6836 scsi_busy &= ~target_id; 6837 AscWriteLramByte(iop_base, 6838 (ushort)ASCV_SCSIBUSY_B, 6839 scsi_busy); 6840 asc_dvc->queue_full_or_busy &= ~target_id; 6841 } 6842 } 6843 if (asc_dvc->cur_total_qng >= n_q_used) { 6844 asc_dvc->cur_total_qng -= n_q_used; 6845 if (asc_dvc->cur_dvc_qng[tid_no] != 0) { 6846 asc_dvc->cur_dvc_qng[tid_no]--; 6847 } 6848 } else { 6849 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG); 6850 scsiq->d3.done_stat = QD_WITH_ERROR; 6851 goto FATAL_ERR_QDONE; 6852 } 6853 if ((scsiq->d2.srb_tag == 0UL) || 6854 ((scsiq->q_status & QS_ABORTED) != 0)) { 6855 return (0x11); 6856 } else if (scsiq->q_status == QS_DONE) { 6857 /* 6858 * This is also curious. 6859 * false_overrun will _always_ be set to 'false' 6860 */ 6861 false_overrun = false; 6862 if (scsiq->extra_bytes != 0) { 6863 scsiq->remain_bytes += scsiq->extra_bytes; 6864 } 6865 if (scsiq->d3.done_stat == QD_WITH_ERROR) { 6866 if (scsiq->d3.host_stat == 6867 QHSTA_M_DATA_OVER_RUN) { 6868 if ((scsiq-> 6869 cntl & (QC_DATA_IN | QC_DATA_OUT)) 6870 == 0) { 6871 scsiq->d3.done_stat = 6872 QD_NO_ERROR; 6873 scsiq->d3.host_stat = 6874 QHSTA_NO_ERROR; 6875 } else if (false_overrun) { 6876 scsiq->d3.done_stat = 6877 QD_NO_ERROR; 6878 scsiq->d3.host_stat = 6879 QHSTA_NO_ERROR; 6880 } 6881 } else if (scsiq->d3.host_stat == 6882 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 6883 AscStopChip(iop_base); 6884 AscSetChipControl(iop_base, 6885 (uchar)(CC_SCSI_RESET 6886 | CC_HALT)); 6887 udelay(60); 6888 AscSetChipControl(iop_base, CC_HALT); 6889 AscSetChipStatus(iop_base, 6890 CIW_CLR_SCSI_RESET_INT); 6891 AscSetChipStatus(iop_base, 0); 6892 AscSetChipControl(iop_base, 0); 6893 } 6894 } 6895 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { 6896 asc_isr_callback(asc_dvc, scsiq); 6897 } else { 6898 if ((AscReadLramByte(iop_base, 6899 (ushort)(q_addr + (ushort) 6900 ASC_SCSIQ_CDB_BEG)) 6901 == START_STOP)) { 6902 asc_dvc->unit_not_ready &= ~target_id; 6903 if (scsiq->d3.done_stat != QD_NO_ERROR) { 6904 asc_dvc->start_motor &= 6905 ~target_id; 6906 } 6907 } 6908 } 6909 return (1); 6910 } else { 6911 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS); 6912 FATAL_ERR_QDONE: 6913 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { 6914 asc_isr_callback(asc_dvc, scsiq); 6915 } 6916 return (0x80); 6917 } 6918 } 6919 return (0); 6920 } 6921 6922 static int AscISR(ASC_DVC_VAR *asc_dvc) 6923 { 6924 ASC_CS_TYPE chipstat; 6925 PortAddr iop_base; 6926 ushort saved_ram_addr; 6927 uchar ctrl_reg; 6928 uchar saved_ctrl_reg; 6929 int int_pending; 6930 int status; 6931 uchar host_flag; 6932 6933 iop_base = asc_dvc->iop_base; 6934 int_pending = ASC_FALSE; 6935 6936 if (AscIsIntPending(iop_base) == 0) 6937 return int_pending; 6938 6939 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) { 6940 return ASC_ERROR; 6941 } 6942 if (asc_dvc->in_critical_cnt != 0) { 6943 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL); 6944 return ASC_ERROR; 6945 } 6946 if (asc_dvc->is_in_int) { 6947 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY); 6948 return ASC_ERROR; 6949 } 6950 asc_dvc->is_in_int = true; 6951 ctrl_reg = AscGetChipControl(iop_base); 6952 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET | 6953 CC_SINGLE_STEP | CC_DIAG | CC_TEST)); 6954 chipstat = AscGetChipStatus(iop_base); 6955 if (chipstat & CSW_SCSI_RESET_LATCH) { 6956 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 6957 int i = 10; 6958 int_pending = ASC_TRUE; 6959 asc_dvc->sdtr_done = 0; 6960 saved_ctrl_reg &= (uchar)(~CC_HALT); 6961 while ((AscGetChipStatus(iop_base) & 6962 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) { 6963 mdelay(100); 6964 } 6965 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT)); 6966 AscSetChipControl(iop_base, CC_HALT); 6967 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); 6968 AscSetChipStatus(iop_base, 0); 6969 chipstat = AscGetChipStatus(iop_base); 6970 } 6971 } 6972 saved_ram_addr = AscGetChipLramAddr(iop_base); 6973 host_flag = AscReadLramByte(iop_base, 6974 ASCV_HOST_FLAG_B) & 6975 (uchar)(~ASC_HOST_FLAG_IN_ISR); 6976 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, 6977 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR)); 6978 if ((chipstat & CSW_INT_PENDING) || (int_pending)) { 6979 AscAckInterrupt(iop_base); 6980 int_pending = ASC_TRUE; 6981 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) { 6982 AscIsrChipHalted(asc_dvc); 6983 saved_ctrl_reg &= (uchar)(~CC_HALT); 6984 } else { 6985 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) { 6986 while (((status = 6987 AscIsrQDone(asc_dvc)) & 0x01) != 0) { 6988 } 6989 } else { 6990 do { 6991 if ((status = 6992 AscIsrQDone(asc_dvc)) == 1) { 6993 break; 6994 } 6995 } while (status == 0x11); 6996 } 6997 if ((status & 0x80) != 0) 6998 int_pending = ASC_ERROR; 6999 } 7000 } 7001 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); 7002 AscSetChipLramAddr(iop_base, saved_ram_addr); 7003 AscSetChipControl(iop_base, saved_ctrl_reg); 7004 asc_dvc->is_in_int = false; 7005 return int_pending; 7006 } 7007 7008 /* 7009 * advansys_reset() 7010 * 7011 * Reset the host associated with the command 'scp'. 7012 * 7013 * This function runs its own thread. Interrupts must be blocked but 7014 * sleeping is allowed and no locking other than for host structures is 7015 * required. Returns SUCCESS or FAILED. 7016 */ 7017 static int advansys_reset(struct scsi_cmnd *scp) 7018 { 7019 struct Scsi_Host *shost = scp->device->host; 7020 struct asc_board *boardp = shost_priv(shost); 7021 unsigned long flags; 7022 int status; 7023 int ret = SUCCESS; 7024 7025 ASC_DBG(1, "0x%p\n", scp); 7026 7027 ASC_STATS(shost, reset); 7028 7029 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n"); 7030 7031 if (ASC_NARROW_BOARD(boardp)) { 7032 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var; 7033 7034 /* Reset the chip and SCSI bus. */ 7035 ASC_DBG(1, "before AscInitAsc1000Driver()\n"); 7036 status = AscInitAsc1000Driver(asc_dvc); 7037 7038 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */ 7039 if (asc_dvc->err_code || !asc_dvc->overrun_dma) { 7040 scmd_printk(KERN_INFO, scp, "SCSI host reset error: " 7041 "0x%x, status: 0x%x\n", asc_dvc->err_code, 7042 status); 7043 ret = FAILED; 7044 } else if (status) { 7045 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: " 7046 "0x%x\n", status); 7047 } else { 7048 scmd_printk(KERN_INFO, scp, "SCSI host reset " 7049 "successful\n"); 7050 } 7051 7052 ASC_DBG(1, "after AscInitAsc1000Driver()\n"); 7053 } else { 7054 /* 7055 * If the suggest reset bus flags are set, then reset the bus. 7056 * Otherwise only reset the device. 7057 */ 7058 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var; 7059 7060 /* 7061 * Reset the chip and SCSI bus. 7062 */ 7063 ASC_DBG(1, "before AdvResetChipAndSB()\n"); 7064 switch (AdvResetChipAndSB(adv_dvc)) { 7065 case ASC_TRUE: 7066 scmd_printk(KERN_INFO, scp, "SCSI host reset " 7067 "successful\n"); 7068 break; 7069 case ASC_FALSE: 7070 default: 7071 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n"); 7072 ret = FAILED; 7073 break; 7074 } 7075 spin_lock_irqsave(shost->host_lock, flags); 7076 AdvISR(adv_dvc); 7077 spin_unlock_irqrestore(shost->host_lock, flags); 7078 } 7079 7080 ASC_DBG(1, "ret %d\n", ret); 7081 7082 return ret; 7083 } 7084 7085 /* 7086 * advansys_biosparam() 7087 * 7088 * Translate disk drive geometry if the "BIOS greater than 1 GB" 7089 * support is enabled for a drive. 7090 * 7091 * ip (information pointer) is an int array with the following definition: 7092 * ip[0]: heads 7093 * ip[1]: sectors 7094 * ip[2]: cylinders 7095 */ 7096 static int 7097 advansys_biosparam(struct scsi_device *sdev, struct gendisk *unused, 7098 sector_t capacity, int ip[]) 7099 { 7100 struct asc_board *boardp = shost_priv(sdev->host); 7101 7102 ASC_DBG(1, "begin\n"); 7103 ASC_STATS(sdev->host, biosparam); 7104 if (ASC_NARROW_BOARD(boardp)) { 7105 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl & 7106 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) { 7107 ip[0] = 255; 7108 ip[1] = 63; 7109 } else { 7110 ip[0] = 64; 7111 ip[1] = 32; 7112 } 7113 } else { 7114 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl & 7115 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) { 7116 ip[0] = 255; 7117 ip[1] = 63; 7118 } else { 7119 ip[0] = 64; 7120 ip[1] = 32; 7121 } 7122 } 7123 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]); 7124 ASC_DBG(1, "end\n"); 7125 return 0; 7126 } 7127 7128 /* 7129 * First-level interrupt handler. 7130 * 7131 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host. 7132 */ 7133 static irqreturn_t advansys_interrupt(int irq, void *dev_id) 7134 { 7135 struct Scsi_Host *shost = dev_id; 7136 struct asc_board *boardp = shost_priv(shost); 7137 irqreturn_t result = IRQ_NONE; 7138 unsigned long flags; 7139 7140 ASC_DBG(2, "boardp 0x%p\n", boardp); 7141 spin_lock_irqsave(shost->host_lock, flags); 7142 if (ASC_NARROW_BOARD(boardp)) { 7143 if (AscIsIntPending(shost->io_port)) { 7144 result = IRQ_HANDLED; 7145 ASC_STATS(shost, interrupt); 7146 ASC_DBG(1, "before AscISR()\n"); 7147 AscISR(&boardp->dvc_var.asc_dvc_var); 7148 } 7149 } else { 7150 ASC_DBG(1, "before AdvISR()\n"); 7151 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) { 7152 result = IRQ_HANDLED; 7153 ASC_STATS(shost, interrupt); 7154 } 7155 } 7156 spin_unlock_irqrestore(shost->host_lock, flags); 7157 7158 ASC_DBG(1, "end\n"); 7159 return result; 7160 } 7161 7162 static bool AscHostReqRiscHalt(PortAddr iop_base) 7163 { 7164 int count = 0; 7165 bool sta = false; 7166 uchar saved_stop_code; 7167 7168 if (AscIsChipHalted(iop_base)) 7169 return true; 7170 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B); 7171 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 7172 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 7173 do { 7174 if (AscIsChipHalted(iop_base)) { 7175 sta = true; 7176 break; 7177 } 7178 mdelay(100); 7179 } while (count++ < 20); 7180 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code); 7181 return sta; 7182 } 7183 7184 static bool 7185 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data) 7186 { 7187 bool sta = false; 7188 7189 if (AscHostReqRiscHalt(iop_base)) { 7190 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data); 7191 AscStartChip(iop_base); 7192 } 7193 return sta; 7194 } 7195 7196 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev) 7197 { 7198 char type = sdev->type; 7199 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id; 7200 7201 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN)) 7202 return; 7203 if (asc_dvc->init_sdtr & tid_bits) 7204 return; 7205 7206 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0)) 7207 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits; 7208 7209 asc_dvc->pci_fix_asyn_xfer |= tid_bits; 7210 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) || 7211 (type == TYPE_ROM) || (type == TYPE_TAPE)) 7212 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits; 7213 7214 if (asc_dvc->pci_fix_asyn_xfer & tid_bits) 7215 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id, 7216 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 7217 } 7218 7219 static void 7220 advansys_narrow_sdev_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc) 7221 { 7222 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id; 7223 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng; 7224 7225 if (sdev->lun == 0) { 7226 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr; 7227 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) { 7228 asc_dvc->init_sdtr |= tid_bit; 7229 } else { 7230 asc_dvc->init_sdtr &= ~tid_bit; 7231 } 7232 7233 if (orig_init_sdtr != asc_dvc->init_sdtr) 7234 AscAsyncFix(asc_dvc, sdev); 7235 } 7236 7237 if (sdev->tagged_supported) { 7238 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) { 7239 if (sdev->lun == 0) { 7240 asc_dvc->cfg->can_tagged_qng |= tid_bit; 7241 asc_dvc->use_tagged_qng |= tid_bit; 7242 } 7243 scsi_change_queue_depth(sdev, 7244 asc_dvc->max_dvc_qng[sdev->id]); 7245 } 7246 } else { 7247 if (sdev->lun == 0) { 7248 asc_dvc->cfg->can_tagged_qng &= ~tid_bit; 7249 asc_dvc->use_tagged_qng &= ~tid_bit; 7250 } 7251 } 7252 7253 if ((sdev->lun == 0) && 7254 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) { 7255 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B, 7256 asc_dvc->cfg->disc_enable); 7257 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B, 7258 asc_dvc->use_tagged_qng); 7259 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B, 7260 asc_dvc->cfg->can_tagged_qng); 7261 7262 asc_dvc->max_dvc_qng[sdev->id] = 7263 asc_dvc->cfg->max_tag_qng[sdev->id]; 7264 AscWriteLramByte(asc_dvc->iop_base, 7265 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id), 7266 asc_dvc->max_dvc_qng[sdev->id]); 7267 } 7268 } 7269 7270 /* 7271 * Wide Transfers 7272 * 7273 * If the EEPROM enabled WDTR for the device and the device supports wide 7274 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and 7275 * write the new value to the microcode. 7276 */ 7277 static void 7278 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask) 7279 { 7280 unsigned short cfg_word; 7281 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word); 7282 if ((cfg_word & tidmask) != 0) 7283 return; 7284 7285 cfg_word |= tidmask; 7286 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word); 7287 7288 /* 7289 * Clear the microcode SDTR and WDTR negotiation done indicators for 7290 * the target to cause it to negotiate with the new setting set above. 7291 * WDTR when accepted causes the target to enter asynchronous mode, so 7292 * SDTR must be negotiated. 7293 */ 7294 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7295 cfg_word &= ~tidmask; 7296 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7297 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word); 7298 cfg_word &= ~tidmask; 7299 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word); 7300 } 7301 7302 /* 7303 * Synchronous Transfers 7304 * 7305 * If the EEPROM enabled SDTR for the device and the device 7306 * supports synchronous transfers, then turn on the device's 7307 * 'sdtr_able' bit. Write the new value to the microcode. 7308 */ 7309 static void 7310 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask) 7311 { 7312 unsigned short cfg_word; 7313 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word); 7314 if ((cfg_word & tidmask) != 0) 7315 return; 7316 7317 cfg_word |= tidmask; 7318 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word); 7319 7320 /* 7321 * Clear the microcode "SDTR negotiation" done indicator for the 7322 * target to cause it to negotiate with the new setting set above. 7323 */ 7324 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7325 cfg_word &= ~tidmask; 7326 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7327 } 7328 7329 /* 7330 * PPR (Parallel Protocol Request) Capable 7331 * 7332 * If the device supports DT mode, then it must be PPR capable. 7333 * The PPR message will be used in place of the SDTR and WDTR 7334 * messages to negotiate synchronous speed and offset, transfer 7335 * width, and protocol options. 7336 */ 7337 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc, 7338 AdvPortAddr iop_base, unsigned short tidmask) 7339 { 7340 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able); 7341 adv_dvc->ppr_able |= tidmask; 7342 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able); 7343 } 7344 7345 static void 7346 advansys_wide_sdev_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc) 7347 { 7348 AdvPortAddr iop_base = adv_dvc->iop_base; 7349 unsigned short tidmask = 1 << sdev->id; 7350 7351 if (sdev->lun == 0) { 7352 /* 7353 * Handle WDTR, SDTR, and Tag Queuing. If the feature 7354 * is enabled in the EEPROM and the device supports the 7355 * feature, then enable it in the microcode. 7356 */ 7357 7358 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr) 7359 advansys_wide_enable_wdtr(iop_base, tidmask); 7360 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr) 7361 advansys_wide_enable_sdtr(iop_base, tidmask); 7362 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr) 7363 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask); 7364 7365 /* 7366 * Tag Queuing is disabled for the BIOS which runs in polled 7367 * mode and would see no benefit from Tag Queuing. Also by 7368 * disabling Tag Queuing in the BIOS devices with Tag Queuing 7369 * bugs will at least work with the BIOS. 7370 */ 7371 if ((adv_dvc->tagqng_able & tidmask) && 7372 sdev->tagged_supported) { 7373 unsigned short cfg_word; 7374 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word); 7375 cfg_word |= tidmask; 7376 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 7377 cfg_word); 7378 AdvWriteByteLram(iop_base, 7379 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id, 7380 adv_dvc->max_dvc_qng); 7381 } 7382 } 7383 7384 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) 7385 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng); 7386 } 7387 7388 /* 7389 * Set the number of commands to queue per device for the 7390 * specified host adapter. 7391 */ 7392 static int advansys_sdev_configure(struct scsi_device *sdev, 7393 struct queue_limits *lim) 7394 { 7395 struct asc_board *boardp = shost_priv(sdev->host); 7396 7397 if (ASC_NARROW_BOARD(boardp)) 7398 advansys_narrow_sdev_configure(sdev, 7399 &boardp->dvc_var.asc_dvc_var); 7400 else 7401 advansys_wide_sdev_configure(sdev, 7402 &boardp->dvc_var.adv_dvc_var); 7403 7404 return 0; 7405 } 7406 7407 static __le32 asc_get_sense_buffer_dma(struct scsi_cmnd *scp) 7408 { 7409 struct asc_board *board = shost_priv(scp->device->host); 7410 struct advansys_cmd *acmd = advansys_cmd(scp); 7411 7412 acmd->dma_handle = dma_map_single(board->dev, scp->sense_buffer, 7413 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 7414 if (dma_mapping_error(board->dev, acmd->dma_handle)) { 7415 ASC_DBG(1, "failed to map sense buffer\n"); 7416 return 0; 7417 } 7418 return cpu_to_le32(acmd->dma_handle); 7419 } 7420 7421 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp, 7422 struct asc_scsi_q *asc_scsi_q) 7423 { 7424 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var; 7425 int use_sg; 7426 u32 srb_tag; 7427 7428 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q)); 7429 7430 /* 7431 * Set the srb_tag to the command tag + 1, as 7432 * srb_tag '0' is used internally by the chip. 7433 */ 7434 srb_tag = scsi_cmd_to_rq(scp)->tag + 1; 7435 asc_scsi_q->q2.srb_tag = srb_tag; 7436 7437 /* 7438 * Build the ASC_SCSI_Q request. 7439 */ 7440 asc_scsi_q->cdbptr = &scp->cmnd[0]; 7441 asc_scsi_q->q2.cdb_len = scp->cmd_len; 7442 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id); 7443 asc_scsi_q->q1.target_lun = scp->device->lun; 7444 asc_scsi_q->q2.target_ix = 7445 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun); 7446 asc_scsi_q->q1.sense_addr = asc_get_sense_buffer_dma(scp); 7447 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE; 7448 if (!asc_scsi_q->q1.sense_addr) 7449 return ASC_BUSY; 7450 7451 /* 7452 * If there are any outstanding requests for the current target, 7453 * then every 255th request send an ORDERED request. This heuristic 7454 * tries to retain the benefit of request sorting while preventing 7455 * request starvation. 255 is the max number of tags or pending commands 7456 * a device may have outstanding. 7457 * 7458 * The request count is incremented below for every successfully 7459 * started request. 7460 * 7461 */ 7462 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) && 7463 (boardp->reqcnt[scp->device->id] % 255) == 0) { 7464 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG; 7465 } else { 7466 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG; 7467 } 7468 7469 /* Build ASC_SCSI_Q */ 7470 use_sg = scsi_dma_map(scp); 7471 if (use_sg < 0) { 7472 ASC_DBG(1, "failed to map sglist\n"); 7473 return ASC_BUSY; 7474 } else if (use_sg > 0) { 7475 int sgcnt; 7476 struct scatterlist *slp; 7477 struct asc_sg_head *asc_sg_head; 7478 7479 if (use_sg > scp->device->host->sg_tablesize) { 7480 scmd_printk(KERN_ERR, scp, "use_sg %d > " 7481 "sg_tablesize %d\n", use_sg, 7482 scp->device->host->sg_tablesize); 7483 scsi_dma_unmap(scp); 7484 set_host_byte(scp, DID_ERROR); 7485 return ASC_ERROR; 7486 } 7487 7488 asc_sg_head = kzalloc_flex(*asc_sg_head, sg_list, use_sg, 7489 GFP_ATOMIC); 7490 if (!asc_sg_head) { 7491 scsi_dma_unmap(scp); 7492 set_host_byte(scp, DID_SOFT_ERROR); 7493 return ASC_ERROR; 7494 } 7495 7496 asc_scsi_q->q1.cntl |= QC_SG_HEAD; 7497 asc_scsi_q->sg_head = asc_sg_head; 7498 asc_scsi_q->q1.data_cnt = 0; 7499 asc_scsi_q->q1.data_addr = 0; 7500 /* This is a byte value, otherwise it would need to be swapped. */ 7501 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg; 7502 ASC_STATS_ADD(scp->device->host, xfer_elem, 7503 asc_sg_head->entry_cnt); 7504 7505 /* 7506 * Convert scatter-gather list into ASC_SG_HEAD list. 7507 */ 7508 scsi_for_each_sg(scp, slp, use_sg, sgcnt) { 7509 asc_sg_head->sg_list[sgcnt].addr = 7510 cpu_to_le32(sg_dma_address(slp)); 7511 asc_sg_head->sg_list[sgcnt].bytes = 7512 cpu_to_le32(sg_dma_len(slp)); 7513 ASC_STATS_ADD(scp->device->host, xfer_sect, 7514 DIV_ROUND_UP(sg_dma_len(slp), 512)); 7515 } 7516 } 7517 7518 ASC_STATS(scp->device->host, xfer_cnt); 7519 7520 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q); 7521 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len); 7522 7523 return ASC_NOERROR; 7524 } 7525 7526 /* 7527 * Build scatter-gather list for Adv Library (Wide Board). 7528 * 7529 * Additional ADV_SG_BLOCK structures will need to be allocated 7530 * if the total number of scatter-gather elements exceeds 7531 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are 7532 * assumed to be physically contiguous. 7533 * 7534 * Return: 7535 * ADV_SUCCESS(1) - SG List successfully created 7536 * ADV_ERROR(-1) - SG List creation failed 7537 */ 7538 static int 7539 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, 7540 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg) 7541 { 7542 adv_sgblk_t *sgblkp, *prev_sgblkp; 7543 struct scatterlist *slp; 7544 int sg_elem_cnt; 7545 ADV_SG_BLOCK *sg_block, *prev_sg_block; 7546 dma_addr_t sgblk_paddr; 7547 int i; 7548 7549 slp = scsi_sglist(scp); 7550 sg_elem_cnt = use_sg; 7551 prev_sgblkp = NULL; 7552 prev_sg_block = NULL; 7553 reqp->sgblkp = NULL; 7554 7555 for (;;) { 7556 /* 7557 * Allocate a 'adv_sgblk_t' structure from the board free 7558 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK 7559 * (15) scatter-gather elements. 7560 */ 7561 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC, 7562 &sgblk_paddr); 7563 if (!sgblkp) { 7564 ASC_DBG(1, "no free adv_sgblk_t\n"); 7565 ASC_STATS(scp->device->host, adv_build_nosg); 7566 7567 /* 7568 * Allocation failed. Free 'adv_sgblk_t' structures 7569 * already allocated for the request. 7570 */ 7571 while ((sgblkp = reqp->sgblkp) != NULL) { 7572 /* Remove 'sgblkp' from the request list. */ 7573 reqp->sgblkp = sgblkp->next_sgblkp; 7574 sgblkp->next_sgblkp = NULL; 7575 dma_pool_free(boardp->adv_sgblk_pool, sgblkp, 7576 sgblkp->sg_addr); 7577 } 7578 return ASC_BUSY; 7579 } 7580 /* Complete 'adv_sgblk_t' board allocation. */ 7581 sgblkp->sg_addr = sgblk_paddr; 7582 sgblkp->next_sgblkp = NULL; 7583 sg_block = &sgblkp->sg_block; 7584 7585 /* 7586 * Check if this is the first 'adv_sgblk_t' for the 7587 * request. 7588 */ 7589 if (reqp->sgblkp == NULL) { 7590 /* Request's first scatter-gather block. */ 7591 reqp->sgblkp = sgblkp; 7592 7593 /* 7594 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical 7595 * address pointers. 7596 */ 7597 scsiqp->sg_list_ptr = sg_block; 7598 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr); 7599 } else { 7600 /* Request's second or later scatter-gather block. */ 7601 prev_sgblkp->next_sgblkp = sgblkp; 7602 7603 /* 7604 * Point the previous ADV_SG_BLOCK structure to 7605 * the newly allocated ADV_SG_BLOCK structure. 7606 */ 7607 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr); 7608 } 7609 7610 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { 7611 sg_block->sg_list[i].sg_addr = 7612 cpu_to_le32(sg_dma_address(slp)); 7613 sg_block->sg_list[i].sg_count = 7614 cpu_to_le32(sg_dma_len(slp)); 7615 ASC_STATS_ADD(scp->device->host, xfer_sect, 7616 DIV_ROUND_UP(sg_dma_len(slp), 512)); 7617 7618 if (--sg_elem_cnt == 0) { 7619 /* 7620 * Last ADV_SG_BLOCK and scatter-gather entry. 7621 */ 7622 sg_block->sg_cnt = i + 1; 7623 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */ 7624 return ADV_SUCCESS; 7625 } 7626 slp = sg_next(slp); 7627 } 7628 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK; 7629 prev_sg_block = sg_block; 7630 prev_sgblkp = sgblkp; 7631 } 7632 } 7633 7634 /* 7635 * Build a request structure for the Adv Library (Wide Board). 7636 * 7637 * If an adv_req_t can not be allocated to issue the request, 7638 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR. 7639 * 7640 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the 7641 * microcode for DMA addresses or math operations are byte swapped 7642 * to little-endian order. 7643 */ 7644 static int 7645 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp, 7646 adv_req_t **adv_reqpp) 7647 { 7648 u32 srb_tag = scsi_cmd_to_rq(scp)->tag; 7649 adv_req_t *reqp; 7650 ADV_SCSI_REQ_Q *scsiqp; 7651 int ret; 7652 int use_sg; 7653 dma_addr_t sense_addr; 7654 7655 /* 7656 * Allocate an adv_req_t structure from the board to execute 7657 * the command. 7658 */ 7659 reqp = &boardp->adv_reqp[srb_tag]; 7660 if (reqp->cmndp && reqp->cmndp != scp ) { 7661 ASC_DBG(1, "no free adv_req_t\n"); 7662 ASC_STATS(scp->device->host, adv_build_noreq); 7663 return ASC_BUSY; 7664 } 7665 7666 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t)); 7667 7668 scsiqp = &reqp->scsi_req_q; 7669 7670 /* 7671 * Initialize the structure. 7672 */ 7673 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0; 7674 7675 /* 7676 * Set the srb_tag to the command tag. 7677 */ 7678 scsiqp->srb_tag = srb_tag; 7679 7680 /* 7681 * Set 'host_scribble' to point to the adv_req_t structure. 7682 */ 7683 reqp->cmndp = scp; 7684 scp->host_scribble = (void *)reqp; 7685 7686 /* 7687 * Build the ADV_SCSI_REQ_Q request. 7688 */ 7689 7690 /* Set CDB length and copy it to the request structure. */ 7691 scsiqp->cdb_len = scp->cmd_len; 7692 /* Copy first 12 CDB bytes to cdb[]. */ 7693 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12); 7694 /* Copy last 4 CDB bytes, if present, to cdb16[]. */ 7695 if (scp->cmd_len > 12) { 7696 int cdb16_len = scp->cmd_len - 12; 7697 7698 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len); 7699 } 7700 7701 scsiqp->target_id = scp->device->id; 7702 scsiqp->target_lun = scp->device->lun; 7703 7704 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer, 7705 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 7706 if (dma_mapping_error(boardp->dev, sense_addr)) { 7707 ASC_DBG(1, "failed to map sense buffer\n"); 7708 ASC_STATS(scp->device->host, adv_build_noreq); 7709 return ASC_BUSY; 7710 } 7711 scsiqp->sense_addr = cpu_to_le32(sense_addr); 7712 scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE; 7713 7714 /* Build ADV_SCSI_REQ_Q */ 7715 7716 use_sg = scsi_dma_map(scp); 7717 if (use_sg < 0) { 7718 ASC_DBG(1, "failed to map SG list\n"); 7719 ASC_STATS(scp->device->host, adv_build_noreq); 7720 return ASC_BUSY; 7721 } else if (use_sg == 0) { 7722 /* Zero-length transfer */ 7723 reqp->sgblkp = NULL; 7724 scsiqp->data_cnt = 0; 7725 7726 scsiqp->data_addr = 0; 7727 scsiqp->sg_list_ptr = NULL; 7728 scsiqp->sg_real_addr = 0; 7729 } else { 7730 if (use_sg > ADV_MAX_SG_LIST) { 7731 scmd_printk(KERN_ERR, scp, "use_sg %d > " 7732 "ADV_MAX_SG_LIST %d\n", use_sg, 7733 scp->device->host->sg_tablesize); 7734 scsi_dma_unmap(scp); 7735 set_host_byte(scp, DID_ERROR); 7736 reqp->cmndp = NULL; 7737 scp->host_scribble = NULL; 7738 7739 return ASC_ERROR; 7740 } 7741 7742 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp)); 7743 7744 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg); 7745 if (ret != ADV_SUCCESS) { 7746 scsi_dma_unmap(scp); 7747 set_host_byte(scp, DID_ERROR); 7748 reqp->cmndp = NULL; 7749 scp->host_scribble = NULL; 7750 7751 return ret; 7752 } 7753 7754 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg); 7755 } 7756 7757 ASC_STATS(scp->device->host, xfer_cnt); 7758 7759 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp); 7760 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len); 7761 7762 *adv_reqpp = reqp; 7763 7764 return ASC_NOERROR; 7765 } 7766 7767 static int AscSgListToQueue(int sg_list) 7768 { 7769 int n_sg_list_qs; 7770 7771 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 7772 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 7773 n_sg_list_qs++; 7774 return n_sg_list_qs + 1; 7775 } 7776 7777 static uint 7778 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs) 7779 { 7780 uint cur_used_qs; 7781 uint cur_free_qs; 7782 ASC_SCSI_BIT_ID_TYPE target_id; 7783 uchar tid_no; 7784 7785 target_id = ASC_TIX_TO_TARGET_ID(target_ix); 7786 tid_no = ASC_TIX_TO_TID(target_ix); 7787 if ((asc_dvc->unit_not_ready & target_id) || 7788 (asc_dvc->queue_full_or_busy & target_id)) { 7789 return 0; 7790 } 7791 if (n_qs == 1) { 7792 cur_used_qs = (uint) asc_dvc->cur_total_qng + 7793 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q; 7794 } else { 7795 cur_used_qs = (uint) asc_dvc->cur_total_qng + 7796 (uint) ASC_MIN_FREE_Q; 7797 } 7798 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) { 7799 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs; 7800 if (asc_dvc->cur_dvc_qng[tid_no] >= 7801 asc_dvc->max_dvc_qng[tid_no]) { 7802 return 0; 7803 } 7804 return cur_free_qs; 7805 } 7806 if (n_qs > 1) { 7807 if ((n_qs > asc_dvc->last_q_shortage) 7808 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) { 7809 asc_dvc->last_q_shortage = n_qs; 7810 } 7811 } 7812 return 0; 7813 } 7814 7815 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head) 7816 { 7817 ushort q_addr; 7818 uchar next_qp; 7819 uchar q_status; 7820 7821 q_addr = ASC_QNO_TO_QADDR(free_q_head); 7822 q_status = (uchar)AscReadLramByte(iop_base, 7823 (ushort)(q_addr + 7824 ASC_SCSIQ_B_STATUS)); 7825 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD)); 7826 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 7827 return next_qp; 7828 return ASC_QLINK_END; 7829 } 7830 7831 static uchar 7832 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q) 7833 { 7834 uchar i; 7835 7836 for (i = 0; i < n_free_q; i++) { 7837 free_q_head = AscAllocFreeQueue(iop_base, free_q_head); 7838 if (free_q_head == ASC_QLINK_END) 7839 break; 7840 } 7841 return free_q_head; 7842 } 7843 7844 /* 7845 * void 7846 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) 7847 * 7848 * Calling/Exit State: 7849 * none 7850 * 7851 * Description: 7852 * Output an ASC_SCSI_Q structure to the chip 7853 */ 7854 static void 7855 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) 7856 { 7857 int i; 7858 7859 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words); 7860 AscSetChipLramAddr(iop_base, s_addr); 7861 for (i = 0; i < 2 * words; i += 2) { 7862 if (i == 4 || i == 20) { 7863 continue; 7864 } 7865 outpw(iop_base + IOP_RAM_DATA, 7866 ((ushort)outbuf[i + 1] << 8) | outbuf[i]); 7867 } 7868 } 7869 7870 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) 7871 { 7872 ushort q_addr; 7873 uchar tid_no; 7874 uchar sdtr_data; 7875 uchar syn_period_ix; 7876 uchar syn_offset; 7877 PortAddr iop_base; 7878 7879 iop_base = asc_dvc->iop_base; 7880 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) && 7881 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) { 7882 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 7883 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 7884 syn_period_ix = 7885 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1); 7886 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 7887 AscMsgOutSDTR(asc_dvc, 7888 asc_dvc->sdtr_period_tbl[syn_period_ix], 7889 syn_offset); 7890 scsiq->q1.cntl |= QC_MSG_OUT; 7891 } 7892 q_addr = ASC_QNO_TO_QADDR(q_no); 7893 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) { 7894 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG; 7895 } 7896 scsiq->q1.status = QS_FREE; 7897 AscMemWordCopyPtrToLram(iop_base, 7898 q_addr + ASC_SCSIQ_CDB_BEG, 7899 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 7900 7901 DvcPutScsiQ(iop_base, 7902 q_addr + ASC_SCSIQ_CPY_BEG, 7903 (uchar *)&scsiq->q1.cntl, 7904 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1); 7905 AscWriteLramWord(iop_base, 7906 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS), 7907 (ushort)(((ushort)scsiq->q1. 7908 q_no << 8) | (ushort)QS_READY)); 7909 return 1; 7910 } 7911 7912 static int 7913 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) 7914 { 7915 int sta; 7916 int i; 7917 ASC_SG_HEAD *sg_head; 7918 ASC_SG_LIST_Q scsi_sg_q; 7919 __le32 saved_data_addr; 7920 __le32 saved_data_cnt; 7921 PortAddr iop_base; 7922 ushort sg_list_dwords; 7923 ushort sg_index; 7924 ushort sg_entry_cnt; 7925 ushort q_addr; 7926 uchar next_qp; 7927 7928 iop_base = asc_dvc->iop_base; 7929 sg_head = scsiq->sg_head; 7930 saved_data_addr = scsiq->q1.data_addr; 7931 saved_data_cnt = scsiq->q1.data_cnt; 7932 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr); 7933 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes); 7934 /* 7935 * Set sg_entry_cnt to be the number of SG elements that 7936 * will fit in the allocated SG queues. It is minus 1, because 7937 * the first SG element is handled above. 7938 */ 7939 sg_entry_cnt = sg_head->entry_cnt - 1; 7940 7941 if (sg_entry_cnt != 0) { 7942 scsiq->q1.cntl |= QC_SG_HEAD; 7943 q_addr = ASC_QNO_TO_QADDR(q_no); 7944 sg_index = 1; 7945 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 7946 scsi_sg_q.sg_head_qp = q_no; 7947 scsi_sg_q.cntl = QCSG_SG_XFER_LIST; 7948 for (i = 0; i < sg_head->queue_cnt; i++) { 7949 scsi_sg_q.seq_no = i + 1; 7950 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 7951 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2); 7952 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 7953 if (i == 0) { 7954 scsi_sg_q.sg_list_cnt = 7955 ASC_SG_LIST_PER_Q; 7956 scsi_sg_q.sg_cur_list_cnt = 7957 ASC_SG_LIST_PER_Q; 7958 } else { 7959 scsi_sg_q.sg_list_cnt = 7960 ASC_SG_LIST_PER_Q - 1; 7961 scsi_sg_q.sg_cur_list_cnt = 7962 ASC_SG_LIST_PER_Q - 1; 7963 } 7964 } else { 7965 scsi_sg_q.cntl |= QCSG_SG_XFER_END; 7966 sg_list_dwords = sg_entry_cnt << 1; 7967 if (i == 0) { 7968 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 7969 scsi_sg_q.sg_cur_list_cnt = 7970 sg_entry_cnt; 7971 } else { 7972 scsi_sg_q.sg_list_cnt = 7973 sg_entry_cnt - 1; 7974 scsi_sg_q.sg_cur_list_cnt = 7975 sg_entry_cnt - 1; 7976 } 7977 sg_entry_cnt = 0; 7978 } 7979 next_qp = AscReadLramByte(iop_base, 7980 (ushort)(q_addr + 7981 ASC_SCSIQ_B_FWD)); 7982 scsi_sg_q.q_no = next_qp; 7983 q_addr = ASC_QNO_TO_QADDR(next_qp); 7984 AscMemWordCopyPtrToLram(iop_base, 7985 q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 7986 (uchar *)&scsi_sg_q, 7987 sizeof(ASC_SG_LIST_Q) >> 1); 7988 AscMemDWordCopyPtrToLram(iop_base, 7989 q_addr + ASC_SGQ_LIST_BEG, 7990 (uchar *)&sg_head-> 7991 sg_list[sg_index], 7992 sg_list_dwords); 7993 sg_index += ASC_SG_LIST_PER_Q; 7994 scsiq->next_sg_index = sg_index; 7995 } 7996 } else { 7997 scsiq->q1.cntl &= ~QC_SG_HEAD; 7998 } 7999 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no); 8000 scsiq->q1.data_addr = saved_data_addr; 8001 scsiq->q1.data_cnt = saved_data_cnt; 8002 return (sta); 8003 } 8004 8005 static int 8006 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required) 8007 { 8008 PortAddr iop_base; 8009 uchar free_q_head; 8010 uchar next_qp; 8011 uchar tid_no; 8012 uchar target_ix; 8013 int sta; 8014 8015 iop_base = asc_dvc->iop_base; 8016 target_ix = scsiq->q2.target_ix; 8017 tid_no = ASC_TIX_TO_TID(target_ix); 8018 sta = 0; 8019 free_q_head = (uchar)AscGetVarFreeQHead(iop_base); 8020 if (n_q_required > 1) { 8021 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head, 8022 (uchar)n_q_required); 8023 if (next_qp != ASC_QLINK_END) { 8024 asc_dvc->last_q_shortage = 0; 8025 scsiq->sg_head->queue_cnt = n_q_required - 1; 8026 scsiq->q1.q_no = free_q_head; 8027 sta = AscPutReadySgListQueue(asc_dvc, scsiq, 8028 free_q_head); 8029 } 8030 } else if (n_q_required == 1) { 8031 next_qp = AscAllocFreeQueue(iop_base, free_q_head); 8032 if (next_qp != ASC_QLINK_END) { 8033 scsiq->q1.q_no = free_q_head; 8034 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head); 8035 } 8036 } 8037 if (sta == 1) { 8038 AscPutVarFreeQHead(iop_base, next_qp); 8039 asc_dvc->cur_total_qng += n_q_required; 8040 asc_dvc->cur_dvc_qng[tid_no]++; 8041 } 8042 return sta; 8043 } 8044 8045 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16 8046 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = { 8047 INQUIRY, 8048 REQUEST_SENSE, 8049 READ_CAPACITY, 8050 READ_TOC, 8051 MODE_SELECT, 8052 MODE_SENSE, 8053 MODE_SELECT_10, 8054 MODE_SENSE_10, 8055 0xFF, 8056 0xFF, 8057 0xFF, 8058 0xFF, 8059 0xFF, 8060 0xFF, 8061 0xFF, 8062 0xFF 8063 }; 8064 8065 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) 8066 { 8067 PortAddr iop_base; 8068 int sta; 8069 int n_q_required; 8070 bool disable_syn_offset_one_fix; 8071 int i; 8072 u32 addr; 8073 ushort sg_entry_cnt = 0; 8074 ushort sg_entry_cnt_minus_one = 0; 8075 uchar target_ix; 8076 uchar tid_no; 8077 uchar sdtr_data; 8078 uchar extra_bytes; 8079 uchar scsi_cmd; 8080 uchar disable_cmd; 8081 ASC_SG_HEAD *sg_head; 8082 unsigned long data_cnt; 8083 8084 iop_base = asc_dvc->iop_base; 8085 sg_head = scsiq->sg_head; 8086 if (asc_dvc->err_code != 0) 8087 return ASC_ERROR; 8088 scsiq->q1.q_no = 0; 8089 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) { 8090 scsiq->q1.extra_bytes = 0; 8091 } 8092 sta = 0; 8093 target_ix = scsiq->q2.target_ix; 8094 tid_no = ASC_TIX_TO_TID(target_ix); 8095 n_q_required = 1; 8096 if (scsiq->cdbptr[0] == REQUEST_SENSE) { 8097 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) { 8098 asc_dvc->sdtr_done &= ~scsiq->q1.target_id; 8099 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 8100 AscMsgOutSDTR(asc_dvc, 8101 asc_dvc-> 8102 sdtr_period_tbl[(sdtr_data >> 4) & 8103 (uchar)(asc_dvc-> 8104 max_sdtr_index - 8105 1)], 8106 (uchar)(sdtr_data & (uchar) 8107 ASC_SYN_MAX_OFFSET)); 8108 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT); 8109 } 8110 } 8111 if (asc_dvc->in_critical_cnt != 0) { 8112 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY); 8113 return ASC_ERROR; 8114 } 8115 asc_dvc->in_critical_cnt++; 8116 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { 8117 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) { 8118 asc_dvc->in_critical_cnt--; 8119 return ASC_ERROR; 8120 } 8121 if (sg_entry_cnt > ASC_MAX_SG_LIST) { 8122 asc_dvc->in_critical_cnt--; 8123 return ASC_ERROR; 8124 } 8125 if (sg_entry_cnt == 1) { 8126 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr); 8127 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes); 8128 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE); 8129 } 8130 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 8131 } 8132 scsi_cmd = scsiq->cdbptr[0]; 8133 disable_syn_offset_one_fix = false; 8134 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 8135 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 8136 if (scsiq->q1.cntl & QC_SG_HEAD) { 8137 data_cnt = 0; 8138 for (i = 0; i < sg_entry_cnt; i++) { 8139 data_cnt += le32_to_cpu(sg_head->sg_list[i]. 8140 bytes); 8141 } 8142 } else { 8143 data_cnt = le32_to_cpu(scsiq->q1.data_cnt); 8144 } 8145 if (data_cnt != 0UL) { 8146 if (data_cnt < 512UL) { 8147 disable_syn_offset_one_fix = true; 8148 } else { 8149 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; 8150 i++) { 8151 disable_cmd = 8152 _syn_offset_one_disable_cmd[i]; 8153 if (disable_cmd == 0xFF) { 8154 break; 8155 } 8156 if (scsi_cmd == disable_cmd) { 8157 disable_syn_offset_one_fix = 8158 true; 8159 break; 8160 } 8161 } 8162 } 8163 } 8164 } 8165 if (disable_syn_offset_one_fix) { 8166 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG; 8167 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 8168 ASC_TAG_FLAG_DISABLE_DISCONNECT); 8169 } else { 8170 scsiq->q2.tag_code &= 0x27; 8171 } 8172 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { 8173 if (asc_dvc->bug_fix_cntl) { 8174 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 8175 if ((scsi_cmd == READ_6) || 8176 (scsi_cmd == READ_10)) { 8177 addr = le32_to_cpu(sg_head-> 8178 sg_list 8179 [sg_entry_cnt_minus_one]. 8180 addr) + 8181 le32_to_cpu(sg_head-> 8182 sg_list 8183 [sg_entry_cnt_minus_one]. 8184 bytes); 8185 extra_bytes = 8186 (uchar)((ushort)addr & 0x0003); 8187 if ((extra_bytes != 0) 8188 && 8189 ((scsiq->q2. 8190 tag_code & 8191 ASC_TAG_FLAG_EXTRA_BYTES) 8192 == 0)) { 8193 scsiq->q2.tag_code |= 8194 ASC_TAG_FLAG_EXTRA_BYTES; 8195 scsiq->q1.extra_bytes = 8196 extra_bytes; 8197 data_cnt = 8198 le32_to_cpu(sg_head-> 8199 sg_list 8200 [sg_entry_cnt_minus_one]. 8201 bytes); 8202 data_cnt -= extra_bytes; 8203 sg_head-> 8204 sg_list 8205 [sg_entry_cnt_minus_one]. 8206 bytes = 8207 cpu_to_le32(data_cnt); 8208 } 8209 } 8210 } 8211 } 8212 sg_head->entry_to_copy = sg_head->entry_cnt; 8213 n_q_required = AscSgListToQueue(sg_entry_cnt); 8214 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >= 8215 (uint) n_q_required) 8216 || ((scsiq->q1.cntl & QC_URGENT) != 0)) { 8217 if ((sta = 8218 AscSendScsiQueue(asc_dvc, scsiq, 8219 n_q_required)) == 1) { 8220 asc_dvc->in_critical_cnt--; 8221 return (sta); 8222 } 8223 } 8224 } else { 8225 if (asc_dvc->bug_fix_cntl) { 8226 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 8227 if ((scsi_cmd == READ_6) || 8228 (scsi_cmd == READ_10)) { 8229 addr = 8230 le32_to_cpu(scsiq->q1.data_addr) + 8231 le32_to_cpu(scsiq->q1.data_cnt); 8232 extra_bytes = 8233 (uchar)((ushort)addr & 0x0003); 8234 if ((extra_bytes != 0) 8235 && 8236 ((scsiq->q2. 8237 tag_code & 8238 ASC_TAG_FLAG_EXTRA_BYTES) 8239 == 0)) { 8240 data_cnt = 8241 le32_to_cpu(scsiq->q1. 8242 data_cnt); 8243 if (((ushort)data_cnt & 0x01FF) 8244 == 0) { 8245 scsiq->q2.tag_code |= 8246 ASC_TAG_FLAG_EXTRA_BYTES; 8247 data_cnt -= extra_bytes; 8248 scsiq->q1.data_cnt = 8249 cpu_to_le32 8250 (data_cnt); 8251 scsiq->q1.extra_bytes = 8252 extra_bytes; 8253 } 8254 } 8255 } 8256 } 8257 } 8258 n_q_required = 1; 8259 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) || 8260 ((scsiq->q1.cntl & QC_URGENT) != 0)) { 8261 if ((sta = AscSendScsiQueue(asc_dvc, scsiq, 8262 n_q_required)) == 1) { 8263 asc_dvc->in_critical_cnt--; 8264 return (sta); 8265 } 8266 } 8267 } 8268 asc_dvc->in_critical_cnt--; 8269 return (sta); 8270 } 8271 8272 /* 8273 * AdvExeScsiQueue() - Send a request to the RISC microcode program. 8274 * 8275 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q, 8276 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 8277 * RISC to notify it a new command is ready to be executed. 8278 * 8279 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 8280 * set to SCSI_MAX_RETRY. 8281 * 8282 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the microcode 8283 * for DMA addresses or math operations are byte swapped to little-endian 8284 * order. 8285 * 8286 * Return: 8287 * ADV_SUCCESS(1) - The request was successfully queued. 8288 * ADV_BUSY(0) - Resource unavailable; Retry again after pending 8289 * request completes. 8290 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure 8291 * host IC error. 8292 */ 8293 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp) 8294 { 8295 AdvPortAddr iop_base; 8296 ADV_CARR_T *new_carrp; 8297 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q; 8298 8299 /* 8300 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID. 8301 */ 8302 if (scsiq->target_id > ADV_MAX_TID) { 8303 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 8304 scsiq->done_status = QD_WITH_ERROR; 8305 return ADV_ERROR; 8306 } 8307 8308 iop_base = asc_dvc->iop_base; 8309 8310 /* 8311 * Allocate a carrier ensuring at least one carrier always 8312 * remains on the freelist and initialize fields. 8313 */ 8314 new_carrp = adv_get_next_carrier(asc_dvc); 8315 if (!new_carrp) { 8316 ASC_DBG(1, "No free carriers\n"); 8317 return ADV_BUSY; 8318 } 8319 8320 asc_dvc->carr_pending_cnt++; 8321 8322 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */ 8323 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag); 8324 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr); 8325 8326 scsiq->carr_va = asc_dvc->icq_sp->carr_va; 8327 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa; 8328 8329 /* 8330 * Use the current stopper to send the ADV_SCSI_REQ_Q command to 8331 * the microcode. The newly allocated stopper will become the new 8332 * stopper. 8333 */ 8334 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr; 8335 8336 /* 8337 * Set the 'next_vpa' pointer for the old stopper to be the 8338 * physical address of the new stopper. The RISC can only 8339 * follow physical addresses. 8340 */ 8341 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa; 8342 8343 /* 8344 * Set the host adapter stopper pointer to point to the new carrier. 8345 */ 8346 asc_dvc->icq_sp = new_carrp; 8347 8348 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 || 8349 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 8350 /* 8351 * Tickle the RISC to tell it to read its Command Queue Head pointer. 8352 */ 8353 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A); 8354 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 8355 /* 8356 * Clear the tickle value. In the ASC-3550 the RISC flag 8357 * command 'clr_tickle_a' does not work unless the host 8358 * value is cleared. 8359 */ 8360 AdvWriteByteRegister(iop_base, IOPB_TICKLE, 8361 ADV_TICKLE_NOP); 8362 } 8363 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 8364 /* 8365 * Notify the RISC a carrier is ready by writing the physical 8366 * address of the new carrier stopper to the COMMA register. 8367 */ 8368 AdvWriteDWordRegister(iop_base, IOPDW_COMMA, 8369 le32_to_cpu(new_carrp->carr_pa)); 8370 } 8371 8372 return ADV_SUCCESS; 8373 } 8374 8375 /* 8376 * Execute a single 'struct scsi_cmnd'. 8377 */ 8378 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp) 8379 { 8380 int ret, err_code; 8381 struct asc_board *boardp = shost_priv(scp->device->host); 8382 8383 ASC_DBG(1, "scp 0x%p\n", scp); 8384 8385 if (ASC_NARROW_BOARD(boardp)) { 8386 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var; 8387 struct asc_scsi_q asc_scsi_q; 8388 8389 ret = asc_build_req(boardp, scp, &asc_scsi_q); 8390 if (ret != ASC_NOERROR) { 8391 ASC_STATS(scp->device->host, build_error); 8392 return ret; 8393 } 8394 8395 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q); 8396 kfree(asc_scsi_q.sg_head); 8397 err_code = asc_dvc->err_code; 8398 } else { 8399 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var; 8400 adv_req_t *adv_reqp; 8401 8402 switch (adv_build_req(boardp, scp, &adv_reqp)) { 8403 case ASC_NOERROR: 8404 ASC_DBG(3, "adv_build_req ASC_NOERROR\n"); 8405 break; 8406 case ASC_BUSY: 8407 ASC_DBG(1, "adv_build_req ASC_BUSY\n"); 8408 /* 8409 * The asc_stats fields 'adv_build_noreq' and 8410 * 'adv_build_nosg' count wide board busy conditions. 8411 * They are updated in adv_build_req and 8412 * adv_get_sglist, respectively. 8413 */ 8414 return ASC_BUSY; 8415 case ASC_ERROR: 8416 default: 8417 ASC_DBG(1, "adv_build_req ASC_ERROR\n"); 8418 ASC_STATS(scp->device->host, build_error); 8419 return ASC_ERROR; 8420 } 8421 8422 ret = AdvExeScsiQueue(adv_dvc, adv_reqp); 8423 err_code = adv_dvc->err_code; 8424 } 8425 8426 switch (ret) { 8427 case ASC_NOERROR: 8428 ASC_STATS(scp->device->host, exe_noerror); 8429 /* 8430 * Increment monotonically increasing per device 8431 * successful request counter. Wrapping doesn't matter. 8432 */ 8433 boardp->reqcnt[scp->device->id]++; 8434 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n"); 8435 break; 8436 case ASC_BUSY: 8437 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n"); 8438 ASC_STATS(scp->device->host, exe_busy); 8439 break; 8440 case ASC_ERROR: 8441 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, " 8442 "err_code 0x%x\n", err_code); 8443 ASC_STATS(scp->device->host, exe_error); 8444 set_host_byte(scp, DID_ERROR); 8445 break; 8446 default: 8447 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, " 8448 "err_code 0x%x\n", err_code); 8449 ASC_STATS(scp->device->host, exe_unknown); 8450 set_host_byte(scp, DID_ERROR); 8451 break; 8452 } 8453 8454 ASC_DBG(1, "end\n"); 8455 return ret; 8456 } 8457 8458 /* 8459 * advansys_queuecommand() - interrupt-driven I/O entrypoint. 8460 * 8461 * This function always returns 0. Command return status is saved 8462 * in the 'scp' result field. 8463 */ 8464 static enum scsi_qc_status advansys_queuecommand_lck(struct scsi_cmnd *scp) 8465 { 8466 struct Scsi_Host *shost = scp->device->host; 8467 enum scsi_qc_status result = 0; 8468 int asc_res; 8469 8470 ASC_STATS(shost, queuecommand); 8471 8472 asc_res = asc_execute_scsi_cmnd(scp); 8473 8474 switch (asc_res) { 8475 case ASC_NOERROR: 8476 break; 8477 case ASC_BUSY: 8478 result = SCSI_MLQUEUE_HOST_BUSY; 8479 break; 8480 case ASC_ERROR: 8481 default: 8482 asc_scsi_done(scp); 8483 break; 8484 } 8485 8486 return result; 8487 } 8488 8489 static DEF_SCSI_QCMD(advansys_queuecommand) 8490 8491 static ushort AscGetEisaChipCfg(PortAddr iop_base) 8492 { 8493 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) | 8494 (PortAddr) (ASC_EISA_CFG_IOP_MASK); 8495 return inpw(eisa_cfg_iop); 8496 } 8497 8498 /* 8499 * Return the BIOS address of the adapter at the specified 8500 * I/O port and with the specified bus type. 8501 */ 8502 static unsigned short AscGetChipBiosAddress(PortAddr iop_base, 8503 unsigned short bus_type) 8504 { 8505 unsigned short cfg_lsw; 8506 unsigned short bios_addr; 8507 8508 /* 8509 * The PCI BIOS is re-located by the motherboard BIOS. Because 8510 * of this the driver can not determine where a PCI BIOS is 8511 * loaded and executes. 8512 */ 8513 if (bus_type & ASC_IS_PCI) 8514 return 0; 8515 8516 if ((bus_type & ASC_IS_EISA) != 0) { 8517 cfg_lsw = AscGetEisaChipCfg(iop_base); 8518 cfg_lsw &= 0x000F; 8519 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE; 8520 return bios_addr; 8521 } 8522 8523 cfg_lsw = AscGetChipCfgLsw(iop_base); 8524 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE; 8525 return bios_addr; 8526 } 8527 8528 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id) 8529 { 8530 ushort cfg_lsw; 8531 8532 if (AscGetChipScsiID(iop_base) == new_host_id) { 8533 return (new_host_id); 8534 } 8535 cfg_lsw = AscGetChipCfgLsw(iop_base); 8536 cfg_lsw &= 0xF8FF; 8537 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8); 8538 AscSetChipCfgLsw(iop_base, cfg_lsw); 8539 return (AscGetChipScsiID(iop_base)); 8540 } 8541 8542 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base) 8543 { 8544 unsigned char sc; 8545 8546 AscSetBank(iop_base, 1); 8547 sc = inp(iop_base + IOP_REG_SC); 8548 AscSetBank(iop_base, 0); 8549 return sc; 8550 } 8551 8552 static unsigned char AscGetChipVersion(PortAddr iop_base, 8553 unsigned short bus_type) 8554 { 8555 if (bus_type & ASC_IS_EISA) { 8556 PortAddr eisa_iop; 8557 unsigned char revision; 8558 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) | 8559 (PortAddr) ASC_EISA_REV_IOP_MASK; 8560 revision = inp(eisa_iop); 8561 return ASC_CHIP_MIN_VER_EISA - 1 + revision; 8562 } 8563 return AscGetChipVerNo(iop_base); 8564 } 8565 8566 static int AscStopQueueExe(PortAddr iop_base) 8567 { 8568 int count = 0; 8569 8570 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) { 8571 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 8572 ASC_STOP_REQ_RISC_STOP); 8573 do { 8574 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) & 8575 ASC_STOP_ACK_RISC_STOP) { 8576 return (1); 8577 } 8578 mdelay(100); 8579 } while (count++ < 20); 8580 } 8581 return (0); 8582 } 8583 8584 static unsigned int AscGetMaxDmaCount(ushort bus_type) 8585 { 8586 if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 8587 return ASC_MAX_VL_DMA_COUNT; 8588 return ASC_MAX_PCI_DMA_COUNT; 8589 } 8590 8591 static void AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc) 8592 { 8593 int i; 8594 PortAddr iop_base; 8595 uchar chip_version; 8596 8597 iop_base = asc_dvc->iop_base; 8598 asc_dvc->err_code = 0; 8599 if ((asc_dvc->bus_type & 8600 (ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) { 8601 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE; 8602 } 8603 AscSetChipControl(iop_base, CC_HALT); 8604 AscSetChipStatus(iop_base, 0); 8605 asc_dvc->bug_fix_cntl = 0; 8606 asc_dvc->pci_fix_asyn_xfer = 0; 8607 asc_dvc->pci_fix_asyn_xfer_always = 0; 8608 /* asc_dvc->init_state initialized in AscInitGetConfig(). */ 8609 asc_dvc->sdtr_done = 0; 8610 asc_dvc->cur_total_qng = 0; 8611 asc_dvc->is_in_int = false; 8612 asc_dvc->in_critical_cnt = 0; 8613 asc_dvc->last_q_shortage = 0; 8614 asc_dvc->use_tagged_qng = 0; 8615 asc_dvc->no_scam = 0; 8616 asc_dvc->unit_not_ready = 0; 8617 asc_dvc->queue_full_or_busy = 0; 8618 asc_dvc->redo_scam = 0; 8619 asc_dvc->res2 = 0; 8620 asc_dvc->min_sdtr_index = 0; 8621 asc_dvc->cfg->can_tagged_qng = 0; 8622 asc_dvc->cfg->cmd_qng_enabled = 0; 8623 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL; 8624 asc_dvc->init_sdtr = 0; 8625 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 8626 asc_dvc->scsi_reset_wait = 3; 8627 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 8628 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type); 8629 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 8630 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 8631 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 8632 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type); 8633 asc_dvc->cfg->chip_version = chip_version; 8634 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period; 8635 asc_dvc->max_sdtr_index = 7; 8636 if ((asc_dvc->bus_type & ASC_IS_PCI) && 8637 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 8638 asc_dvc->bus_type = ASC_IS_PCI_ULTRA; 8639 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period; 8640 asc_dvc->max_sdtr_index = 15; 8641 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) { 8642 AscSetExtraControl(iop_base, 8643 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 8644 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) { 8645 AscSetExtraControl(iop_base, 8646 (SEC_ACTIVE_NEGATE | 8647 SEC_ENABLE_FILTER)); 8648 } 8649 } 8650 if (asc_dvc->bus_type == ASC_IS_PCI) { 8651 AscSetExtraControl(iop_base, 8652 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 8653 } 8654 8655 for (i = 0; i <= ASC_MAX_TID; i++) { 8656 asc_dvc->cur_dvc_qng[i] = 0; 8657 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 8658 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L; 8659 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L; 8660 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 8661 } 8662 } 8663 8664 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg) 8665 { 8666 int retry; 8667 8668 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) { 8669 unsigned char read_back; 8670 AscSetChipEEPCmd(iop_base, cmd_reg); 8671 mdelay(1); 8672 read_back = AscGetChipEEPCmd(iop_base); 8673 if (read_back == cmd_reg) 8674 return 1; 8675 } 8676 return 0; 8677 } 8678 8679 static void AscWaitEEPRead(void) 8680 { 8681 mdelay(1); 8682 } 8683 8684 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr) 8685 { 8686 ushort read_wval; 8687 uchar cmd_reg; 8688 8689 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE); 8690 AscWaitEEPRead(); 8691 cmd_reg = addr | ASC_EEP_CMD_READ; 8692 AscWriteEEPCmdReg(iop_base, cmd_reg); 8693 AscWaitEEPRead(); 8694 read_wval = AscGetChipEEPData(iop_base); 8695 AscWaitEEPRead(); 8696 return read_wval; 8697 } 8698 8699 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, 8700 ushort bus_type) 8701 { 8702 ushort wval; 8703 ushort sum; 8704 ushort *wbuf; 8705 int cfg_beg; 8706 int cfg_end; 8707 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2; 8708 int s_addr; 8709 8710 wbuf = (ushort *)cfg_buf; 8711 sum = 0; 8712 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */ 8713 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 8714 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr); 8715 sum += *wbuf; 8716 } 8717 if (bus_type & ASC_IS_VL) { 8718 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 8719 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 8720 } else { 8721 cfg_beg = ASC_EEP_DVC_CFG_BEG; 8722 cfg_end = ASC_EEP_MAX_DVC_ADDR; 8723 } 8724 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 8725 wval = AscReadEEPWord(iop_base, (uchar)s_addr); 8726 if (s_addr <= uchar_end_in_config) { 8727 /* 8728 * Swap all char fields - must unswap bytes already swapped 8729 * by AscReadEEPWord(). 8730 */ 8731 *wbuf = le16_to_cpu(wval); 8732 } else { 8733 /* Don't swap word field at the end - cntl field. */ 8734 *wbuf = wval; 8735 } 8736 sum += wval; /* Checksum treats all EEPROM data as words. */ 8737 } 8738 /* 8739 * Read the checksum word which will be compared against 'sum' 8740 * by the caller. Word field already swapped. 8741 */ 8742 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr); 8743 return sum; 8744 } 8745 8746 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc) 8747 { 8748 PortAddr iop_base; 8749 ushort q_addr; 8750 ushort saved_word; 8751 int sta; 8752 8753 iop_base = asc_dvc->iop_base; 8754 sta = 0; 8755 q_addr = ASC_QNO_TO_QADDR(241); 8756 saved_word = AscReadLramWord(iop_base, q_addr); 8757 AscSetChipLramAddr(iop_base, q_addr); 8758 AscSetChipLramData(iop_base, 0x55AA); 8759 mdelay(10); 8760 AscSetChipLramAddr(iop_base, q_addr); 8761 if (AscGetChipLramData(iop_base) == 0x55AA) { 8762 sta = 1; 8763 AscWriteLramWord(iop_base, q_addr, saved_word); 8764 } 8765 return (sta); 8766 } 8767 8768 static void AscWaitEEPWrite(void) 8769 { 8770 mdelay(20); 8771 } 8772 8773 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg) 8774 { 8775 ushort read_back; 8776 int retry; 8777 8778 retry = 0; 8779 while (true) { 8780 AscSetChipEEPData(iop_base, data_reg); 8781 mdelay(1); 8782 read_back = AscGetChipEEPData(iop_base); 8783 if (read_back == data_reg) { 8784 return (1); 8785 } 8786 if (retry++ > ASC_EEP_MAX_RETRY) { 8787 return (0); 8788 } 8789 } 8790 } 8791 8792 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val) 8793 { 8794 ushort read_wval; 8795 8796 read_wval = AscReadEEPWord(iop_base, addr); 8797 if (read_wval != word_val) { 8798 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE); 8799 AscWaitEEPRead(); 8800 AscWriteEEPDataReg(iop_base, word_val); 8801 AscWaitEEPRead(); 8802 AscWriteEEPCmdReg(iop_base, 8803 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr)); 8804 AscWaitEEPWrite(); 8805 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE); 8806 AscWaitEEPRead(); 8807 return (AscReadEEPWord(iop_base, addr)); 8808 } 8809 return (read_wval); 8810 } 8811 8812 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, 8813 ushort bus_type) 8814 { 8815 int n_error; 8816 ushort *wbuf; 8817 ushort word; 8818 ushort sum; 8819 int s_addr; 8820 int cfg_beg; 8821 int cfg_end; 8822 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2; 8823 8824 wbuf = (ushort *)cfg_buf; 8825 n_error = 0; 8826 sum = 0; 8827 /* Write two config words; AscWriteEEPWord() will swap bytes. */ 8828 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 8829 sum += *wbuf; 8830 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) { 8831 n_error++; 8832 } 8833 } 8834 if (bus_type & ASC_IS_VL) { 8835 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 8836 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 8837 } else { 8838 cfg_beg = ASC_EEP_DVC_CFG_BEG; 8839 cfg_end = ASC_EEP_MAX_DVC_ADDR; 8840 } 8841 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 8842 if (s_addr <= uchar_end_in_config) { 8843 /* 8844 * This is a char field. Swap char fields before they are 8845 * swapped again by AscWriteEEPWord(). 8846 */ 8847 word = cpu_to_le16(*wbuf); 8848 if (word != 8849 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) { 8850 n_error++; 8851 } 8852 } else { 8853 /* Don't swap word field at the end - cntl field. */ 8854 if (*wbuf != 8855 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) { 8856 n_error++; 8857 } 8858 } 8859 sum += *wbuf; /* Checksum calculated from word values. */ 8860 } 8861 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */ 8862 *wbuf = sum; 8863 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) { 8864 n_error++; 8865 } 8866 8867 /* Read EEPROM back again. */ 8868 wbuf = (ushort *)cfg_buf; 8869 /* 8870 * Read two config words; Byte-swapping done by AscReadEEPWord(). 8871 */ 8872 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 8873 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) { 8874 n_error++; 8875 } 8876 } 8877 if (bus_type & ASC_IS_VL) { 8878 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 8879 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 8880 } else { 8881 cfg_beg = ASC_EEP_DVC_CFG_BEG; 8882 cfg_end = ASC_EEP_MAX_DVC_ADDR; 8883 } 8884 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 8885 if (s_addr <= uchar_end_in_config) { 8886 /* 8887 * Swap all char fields. Must unswap bytes already swapped 8888 * by AscReadEEPWord(). 8889 */ 8890 word = 8891 le16_to_cpu(AscReadEEPWord 8892 (iop_base, (uchar)s_addr)); 8893 } else { 8894 /* Don't swap word field at the end - cntl field. */ 8895 word = AscReadEEPWord(iop_base, (uchar)s_addr); 8896 } 8897 if (*wbuf != word) { 8898 n_error++; 8899 } 8900 } 8901 /* Read checksum; Byte swapping not needed. */ 8902 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) { 8903 n_error++; 8904 } 8905 return n_error; 8906 } 8907 8908 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, 8909 ushort bus_type) 8910 { 8911 int retry; 8912 int n_error; 8913 8914 retry = 0; 8915 while (true) { 8916 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf, 8917 bus_type)) == 0) { 8918 break; 8919 } 8920 if (++retry > ASC_EEP_MAX_RETRY) { 8921 break; 8922 } 8923 } 8924 return n_error; 8925 } 8926 8927 static int AscInitFromEEP(ASC_DVC_VAR *asc_dvc) 8928 { 8929 ASCEEP_CONFIG eep_config_buf; 8930 ASCEEP_CONFIG *eep_config; 8931 PortAddr iop_base; 8932 ushort chksum; 8933 ushort warn_code; 8934 ushort cfg_msw, cfg_lsw; 8935 int i; 8936 int write_eep = 0; 8937 8938 iop_base = asc_dvc->iop_base; 8939 warn_code = 0; 8940 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE); 8941 AscStopQueueExe(iop_base); 8942 if ((AscStopChip(iop_base)) || 8943 (AscGetChipScsiCtrl(iop_base) != 0)) { 8944 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE; 8945 AscResetChipAndScsiBus(asc_dvc); 8946 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ 8947 } 8948 if (!AscIsChipHalted(iop_base)) { 8949 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; 8950 return (warn_code); 8951 } 8952 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR); 8953 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) { 8954 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR; 8955 return (warn_code); 8956 } 8957 eep_config = (ASCEEP_CONFIG *)&eep_config_buf; 8958 cfg_msw = AscGetChipCfgMsw(iop_base); 8959 cfg_lsw = AscGetChipCfgLsw(iop_base); 8960 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 8961 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 8962 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 8963 AscSetChipCfgMsw(iop_base, cfg_msw); 8964 } 8965 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type); 8966 ASC_DBG(1, "chksum 0x%x\n", chksum); 8967 if (chksum == 0) { 8968 chksum = 0xaa55; 8969 } 8970 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) { 8971 warn_code |= ASC_WARN_AUTO_CONFIG; 8972 if (asc_dvc->cfg->chip_version == 3) { 8973 if (eep_config->cfg_lsw != cfg_lsw) { 8974 warn_code |= ASC_WARN_EEPROM_RECOVER; 8975 eep_config->cfg_lsw = 8976 AscGetChipCfgLsw(iop_base); 8977 } 8978 if (eep_config->cfg_msw != cfg_msw) { 8979 warn_code |= ASC_WARN_EEPROM_RECOVER; 8980 eep_config->cfg_msw = 8981 AscGetChipCfgMsw(iop_base); 8982 } 8983 } 8984 } 8985 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 8986 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 8987 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum); 8988 if (chksum != eep_config->chksum) { 8989 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) == 8990 ASC_CHIP_VER_PCI_ULTRA_3050) { 8991 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n"); 8992 eep_config->init_sdtr = 0xFF; 8993 eep_config->disc_enable = 0xFF; 8994 eep_config->start_motor = 0xFF; 8995 eep_config->use_cmd_qng = 0; 8996 eep_config->max_total_qng = 0xF0; 8997 eep_config->max_tag_qng = 0x20; 8998 eep_config->cntl = 0xBFFF; 8999 ASC_EEP_SET_CHIP_ID(eep_config, 7); 9000 eep_config->no_scam = 0; 9001 eep_config->adapter_info[0] = 0; 9002 eep_config->adapter_info[1] = 0; 9003 eep_config->adapter_info[2] = 0; 9004 eep_config->adapter_info[3] = 0; 9005 eep_config->adapter_info[4] = 0; 9006 /* Indicate EEPROM-less board. */ 9007 eep_config->adapter_info[5] = 0xBB; 9008 } else { 9009 ASC_PRINT 9010 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n"); 9011 write_eep = 1; 9012 warn_code |= ASC_WARN_EEPROM_CHKSUM; 9013 } 9014 } 9015 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr; 9016 asc_dvc->cfg->disc_enable = eep_config->disc_enable; 9017 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng; 9018 asc_dvc->start_motor = eep_config->start_motor; 9019 asc_dvc->dvc_cntl = eep_config->cntl; 9020 asc_dvc->no_scam = eep_config->no_scam; 9021 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0]; 9022 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1]; 9023 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2]; 9024 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3]; 9025 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4]; 9026 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5]; 9027 if (!AscTestExternalLram(asc_dvc)) { 9028 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == 9029 ASC_IS_PCI_ULTRA)) { 9030 eep_config->max_total_qng = 9031 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 9032 eep_config->max_tag_qng = 9033 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 9034 } else { 9035 eep_config->cfg_msw |= 0x0800; 9036 cfg_msw |= 0x0800; 9037 AscSetChipCfgMsw(iop_base, cfg_msw); 9038 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 9039 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 9040 } 9041 } else { 9042 } 9043 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) { 9044 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 9045 } 9046 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) { 9047 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 9048 } 9049 if (eep_config->max_tag_qng > eep_config->max_total_qng) { 9050 eep_config->max_tag_qng = eep_config->max_total_qng; 9051 } 9052 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) { 9053 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 9054 } 9055 asc_dvc->max_total_qng = eep_config->max_total_qng; 9056 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 9057 eep_config->use_cmd_qng) { 9058 eep_config->disc_enable = eep_config->use_cmd_qng; 9059 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 9060 } 9061 ASC_EEP_SET_CHIP_ID(eep_config, 9062 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID); 9063 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config); 9064 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 9065 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 9066 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 9067 } 9068 9069 for (i = 0; i <= ASC_MAX_TID; i++) { 9070 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i]; 9071 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng; 9072 asc_dvc->cfg->sdtr_period_offset[i] = 9073 (uchar)(ASC_DEF_SDTR_OFFSET | 9074 (asc_dvc->min_sdtr_index << 4)); 9075 } 9076 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base); 9077 if (write_eep) { 9078 if ((i = AscSetEEPConfig(iop_base, eep_config, 9079 asc_dvc->bus_type)) != 0) { 9080 ASC_PRINT1 9081 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n", 9082 i); 9083 } else { 9084 ASC_PRINT 9085 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n"); 9086 } 9087 } 9088 return (warn_code); 9089 } 9090 9091 static int AscInitGetConfig(struct Scsi_Host *shost) 9092 { 9093 struct asc_board *board = shost_priv(shost); 9094 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var; 9095 unsigned short warn_code = 0; 9096 9097 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG; 9098 if (asc_dvc->err_code != 0) 9099 return asc_dvc->err_code; 9100 9101 if (AscFindSignature(asc_dvc->iop_base)) { 9102 AscInitAscDvcVar(asc_dvc); 9103 warn_code = AscInitFromEEP(asc_dvc); 9104 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG; 9105 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT) 9106 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT; 9107 } else { 9108 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 9109 } 9110 9111 switch (warn_code) { 9112 case 0: /* No error */ 9113 break; 9114 case ASC_WARN_IO_PORT_ROTATE: 9115 shost_printk(KERN_WARNING, shost, "I/O port address " 9116 "modified\n"); 9117 break; 9118 case ASC_WARN_AUTO_CONFIG: 9119 shost_printk(KERN_WARNING, shost, "I/O port increment switch " 9120 "enabled\n"); 9121 break; 9122 case ASC_WARN_EEPROM_CHKSUM: 9123 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n"); 9124 break; 9125 case ASC_WARN_IRQ_MODIFIED: 9126 shost_printk(KERN_WARNING, shost, "IRQ modified\n"); 9127 break; 9128 case ASC_WARN_CMD_QNG_CONFLICT: 9129 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o " 9130 "disconnects\n"); 9131 break; 9132 default: 9133 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n", 9134 warn_code); 9135 break; 9136 } 9137 9138 if (asc_dvc->err_code != 0) 9139 shost_printk(KERN_ERR, shost, "error 0x%x at init_state " 9140 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state); 9141 9142 return asc_dvc->err_code; 9143 } 9144 9145 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost) 9146 { 9147 struct asc_board *board = shost_priv(shost); 9148 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var; 9149 PortAddr iop_base = asc_dvc->iop_base; 9150 unsigned short cfg_msw; 9151 unsigned short warn_code = 0; 9152 9153 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG; 9154 if (asc_dvc->err_code != 0) 9155 return asc_dvc->err_code; 9156 if (!AscFindSignature(asc_dvc->iop_base)) { 9157 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 9158 return asc_dvc->err_code; 9159 } 9160 9161 cfg_msw = AscGetChipCfgMsw(iop_base); 9162 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 9163 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 9164 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 9165 AscSetChipCfgMsw(iop_base, cfg_msw); 9166 } 9167 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) != 9168 asc_dvc->cfg->cmd_qng_enabled) { 9169 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled; 9170 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 9171 } 9172 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) { 9173 warn_code |= ASC_WARN_AUTO_CONFIG; 9174 } 9175 #ifdef CONFIG_PCI 9176 if (asc_dvc->bus_type & ASC_IS_PCI) { 9177 cfg_msw &= 0xFFC0; 9178 AscSetChipCfgMsw(iop_base, cfg_msw); 9179 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) { 9180 } else { 9181 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) || 9182 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) { 9183 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 9184 asc_dvc->bug_fix_cntl |= 9185 ASC_BUG_FIX_ASYN_USE_SYN; 9186 } 9187 } 9188 } else 9189 #endif /* CONFIG_PCI */ 9190 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) != 9191 asc_dvc->cfg->chip_scsi_id) { 9192 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID; 9193 } 9194 9195 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG; 9196 9197 switch (warn_code) { 9198 case 0: /* No error. */ 9199 break; 9200 case ASC_WARN_IO_PORT_ROTATE: 9201 shost_printk(KERN_WARNING, shost, "I/O port address " 9202 "modified\n"); 9203 break; 9204 case ASC_WARN_AUTO_CONFIG: 9205 shost_printk(KERN_WARNING, shost, "I/O port increment switch " 9206 "enabled\n"); 9207 break; 9208 case ASC_WARN_EEPROM_CHKSUM: 9209 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n"); 9210 break; 9211 case ASC_WARN_IRQ_MODIFIED: 9212 shost_printk(KERN_WARNING, shost, "IRQ modified\n"); 9213 break; 9214 case ASC_WARN_CMD_QNG_CONFLICT: 9215 shost_printk(KERN_WARNING, shost, "tag queuing w/o " 9216 "disconnects\n"); 9217 break; 9218 default: 9219 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n", 9220 warn_code); 9221 break; 9222 } 9223 9224 if (asc_dvc->err_code != 0) 9225 shost_printk(KERN_ERR, shost, "error 0x%x at init_state " 9226 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state); 9227 9228 return asc_dvc->err_code; 9229 } 9230 9231 /* 9232 * EEPROM Configuration. 9233 * 9234 * All drivers should use this structure to set the default EEPROM 9235 * configuration. The BIOS now uses this structure when it is built. 9236 * Additional structure information can be found in a_condor.h where 9237 * the structure is defined. 9238 * 9239 * The *_Field_IsChar structs are needed to correct for endianness. 9240 * These values are read from the board 16 bits at a time directly 9241 * into the structs. Because some fields are char, the values will be 9242 * in the wrong order. The *_Field_IsChar tells when to flip the 9243 * bytes. Data read and written to PCI memory is automatically swapped 9244 * on big-endian platforms so char fields read as words are actually being 9245 * unswapped on big-endian platforms. 9246 */ 9247 #ifdef CONFIG_PCI 9248 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = { 9249 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */ 9250 0x0000, /* cfg_msw */ 9251 0xFFFF, /* disc_enable */ 9252 0xFFFF, /* wdtr_able */ 9253 0xFFFF, /* sdtr_able */ 9254 0xFFFF, /* start_motor */ 9255 0xFFFF, /* tagqng_able */ 9256 0xFFFF, /* bios_scan */ 9257 0, /* scam_tolerant */ 9258 7, /* adapter_scsi_id */ 9259 0, /* bios_boot_delay */ 9260 3, /* scsi_reset_delay */ 9261 0, /* bios_id_lun */ 9262 0, /* termination */ 9263 0, /* reserved1 */ 9264 0xFFE7, /* bios_ctrl */ 9265 0xFFFF, /* ultra_able */ 9266 0, /* reserved2 */ 9267 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ 9268 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 9269 0, /* dvc_cntl */ 9270 0, /* bug_fix */ 9271 0, /* serial_number_word1 */ 9272 0, /* serial_number_word2 */ 9273 0, /* serial_number_word3 */ 9274 0, /* check_sum */ 9275 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 9276 , /* oem_name[16] */ 9277 0, /* dvc_err_code */ 9278 0, /* adv_err_code */ 9279 0, /* adv_err_addr */ 9280 0, /* saved_dvc_err_code */ 9281 0, /* saved_adv_err_code */ 9282 0, /* saved_adv_err_addr */ 9283 0 /* num_of_err */ 9284 }; 9285 9286 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = { 9287 0, /* cfg_lsw */ 9288 0, /* cfg_msw */ 9289 0, /* -disc_enable */ 9290 0, /* wdtr_able */ 9291 0, /* sdtr_able */ 9292 0, /* start_motor */ 9293 0, /* tagqng_able */ 9294 0, /* bios_scan */ 9295 0, /* scam_tolerant */ 9296 1, /* adapter_scsi_id */ 9297 1, /* bios_boot_delay */ 9298 1, /* scsi_reset_delay */ 9299 1, /* bios_id_lun */ 9300 1, /* termination */ 9301 1, /* reserved1 */ 9302 0, /* bios_ctrl */ 9303 0, /* ultra_able */ 9304 0, /* reserved2 */ 9305 1, /* max_host_qng */ 9306 1, /* max_dvc_qng */ 9307 0, /* dvc_cntl */ 9308 0, /* bug_fix */ 9309 0, /* serial_number_word1 */ 9310 0, /* serial_number_word2 */ 9311 0, /* serial_number_word3 */ 9312 0, /* check_sum */ 9313 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 9314 , /* oem_name[16] */ 9315 0, /* dvc_err_code */ 9316 0, /* adv_err_code */ 9317 0, /* adv_err_addr */ 9318 0, /* saved_dvc_err_code */ 9319 0, /* saved_adv_err_code */ 9320 0, /* saved_adv_err_addr */ 9321 0 /* num_of_err */ 9322 }; 9323 9324 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = { 9325 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 9326 0x0000, /* 01 cfg_msw */ 9327 0xFFFF, /* 02 disc_enable */ 9328 0xFFFF, /* 03 wdtr_able */ 9329 0x4444, /* 04 sdtr_speed1 */ 9330 0xFFFF, /* 05 start_motor */ 9331 0xFFFF, /* 06 tagqng_able */ 9332 0xFFFF, /* 07 bios_scan */ 9333 0, /* 08 scam_tolerant */ 9334 7, /* 09 adapter_scsi_id */ 9335 0, /* bios_boot_delay */ 9336 3, /* 10 scsi_reset_delay */ 9337 0, /* bios_id_lun */ 9338 0, /* 11 termination_se */ 9339 0, /* termination_lvd */ 9340 0xFFE7, /* 12 bios_ctrl */ 9341 0x4444, /* 13 sdtr_speed2 */ 9342 0x4444, /* 14 sdtr_speed3 */ 9343 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 9344 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 9345 0, /* 16 dvc_cntl */ 9346 0x4444, /* 17 sdtr_speed4 */ 9347 0, /* 18 serial_number_word1 */ 9348 0, /* 19 serial_number_word2 */ 9349 0, /* 20 serial_number_word3 */ 9350 0, /* 21 check_sum */ 9351 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 9352 , /* 22-29 oem_name[16] */ 9353 0, /* 30 dvc_err_code */ 9354 0, /* 31 adv_err_code */ 9355 0, /* 32 adv_err_addr */ 9356 0, /* 33 saved_dvc_err_code */ 9357 0, /* 34 saved_adv_err_code */ 9358 0, /* 35 saved_adv_err_addr */ 9359 0, /* 36 reserved */ 9360 0, /* 37 reserved */ 9361 0, /* 38 reserved */ 9362 0, /* 39 reserved */ 9363 0, /* 40 reserved */ 9364 0, /* 41 reserved */ 9365 0, /* 42 reserved */ 9366 0, /* 43 reserved */ 9367 0, /* 44 reserved */ 9368 0, /* 45 reserved */ 9369 0, /* 46 reserved */ 9370 0, /* 47 reserved */ 9371 0, /* 48 reserved */ 9372 0, /* 49 reserved */ 9373 0, /* 50 reserved */ 9374 0, /* 51 reserved */ 9375 0, /* 52 reserved */ 9376 0, /* 53 reserved */ 9377 0, /* 54 reserved */ 9378 0, /* 55 reserved */ 9379 0, /* 56 cisptr_lsw */ 9380 0, /* 57 cisprt_msw */ 9381 PCI_VENDOR_ID_ASP, /* 58 subsysvid */ 9382 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */ 9383 0, /* 60 reserved */ 9384 0, /* 61 reserved */ 9385 0, /* 62 reserved */ 9386 0 /* 63 reserved */ 9387 }; 9388 9389 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = { 9390 0, /* 00 cfg_lsw */ 9391 0, /* 01 cfg_msw */ 9392 0, /* 02 disc_enable */ 9393 0, /* 03 wdtr_able */ 9394 0, /* 04 sdtr_speed1 */ 9395 0, /* 05 start_motor */ 9396 0, /* 06 tagqng_able */ 9397 0, /* 07 bios_scan */ 9398 0, /* 08 scam_tolerant */ 9399 1, /* 09 adapter_scsi_id */ 9400 1, /* bios_boot_delay */ 9401 1, /* 10 scsi_reset_delay */ 9402 1, /* bios_id_lun */ 9403 1, /* 11 termination_se */ 9404 1, /* termination_lvd */ 9405 0, /* 12 bios_ctrl */ 9406 0, /* 13 sdtr_speed2 */ 9407 0, /* 14 sdtr_speed3 */ 9408 1, /* 15 max_host_qng */ 9409 1, /* max_dvc_qng */ 9410 0, /* 16 dvc_cntl */ 9411 0, /* 17 sdtr_speed4 */ 9412 0, /* 18 serial_number_word1 */ 9413 0, /* 19 serial_number_word2 */ 9414 0, /* 20 serial_number_word3 */ 9415 0, /* 21 check_sum */ 9416 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 9417 , /* 22-29 oem_name[16] */ 9418 0, /* 30 dvc_err_code */ 9419 0, /* 31 adv_err_code */ 9420 0, /* 32 adv_err_addr */ 9421 0, /* 33 saved_dvc_err_code */ 9422 0, /* 34 saved_adv_err_code */ 9423 0, /* 35 saved_adv_err_addr */ 9424 0, /* 36 reserved */ 9425 0, /* 37 reserved */ 9426 0, /* 38 reserved */ 9427 0, /* 39 reserved */ 9428 0, /* 40 reserved */ 9429 0, /* 41 reserved */ 9430 0, /* 42 reserved */ 9431 0, /* 43 reserved */ 9432 0, /* 44 reserved */ 9433 0, /* 45 reserved */ 9434 0, /* 46 reserved */ 9435 0, /* 47 reserved */ 9436 0, /* 48 reserved */ 9437 0, /* 49 reserved */ 9438 0, /* 50 reserved */ 9439 0, /* 51 reserved */ 9440 0, /* 52 reserved */ 9441 0, /* 53 reserved */ 9442 0, /* 54 reserved */ 9443 0, /* 55 reserved */ 9444 0, /* 56 cisptr_lsw */ 9445 0, /* 57 cisprt_msw */ 9446 0, /* 58 subsysvid */ 9447 0, /* 59 subsysid */ 9448 0, /* 60 reserved */ 9449 0, /* 61 reserved */ 9450 0, /* 62 reserved */ 9451 0 /* 63 reserved */ 9452 }; 9453 9454 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = { 9455 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 9456 0x0000, /* 01 cfg_msw */ 9457 0xFFFF, /* 02 disc_enable */ 9458 0xFFFF, /* 03 wdtr_able */ 9459 0x5555, /* 04 sdtr_speed1 */ 9460 0xFFFF, /* 05 start_motor */ 9461 0xFFFF, /* 06 tagqng_able */ 9462 0xFFFF, /* 07 bios_scan */ 9463 0, /* 08 scam_tolerant */ 9464 7, /* 09 adapter_scsi_id */ 9465 0, /* bios_boot_delay */ 9466 3, /* 10 scsi_reset_delay */ 9467 0, /* bios_id_lun */ 9468 0, /* 11 termination_se */ 9469 0, /* termination_lvd */ 9470 0xFFE7, /* 12 bios_ctrl */ 9471 0x5555, /* 13 sdtr_speed2 */ 9472 0x5555, /* 14 sdtr_speed3 */ 9473 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 9474 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 9475 0, /* 16 dvc_cntl */ 9476 0x5555, /* 17 sdtr_speed4 */ 9477 0, /* 18 serial_number_word1 */ 9478 0, /* 19 serial_number_word2 */ 9479 0, /* 20 serial_number_word3 */ 9480 0, /* 21 check_sum */ 9481 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 9482 , /* 22-29 oem_name[16] */ 9483 0, /* 30 dvc_err_code */ 9484 0, /* 31 adv_err_code */ 9485 0, /* 32 adv_err_addr */ 9486 0, /* 33 saved_dvc_err_code */ 9487 0, /* 34 saved_adv_err_code */ 9488 0, /* 35 saved_adv_err_addr */ 9489 0, /* 36 reserved */ 9490 0, /* 37 reserved */ 9491 0, /* 38 reserved */ 9492 0, /* 39 reserved */ 9493 0, /* 40 reserved */ 9494 0, /* 41 reserved */ 9495 0, /* 42 reserved */ 9496 0, /* 43 reserved */ 9497 0, /* 44 reserved */ 9498 0, /* 45 reserved */ 9499 0, /* 46 reserved */ 9500 0, /* 47 reserved */ 9501 0, /* 48 reserved */ 9502 0, /* 49 reserved */ 9503 0, /* 50 reserved */ 9504 0, /* 51 reserved */ 9505 0, /* 52 reserved */ 9506 0, /* 53 reserved */ 9507 0, /* 54 reserved */ 9508 0, /* 55 reserved */ 9509 0, /* 56 cisptr_lsw */ 9510 0, /* 57 cisprt_msw */ 9511 PCI_VENDOR_ID_ASP, /* 58 subsysvid */ 9512 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */ 9513 0, /* 60 reserved */ 9514 0, /* 61 reserved */ 9515 0, /* 62 reserved */ 9516 0 /* 63 reserved */ 9517 }; 9518 9519 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = { 9520 0, /* 00 cfg_lsw */ 9521 0, /* 01 cfg_msw */ 9522 0, /* 02 disc_enable */ 9523 0, /* 03 wdtr_able */ 9524 0, /* 04 sdtr_speed1 */ 9525 0, /* 05 start_motor */ 9526 0, /* 06 tagqng_able */ 9527 0, /* 07 bios_scan */ 9528 0, /* 08 scam_tolerant */ 9529 1, /* 09 adapter_scsi_id */ 9530 1, /* bios_boot_delay */ 9531 1, /* 10 scsi_reset_delay */ 9532 1, /* bios_id_lun */ 9533 1, /* 11 termination_se */ 9534 1, /* termination_lvd */ 9535 0, /* 12 bios_ctrl */ 9536 0, /* 13 sdtr_speed2 */ 9537 0, /* 14 sdtr_speed3 */ 9538 1, /* 15 max_host_qng */ 9539 1, /* max_dvc_qng */ 9540 0, /* 16 dvc_cntl */ 9541 0, /* 17 sdtr_speed4 */ 9542 0, /* 18 serial_number_word1 */ 9543 0, /* 19 serial_number_word2 */ 9544 0, /* 20 serial_number_word3 */ 9545 0, /* 21 check_sum */ 9546 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 9547 , /* 22-29 oem_name[16] */ 9548 0, /* 30 dvc_err_code */ 9549 0, /* 31 adv_err_code */ 9550 0, /* 32 adv_err_addr */ 9551 0, /* 33 saved_dvc_err_code */ 9552 0, /* 34 saved_adv_err_code */ 9553 0, /* 35 saved_adv_err_addr */ 9554 0, /* 36 reserved */ 9555 0, /* 37 reserved */ 9556 0, /* 38 reserved */ 9557 0, /* 39 reserved */ 9558 0, /* 40 reserved */ 9559 0, /* 41 reserved */ 9560 0, /* 42 reserved */ 9561 0, /* 43 reserved */ 9562 0, /* 44 reserved */ 9563 0, /* 45 reserved */ 9564 0, /* 46 reserved */ 9565 0, /* 47 reserved */ 9566 0, /* 48 reserved */ 9567 0, /* 49 reserved */ 9568 0, /* 50 reserved */ 9569 0, /* 51 reserved */ 9570 0, /* 52 reserved */ 9571 0, /* 53 reserved */ 9572 0, /* 54 reserved */ 9573 0, /* 55 reserved */ 9574 0, /* 56 cisptr_lsw */ 9575 0, /* 57 cisprt_msw */ 9576 0, /* 58 subsysvid */ 9577 0, /* 59 subsysid */ 9578 0, /* 60 reserved */ 9579 0, /* 61 reserved */ 9580 0, /* 62 reserved */ 9581 0 /* 63 reserved */ 9582 }; 9583 9584 /* 9585 * Wait for EEPROM command to complete 9586 */ 9587 static void AdvWaitEEPCmd(AdvPortAddr iop_base) 9588 { 9589 int eep_delay_ms; 9590 9591 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) { 9592 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) & 9593 ASC_EEP_CMD_DONE) { 9594 break; 9595 } 9596 mdelay(1); 9597 } 9598 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == 9599 0) 9600 BUG(); 9601 } 9602 9603 /* 9604 * Read the EEPROM from specified location 9605 */ 9606 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr) 9607 { 9608 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9609 ASC_EEP_CMD_READ | eep_word_addr); 9610 AdvWaitEEPCmd(iop_base); 9611 return AdvReadWordRegister(iop_base, IOPW_EE_DATA); 9612 } 9613 9614 /* 9615 * Write the EEPROM from 'cfg_buf'. 9616 */ 9617 static void AdvSet3550EEPConfig(AdvPortAddr iop_base, 9618 ADVEEP_3550_CONFIG *cfg_buf) 9619 { 9620 ushort *wbuf; 9621 ushort addr, chksum; 9622 ushort *charfields; 9623 9624 wbuf = (ushort *)cfg_buf; 9625 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; 9626 chksum = 0; 9627 9628 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 9629 AdvWaitEEPCmd(iop_base); 9630 9631 /* 9632 * Write EEPROM from word 0 to word 20. 9633 */ 9634 for (addr = ADV_EEP_DVC_CFG_BEGIN; 9635 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 9636 ushort word; 9637 9638 if (*charfields++) { 9639 word = cpu_to_le16(*wbuf); 9640 } else { 9641 word = *wbuf; 9642 } 9643 chksum += *wbuf; /* Checksum is calculated from word values. */ 9644 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9645 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9646 ASC_EEP_CMD_WRITE | addr); 9647 AdvWaitEEPCmd(iop_base); 9648 mdelay(ADV_EEP_DELAY_MS); 9649 } 9650 9651 /* 9652 * Write EEPROM checksum at word 21. 9653 */ 9654 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 9655 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 9656 AdvWaitEEPCmd(iop_base); 9657 wbuf++; 9658 charfields++; 9659 9660 /* 9661 * Write EEPROM OEM name at words 22 to 29. 9662 */ 9663 for (addr = ADV_EEP_DVC_CTL_BEGIN; 9664 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 9665 ushort word; 9666 9667 if (*charfields++) { 9668 word = cpu_to_le16(*wbuf); 9669 } else { 9670 word = *wbuf; 9671 } 9672 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9673 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9674 ASC_EEP_CMD_WRITE | addr); 9675 AdvWaitEEPCmd(iop_base); 9676 } 9677 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 9678 AdvWaitEEPCmd(iop_base); 9679 } 9680 9681 /* 9682 * Write the EEPROM from 'cfg_buf'. 9683 */ 9684 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base, 9685 ADVEEP_38C0800_CONFIG *cfg_buf) 9686 { 9687 ushort *wbuf; 9688 ushort *charfields; 9689 ushort addr, chksum; 9690 9691 wbuf = (ushort *)cfg_buf; 9692 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; 9693 chksum = 0; 9694 9695 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 9696 AdvWaitEEPCmd(iop_base); 9697 9698 /* 9699 * Write EEPROM from word 0 to word 20. 9700 */ 9701 for (addr = ADV_EEP_DVC_CFG_BEGIN; 9702 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 9703 ushort word; 9704 9705 if (*charfields++) { 9706 word = cpu_to_le16(*wbuf); 9707 } else { 9708 word = *wbuf; 9709 } 9710 chksum += *wbuf; /* Checksum is calculated from word values. */ 9711 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9712 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9713 ASC_EEP_CMD_WRITE | addr); 9714 AdvWaitEEPCmd(iop_base); 9715 mdelay(ADV_EEP_DELAY_MS); 9716 } 9717 9718 /* 9719 * Write EEPROM checksum at word 21. 9720 */ 9721 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 9722 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 9723 AdvWaitEEPCmd(iop_base); 9724 wbuf++; 9725 charfields++; 9726 9727 /* 9728 * Write EEPROM OEM name at words 22 to 29. 9729 */ 9730 for (addr = ADV_EEP_DVC_CTL_BEGIN; 9731 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 9732 ushort word; 9733 9734 if (*charfields++) { 9735 word = cpu_to_le16(*wbuf); 9736 } else { 9737 word = *wbuf; 9738 } 9739 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9740 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9741 ASC_EEP_CMD_WRITE | addr); 9742 AdvWaitEEPCmd(iop_base); 9743 } 9744 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 9745 AdvWaitEEPCmd(iop_base); 9746 } 9747 9748 /* 9749 * Write the EEPROM from 'cfg_buf'. 9750 */ 9751 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base, 9752 ADVEEP_38C1600_CONFIG *cfg_buf) 9753 { 9754 ushort *wbuf; 9755 ushort *charfields; 9756 ushort addr, chksum; 9757 9758 wbuf = (ushort *)cfg_buf; 9759 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; 9760 chksum = 0; 9761 9762 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 9763 AdvWaitEEPCmd(iop_base); 9764 9765 /* 9766 * Write EEPROM from word 0 to word 20. 9767 */ 9768 for (addr = ADV_EEP_DVC_CFG_BEGIN; 9769 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 9770 ushort word; 9771 9772 if (*charfields++) { 9773 word = cpu_to_le16(*wbuf); 9774 } else { 9775 word = *wbuf; 9776 } 9777 chksum += *wbuf; /* Checksum is calculated from word values. */ 9778 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9779 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9780 ASC_EEP_CMD_WRITE | addr); 9781 AdvWaitEEPCmd(iop_base); 9782 mdelay(ADV_EEP_DELAY_MS); 9783 } 9784 9785 /* 9786 * Write EEPROM checksum at word 21. 9787 */ 9788 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 9789 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 9790 AdvWaitEEPCmd(iop_base); 9791 wbuf++; 9792 charfields++; 9793 9794 /* 9795 * Write EEPROM OEM name at words 22 to 29. 9796 */ 9797 for (addr = ADV_EEP_DVC_CTL_BEGIN; 9798 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 9799 ushort word; 9800 9801 if (*charfields++) { 9802 word = cpu_to_le16(*wbuf); 9803 } else { 9804 word = *wbuf; 9805 } 9806 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9807 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9808 ASC_EEP_CMD_WRITE | addr); 9809 AdvWaitEEPCmd(iop_base); 9810 } 9811 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 9812 AdvWaitEEPCmd(iop_base); 9813 } 9814 9815 /* 9816 * Read EEPROM configuration into the specified buffer. 9817 * 9818 * Return a checksum based on the EEPROM configuration read. 9819 */ 9820 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base, 9821 ADVEEP_3550_CONFIG *cfg_buf) 9822 { 9823 ushort wval, chksum; 9824 ushort *wbuf; 9825 int eep_addr; 9826 ushort *charfields; 9827 9828 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; 9829 wbuf = (ushort *)cfg_buf; 9830 chksum = 0; 9831 9832 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 9833 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 9834 wval = AdvReadEEPWord(iop_base, eep_addr); 9835 chksum += wval; /* Checksum is calculated from word values. */ 9836 if (*charfields++) { 9837 *wbuf = le16_to_cpu(wval); 9838 } else { 9839 *wbuf = wval; 9840 } 9841 } 9842 /* Read checksum word. */ 9843 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9844 wbuf++; 9845 charfields++; 9846 9847 /* Read rest of EEPROM not covered by the checksum. */ 9848 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 9849 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 9850 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9851 if (*charfields++) { 9852 *wbuf = le16_to_cpu(*wbuf); 9853 } 9854 } 9855 return chksum; 9856 } 9857 9858 /* 9859 * Read EEPROM configuration into the specified buffer. 9860 * 9861 * Return a checksum based on the EEPROM configuration read. 9862 */ 9863 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base, 9864 ADVEEP_38C0800_CONFIG *cfg_buf) 9865 { 9866 ushort wval, chksum; 9867 ushort *wbuf; 9868 int eep_addr; 9869 ushort *charfields; 9870 9871 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; 9872 wbuf = (ushort *)cfg_buf; 9873 chksum = 0; 9874 9875 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 9876 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 9877 wval = AdvReadEEPWord(iop_base, eep_addr); 9878 chksum += wval; /* Checksum is calculated from word values. */ 9879 if (*charfields++) { 9880 *wbuf = le16_to_cpu(wval); 9881 } else { 9882 *wbuf = wval; 9883 } 9884 } 9885 /* Read checksum word. */ 9886 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9887 wbuf++; 9888 charfields++; 9889 9890 /* Read rest of EEPROM not covered by the checksum. */ 9891 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 9892 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 9893 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9894 if (*charfields++) { 9895 *wbuf = le16_to_cpu(*wbuf); 9896 } 9897 } 9898 return chksum; 9899 } 9900 9901 /* 9902 * Read EEPROM configuration into the specified buffer. 9903 * 9904 * Return a checksum based on the EEPROM configuration read. 9905 */ 9906 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base, 9907 ADVEEP_38C1600_CONFIG *cfg_buf) 9908 { 9909 ushort wval, chksum; 9910 ushort *wbuf; 9911 int eep_addr; 9912 ushort *charfields; 9913 9914 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; 9915 wbuf = (ushort *)cfg_buf; 9916 chksum = 0; 9917 9918 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 9919 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 9920 wval = AdvReadEEPWord(iop_base, eep_addr); 9921 chksum += wval; /* Checksum is calculated from word values. */ 9922 if (*charfields++) { 9923 *wbuf = le16_to_cpu(wval); 9924 } else { 9925 *wbuf = wval; 9926 } 9927 } 9928 /* Read checksum word. */ 9929 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9930 wbuf++; 9931 charfields++; 9932 9933 /* Read rest of EEPROM not covered by the checksum. */ 9934 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 9935 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 9936 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9937 if (*charfields++) { 9938 *wbuf = le16_to_cpu(*wbuf); 9939 } 9940 } 9941 return chksum; 9942 } 9943 9944 /* 9945 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 9946 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 9947 * all of this is done. 9948 * 9949 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 9950 * 9951 * For a non-fatal error return a warning code. If there are no warnings 9952 * then 0 is returned. 9953 * 9954 * Note: Chip is stopped on entry. 9955 */ 9956 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc) 9957 { 9958 AdvPortAddr iop_base; 9959 ushort warn_code; 9960 ADVEEP_3550_CONFIG eep_config; 9961 9962 iop_base = asc_dvc->iop_base; 9963 9964 warn_code = 0; 9965 9966 /* 9967 * Read the board's EEPROM configuration. 9968 * 9969 * Set default values if a bad checksum is found. 9970 */ 9971 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) { 9972 warn_code |= ASC_WARN_EEPROM_CHKSUM; 9973 9974 /* 9975 * Set EEPROM default values. 9976 */ 9977 memcpy(&eep_config, &Default_3550_EEPROM_Config, 9978 sizeof(ADVEEP_3550_CONFIG)); 9979 9980 /* 9981 * Assume the 6 byte board serial number that was read from 9982 * EEPROM is correct even if the EEPROM checksum failed. 9983 */ 9984 eep_config.serial_number_word3 = 9985 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 9986 9987 eep_config.serial_number_word2 = 9988 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 9989 9990 eep_config.serial_number_word1 = 9991 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 9992 9993 AdvSet3550EEPConfig(iop_base, &eep_config); 9994 } 9995 /* 9996 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the 9997 * EEPROM configuration that was read. 9998 * 9999 * This is the mapping of EEPROM fields to Adv Library fields. 10000 */ 10001 asc_dvc->wdtr_able = eep_config.wdtr_able; 10002 asc_dvc->sdtr_able = eep_config.sdtr_able; 10003 asc_dvc->ultra_able = eep_config.ultra_able; 10004 asc_dvc->tagqng_able = eep_config.tagqng_able; 10005 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 10006 asc_dvc->max_host_qng = eep_config.max_host_qng; 10007 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10008 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID); 10009 asc_dvc->start_motor = eep_config.start_motor; 10010 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 10011 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 10012 asc_dvc->no_scam = eep_config.scam_tolerant; 10013 asc_dvc->cfg->serial1 = eep_config.serial_number_word1; 10014 asc_dvc->cfg->serial2 = eep_config.serial_number_word2; 10015 asc_dvc->cfg->serial3 = eep_config.serial_number_word3; 10016 10017 /* 10018 * Set the host maximum queuing (max. 253, min. 16) and the per device 10019 * maximum queuing (max. 63, min. 4). 10020 */ 10021 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 10022 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10023 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 10024 /* If the value is zero, assume it is uninitialized. */ 10025 if (eep_config.max_host_qng == 0) { 10026 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10027 } else { 10028 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 10029 } 10030 } 10031 10032 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 10033 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10034 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 10035 /* If the value is zero, assume it is uninitialized. */ 10036 if (eep_config.max_dvc_qng == 0) { 10037 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10038 } else { 10039 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 10040 } 10041 } 10042 10043 /* 10044 * If 'max_dvc_qng' is greater than 'max_host_qng', then 10045 * set 'max_dvc_qng' to 'max_host_qng'. 10046 */ 10047 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 10048 eep_config.max_dvc_qng = eep_config.max_host_qng; 10049 } 10050 10051 /* 10052 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 10053 * values based on possibly adjusted EEPROM values. 10054 */ 10055 asc_dvc->max_host_qng = eep_config.max_host_qng; 10056 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10057 10058 /* 10059 * If the EEPROM 'termination' field is set to automatic (0), then set 10060 * the ADV_DVC_CFG 'termination' field to automatic also. 10061 * 10062 * If the termination is specified with a non-zero 'termination' 10063 * value check that a legal value is set and set the ADV_DVC_CFG 10064 * 'termination' field appropriately. 10065 */ 10066 if (eep_config.termination == 0) { 10067 asc_dvc->cfg->termination = 0; /* auto termination */ 10068 } else { 10069 /* Enable manual control with low off / high off. */ 10070 if (eep_config.termination == 1) { 10071 asc_dvc->cfg->termination = TERM_CTL_SEL; 10072 10073 /* Enable manual control with low off / high on. */ 10074 } else if (eep_config.termination == 2) { 10075 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H; 10076 10077 /* Enable manual control with low on / high on. */ 10078 } else if (eep_config.termination == 3) { 10079 asc_dvc->cfg->termination = 10080 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L; 10081 } else { 10082 /* 10083 * The EEPROM 'termination' field contains a bad value. Use 10084 * automatic termination instead. 10085 */ 10086 asc_dvc->cfg->termination = 0; 10087 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10088 } 10089 } 10090 10091 return warn_code; 10092 } 10093 10094 /* 10095 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 10096 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 10097 * all of this is done. 10098 * 10099 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 10100 * 10101 * For a non-fatal error return a warning code. If there are no warnings 10102 * then 0 is returned. 10103 * 10104 * Note: Chip is stopped on entry. 10105 */ 10106 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc) 10107 { 10108 AdvPortAddr iop_base; 10109 ushort warn_code; 10110 ADVEEP_38C0800_CONFIG eep_config; 10111 uchar tid, termination; 10112 ushort sdtr_speed = 0; 10113 10114 iop_base = asc_dvc->iop_base; 10115 10116 warn_code = 0; 10117 10118 /* 10119 * Read the board's EEPROM configuration. 10120 * 10121 * Set default values if a bad checksum is found. 10122 */ 10123 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != 10124 eep_config.check_sum) { 10125 warn_code |= ASC_WARN_EEPROM_CHKSUM; 10126 10127 /* 10128 * Set EEPROM default values. 10129 */ 10130 memcpy(&eep_config, &Default_38C0800_EEPROM_Config, 10131 sizeof(ADVEEP_38C0800_CONFIG)); 10132 10133 /* 10134 * Assume the 6 byte board serial number that was read from 10135 * EEPROM is correct even if the EEPROM checksum failed. 10136 */ 10137 eep_config.serial_number_word3 = 10138 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 10139 10140 eep_config.serial_number_word2 = 10141 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 10142 10143 eep_config.serial_number_word1 = 10144 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 10145 10146 AdvSet38C0800EEPConfig(iop_base, &eep_config); 10147 } 10148 /* 10149 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the 10150 * EEPROM configuration that was read. 10151 * 10152 * This is the mapping of EEPROM fields to Adv Library fields. 10153 */ 10154 asc_dvc->wdtr_able = eep_config.wdtr_able; 10155 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1; 10156 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2; 10157 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3; 10158 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4; 10159 asc_dvc->tagqng_able = eep_config.tagqng_able; 10160 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 10161 asc_dvc->max_host_qng = eep_config.max_host_qng; 10162 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10163 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID); 10164 asc_dvc->start_motor = eep_config.start_motor; 10165 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 10166 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 10167 asc_dvc->no_scam = eep_config.scam_tolerant; 10168 asc_dvc->cfg->serial1 = eep_config.serial_number_word1; 10169 asc_dvc->cfg->serial2 = eep_config.serial_number_word2; 10170 asc_dvc->cfg->serial3 = eep_config.serial_number_word3; 10171 10172 /* 10173 * For every Target ID if any of its 'sdtr_speed[1234]' bits 10174 * are set, then set an 'sdtr_able' bit for it. 10175 */ 10176 asc_dvc->sdtr_able = 0; 10177 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 10178 if (tid == 0) { 10179 sdtr_speed = asc_dvc->sdtr_speed1; 10180 } else if (tid == 4) { 10181 sdtr_speed = asc_dvc->sdtr_speed2; 10182 } else if (tid == 8) { 10183 sdtr_speed = asc_dvc->sdtr_speed3; 10184 } else if (tid == 12) { 10185 sdtr_speed = asc_dvc->sdtr_speed4; 10186 } 10187 if (sdtr_speed & ADV_MAX_TID) { 10188 asc_dvc->sdtr_able |= (1 << tid); 10189 } 10190 sdtr_speed >>= 4; 10191 } 10192 10193 /* 10194 * Set the host maximum queuing (max. 253, min. 16) and the per device 10195 * maximum queuing (max. 63, min. 4). 10196 */ 10197 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 10198 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10199 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 10200 /* If the value is zero, assume it is uninitialized. */ 10201 if (eep_config.max_host_qng == 0) { 10202 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10203 } else { 10204 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 10205 } 10206 } 10207 10208 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 10209 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10210 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 10211 /* If the value is zero, assume it is uninitialized. */ 10212 if (eep_config.max_dvc_qng == 0) { 10213 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10214 } else { 10215 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 10216 } 10217 } 10218 10219 /* 10220 * If 'max_dvc_qng' is greater than 'max_host_qng', then 10221 * set 'max_dvc_qng' to 'max_host_qng'. 10222 */ 10223 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 10224 eep_config.max_dvc_qng = eep_config.max_host_qng; 10225 } 10226 10227 /* 10228 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 10229 * values based on possibly adjusted EEPROM values. 10230 */ 10231 asc_dvc->max_host_qng = eep_config.max_host_qng; 10232 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10233 10234 /* 10235 * If the EEPROM 'termination' field is set to automatic (0), then set 10236 * the ADV_DVC_CFG 'termination' field to automatic also. 10237 * 10238 * If the termination is specified with a non-zero 'termination' 10239 * value check that a legal value is set and set the ADV_DVC_CFG 10240 * 'termination' field appropriately. 10241 */ 10242 if (eep_config.termination_se == 0) { 10243 termination = 0; /* auto termination for SE */ 10244 } else { 10245 /* Enable manual control with low off / high off. */ 10246 if (eep_config.termination_se == 1) { 10247 termination = 0; 10248 10249 /* Enable manual control with low off / high on. */ 10250 } else if (eep_config.termination_se == 2) { 10251 termination = TERM_SE_HI; 10252 10253 /* Enable manual control with low on / high on. */ 10254 } else if (eep_config.termination_se == 3) { 10255 termination = TERM_SE; 10256 } else { 10257 /* 10258 * The EEPROM 'termination_se' field contains a bad value. 10259 * Use automatic termination instead. 10260 */ 10261 termination = 0; 10262 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10263 } 10264 } 10265 10266 if (eep_config.termination_lvd == 0) { 10267 asc_dvc->cfg->termination = termination; /* auto termination for LVD */ 10268 } else { 10269 /* Enable manual control with low off / high off. */ 10270 if (eep_config.termination_lvd == 1) { 10271 asc_dvc->cfg->termination = termination; 10272 10273 /* Enable manual control with low off / high on. */ 10274 } else if (eep_config.termination_lvd == 2) { 10275 asc_dvc->cfg->termination = termination | TERM_LVD_HI; 10276 10277 /* Enable manual control with low on / high on. */ 10278 } else if (eep_config.termination_lvd == 3) { 10279 asc_dvc->cfg->termination = termination | TERM_LVD; 10280 } else { 10281 /* 10282 * The EEPROM 'termination_lvd' field contains a bad value. 10283 * Use automatic termination instead. 10284 */ 10285 asc_dvc->cfg->termination = termination; 10286 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10287 } 10288 } 10289 10290 return warn_code; 10291 } 10292 10293 /* 10294 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and 10295 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while 10296 * all of this is done. 10297 * 10298 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 10299 * 10300 * For a non-fatal error return a warning code. If there are no warnings 10301 * then 0 is returned. 10302 * 10303 * Note: Chip is stopped on entry. 10304 */ 10305 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc) 10306 { 10307 AdvPortAddr iop_base; 10308 ushort warn_code; 10309 ADVEEP_38C1600_CONFIG eep_config; 10310 uchar tid, termination; 10311 ushort sdtr_speed = 0; 10312 10313 iop_base = asc_dvc->iop_base; 10314 10315 warn_code = 0; 10316 10317 /* 10318 * Read the board's EEPROM configuration. 10319 * 10320 * Set default values if a bad checksum is found. 10321 */ 10322 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) != 10323 eep_config.check_sum) { 10324 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc); 10325 warn_code |= ASC_WARN_EEPROM_CHKSUM; 10326 10327 /* 10328 * Set EEPROM default values. 10329 */ 10330 memcpy(&eep_config, &Default_38C1600_EEPROM_Config, 10331 sizeof(ADVEEP_38C1600_CONFIG)); 10332 10333 if (PCI_FUNC(pdev->devfn) != 0) { 10334 u8 ints; 10335 /* 10336 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 10337 * and old Mac system booting problem. The Expansion 10338 * ROM must be disabled in Function 1 for these systems 10339 */ 10340 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE; 10341 /* 10342 * Clear the INTAB (bit 11) if the GPIO 0 input 10343 * indicates the Function 1 interrupt line is wired 10344 * to INTB. 10345 * 10346 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input: 10347 * 1 - Function 1 interrupt line wired to INT A. 10348 * 0 - Function 1 interrupt line wired to INT B. 10349 * 10350 * Note: Function 0 is always wired to INTA. 10351 * Put all 5 GPIO bits in input mode and then read 10352 * their input values. 10353 */ 10354 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0); 10355 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA); 10356 if ((ints & 0x01) == 0) 10357 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB; 10358 } 10359 10360 /* 10361 * Assume the 6 byte board serial number that was read from 10362 * EEPROM is correct even if the EEPROM checksum failed. 10363 */ 10364 eep_config.serial_number_word3 = 10365 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 10366 eep_config.serial_number_word2 = 10367 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 10368 eep_config.serial_number_word1 = 10369 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 10370 10371 AdvSet38C1600EEPConfig(iop_base, &eep_config); 10372 } 10373 10374 /* 10375 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the 10376 * EEPROM configuration that was read. 10377 * 10378 * This is the mapping of EEPROM fields to Adv Library fields. 10379 */ 10380 asc_dvc->wdtr_able = eep_config.wdtr_able; 10381 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1; 10382 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2; 10383 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3; 10384 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4; 10385 asc_dvc->ppr_able = 0; 10386 asc_dvc->tagqng_able = eep_config.tagqng_able; 10387 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 10388 asc_dvc->max_host_qng = eep_config.max_host_qng; 10389 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10390 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID); 10391 asc_dvc->start_motor = eep_config.start_motor; 10392 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 10393 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 10394 asc_dvc->no_scam = eep_config.scam_tolerant; 10395 10396 /* 10397 * For every Target ID if any of its 'sdtr_speed[1234]' bits 10398 * are set, then set an 'sdtr_able' bit for it. 10399 */ 10400 asc_dvc->sdtr_able = 0; 10401 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 10402 if (tid == 0) { 10403 sdtr_speed = asc_dvc->sdtr_speed1; 10404 } else if (tid == 4) { 10405 sdtr_speed = asc_dvc->sdtr_speed2; 10406 } else if (tid == 8) { 10407 sdtr_speed = asc_dvc->sdtr_speed3; 10408 } else if (tid == 12) { 10409 sdtr_speed = asc_dvc->sdtr_speed4; 10410 } 10411 if (sdtr_speed & ASC_MAX_TID) { 10412 asc_dvc->sdtr_able |= (1 << tid); 10413 } 10414 sdtr_speed >>= 4; 10415 } 10416 10417 /* 10418 * Set the host maximum queuing (max. 253, min. 16) and the per device 10419 * maximum queuing (max. 63, min. 4). 10420 */ 10421 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 10422 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10423 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 10424 /* If the value is zero, assume it is uninitialized. */ 10425 if (eep_config.max_host_qng == 0) { 10426 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10427 } else { 10428 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 10429 } 10430 } 10431 10432 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 10433 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10434 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 10435 /* If the value is zero, assume it is uninitialized. */ 10436 if (eep_config.max_dvc_qng == 0) { 10437 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10438 } else { 10439 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 10440 } 10441 } 10442 10443 /* 10444 * If 'max_dvc_qng' is greater than 'max_host_qng', then 10445 * set 'max_dvc_qng' to 'max_host_qng'. 10446 */ 10447 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 10448 eep_config.max_dvc_qng = eep_config.max_host_qng; 10449 } 10450 10451 /* 10452 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng' 10453 * values based on possibly adjusted EEPROM values. 10454 */ 10455 asc_dvc->max_host_qng = eep_config.max_host_qng; 10456 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10457 10458 /* 10459 * If the EEPROM 'termination' field is set to automatic (0), then set 10460 * the ASC_DVC_CFG 'termination' field to automatic also. 10461 * 10462 * If the termination is specified with a non-zero 'termination' 10463 * value check that a legal value is set and set the ASC_DVC_CFG 10464 * 'termination' field appropriately. 10465 */ 10466 if (eep_config.termination_se == 0) { 10467 termination = 0; /* auto termination for SE */ 10468 } else { 10469 /* Enable manual control with low off / high off. */ 10470 if (eep_config.termination_se == 1) { 10471 termination = 0; 10472 10473 /* Enable manual control with low off / high on. */ 10474 } else if (eep_config.termination_se == 2) { 10475 termination = TERM_SE_HI; 10476 10477 /* Enable manual control with low on / high on. */ 10478 } else if (eep_config.termination_se == 3) { 10479 termination = TERM_SE; 10480 } else { 10481 /* 10482 * The EEPROM 'termination_se' field contains a bad value. 10483 * Use automatic termination instead. 10484 */ 10485 termination = 0; 10486 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10487 } 10488 } 10489 10490 if (eep_config.termination_lvd == 0) { 10491 asc_dvc->cfg->termination = termination; /* auto termination for LVD */ 10492 } else { 10493 /* Enable manual control with low off / high off. */ 10494 if (eep_config.termination_lvd == 1) { 10495 asc_dvc->cfg->termination = termination; 10496 10497 /* Enable manual control with low off / high on. */ 10498 } else if (eep_config.termination_lvd == 2) { 10499 asc_dvc->cfg->termination = termination | TERM_LVD_HI; 10500 10501 /* Enable manual control with low on / high on. */ 10502 } else if (eep_config.termination_lvd == 3) { 10503 asc_dvc->cfg->termination = termination | TERM_LVD; 10504 } else { 10505 /* 10506 * The EEPROM 'termination_lvd' field contains a bad value. 10507 * Use automatic termination instead. 10508 */ 10509 asc_dvc->cfg->termination = termination; 10510 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10511 } 10512 } 10513 10514 return warn_code; 10515 } 10516 10517 /* 10518 * Initialize the ADV_DVC_VAR structure. 10519 * 10520 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 10521 * 10522 * For a non-fatal error return a warning code. If there are no warnings 10523 * then 0 is returned. 10524 */ 10525 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost) 10526 { 10527 struct asc_board *board = shost_priv(shost); 10528 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var; 10529 unsigned short warn_code = 0; 10530 AdvPortAddr iop_base = asc_dvc->iop_base; 10531 u16 cmd; 10532 int status; 10533 10534 asc_dvc->err_code = 0; 10535 10536 /* 10537 * Save the state of the PCI Configuration Command Register 10538 * "Parity Error Response Control" Bit. If the bit is clear (0), 10539 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore 10540 * DMA parity errors. 10541 */ 10542 asc_dvc->cfg->control_flag = 0; 10543 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 10544 if ((cmd & PCI_COMMAND_PARITY) == 0) 10545 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR; 10546 10547 asc_dvc->cfg->chip_version = 10548 AdvGetChipVersion(iop_base, asc_dvc->bus_type); 10549 10550 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n", 10551 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1), 10552 (ushort)ADV_CHIP_ID_BYTE); 10553 10554 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n", 10555 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0), 10556 (ushort)ADV_CHIP_ID_WORD); 10557 10558 /* 10559 * Reset the chip to start and allow register writes. 10560 */ 10561 if (AdvFindSignature(iop_base) == 0) { 10562 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 10563 return ADV_ERROR; 10564 } else { 10565 /* 10566 * The caller must set 'chip_type' to a valid setting. 10567 */ 10568 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 && 10569 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 && 10570 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) { 10571 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE; 10572 return ADV_ERROR; 10573 } 10574 10575 /* 10576 * Reset Chip. 10577 */ 10578 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 10579 ADV_CTRL_REG_CMD_RESET); 10580 mdelay(100); 10581 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 10582 ADV_CTRL_REG_CMD_WR_IO_REG); 10583 10584 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 10585 status = AdvInitFrom38C1600EEP(asc_dvc); 10586 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 10587 status = AdvInitFrom38C0800EEP(asc_dvc); 10588 } else { 10589 status = AdvInitFrom3550EEP(asc_dvc); 10590 } 10591 warn_code |= status; 10592 } 10593 10594 if (warn_code != 0) 10595 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code); 10596 10597 if (asc_dvc->err_code) 10598 shost_printk(KERN_ERR, shost, "error code 0x%x\n", 10599 asc_dvc->err_code); 10600 10601 return asc_dvc->err_code; 10602 } 10603 #endif 10604 10605 static const struct scsi_host_template advansys_template = { 10606 .proc_name = DRV_NAME, 10607 #ifdef CONFIG_PROC_FS 10608 .show_info = advansys_show_info, 10609 #endif 10610 .name = DRV_NAME, 10611 .info = advansys_info, 10612 .queuecommand = advansys_queuecommand, 10613 .eh_host_reset_handler = advansys_reset, 10614 .bios_param = advansys_biosparam, 10615 .sdev_configure = advansys_sdev_configure, 10616 .cmd_size = sizeof(struct advansys_cmd), 10617 }; 10618 10619 static int advansys_wide_init_chip(struct Scsi_Host *shost) 10620 { 10621 struct asc_board *board = shost_priv(shost); 10622 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var; 10623 size_t sgblk_pool_size; 10624 int warn_code, err_code; 10625 10626 /* 10627 * Allocate buffer carrier structures. The total size 10628 * is about 8 KB, so allocate all at once. 10629 */ 10630 adv_dvc->carrier = dma_alloc_coherent(board->dev, 10631 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL); 10632 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier); 10633 10634 if (!adv_dvc->carrier) 10635 goto kmalloc_failed; 10636 10637 /* 10638 * Allocate up to 'max_host_qng' request structures for the Wide 10639 * board. The total size is about 16 KB, so allocate all at once. 10640 * If the allocation fails decrement and try again. 10641 */ 10642 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t); 10643 if (board->adv_reqp_size & 0x1f) { 10644 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t)); 10645 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size); 10646 } 10647 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size, 10648 &board->adv_reqp_addr, GFP_KERNEL); 10649 10650 if (!board->adv_reqp) 10651 goto kmalloc_failed; 10652 10653 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp, 10654 adv_dvc->max_host_qng, board->adv_reqp_size); 10655 10656 /* 10657 * Allocate up to ADV_TOT_SG_BLOCK request structures for 10658 * the Wide board. Each structure is about 136 bytes. 10659 */ 10660 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK; 10661 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev, 10662 sgblk_pool_size, 32, 0); 10663 10664 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK, 10665 sizeof(adv_sgblk_t), sgblk_pool_size); 10666 10667 if (!board->adv_sgblk_pool) 10668 goto kmalloc_failed; 10669 10670 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) { 10671 ASC_DBG(2, "AdvInitAsc3550Driver()\n"); 10672 warn_code = AdvInitAsc3550Driver(adv_dvc); 10673 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) { 10674 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n"); 10675 warn_code = AdvInitAsc38C0800Driver(adv_dvc); 10676 } else { 10677 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n"); 10678 warn_code = AdvInitAsc38C1600Driver(adv_dvc); 10679 } 10680 err_code = adv_dvc->err_code; 10681 10682 if (warn_code || err_code) { 10683 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error " 10684 "0x%x\n", warn_code, err_code); 10685 } 10686 10687 goto exit; 10688 10689 kmalloc_failed: 10690 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n"); 10691 err_code = ADV_ERROR; 10692 exit: 10693 return err_code; 10694 } 10695 10696 static void advansys_wide_free_mem(struct asc_board *board) 10697 { 10698 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var; 10699 10700 if (adv_dvc->carrier) { 10701 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE, 10702 adv_dvc->carrier, adv_dvc->carrier_addr); 10703 adv_dvc->carrier = NULL; 10704 } 10705 if (board->adv_reqp) { 10706 dma_free_coherent(board->dev, board->adv_reqp_size, 10707 board->adv_reqp, board->adv_reqp_addr); 10708 board->adv_reqp = NULL; 10709 } 10710 if (board->adv_sgblk_pool) { 10711 dma_pool_destroy(board->adv_sgblk_pool); 10712 board->adv_sgblk_pool = NULL; 10713 } 10714 } 10715 10716 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop, 10717 int bus_type) 10718 { 10719 struct pci_dev *pdev; 10720 struct asc_board *boardp = shost_priv(shost); 10721 ASC_DVC_VAR *asc_dvc_varp = NULL; 10722 ADV_DVC_VAR *adv_dvc_varp = NULL; 10723 int share_irq, warn_code, ret; 10724 10725 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL; 10726 10727 if (ASC_NARROW_BOARD(boardp)) { 10728 ASC_DBG(1, "narrow board\n"); 10729 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; 10730 asc_dvc_varp->bus_type = bus_type; 10731 asc_dvc_varp->drv_ptr = boardp; 10732 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg; 10733 asc_dvc_varp->iop_base = iop; 10734 } else { 10735 #ifdef CONFIG_PCI 10736 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 10737 adv_dvc_varp->drv_ptr = boardp; 10738 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg; 10739 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) { 10740 ASC_DBG(1, "wide board ASC-3550\n"); 10741 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550; 10742 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) { 10743 ASC_DBG(1, "wide board ASC-38C0800\n"); 10744 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800; 10745 } else { 10746 ASC_DBG(1, "wide board ASC-38C1600\n"); 10747 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600; 10748 } 10749 10750 boardp->asc_n_io_port = pci_resource_len(pdev, 1); 10751 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1); 10752 if (!boardp->ioremap_addr) { 10753 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) " 10754 "returned NULL\n", 10755 (long)pci_resource_start(pdev, 1), 10756 boardp->asc_n_io_port); 10757 ret = -ENODEV; 10758 goto err_shost; 10759 } 10760 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr; 10761 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base); 10762 10763 /* 10764 * Even though it isn't used to access wide boards, other 10765 * than for the debug line below, save I/O Port address so 10766 * that it can be reported. 10767 */ 10768 boardp->ioport = iop; 10769 10770 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n", 10771 (ushort)inp(iop + 1), (ushort)inpw(iop)); 10772 #endif /* CONFIG_PCI */ 10773 } 10774 10775 if (ASC_NARROW_BOARD(boardp)) { 10776 /* 10777 * Set the board bus type and PCI IRQ before 10778 * calling AscInitGetConfig(). 10779 */ 10780 switch (asc_dvc_varp->bus_type) { 10781 #ifdef CONFIG_ISA 10782 case ASC_IS_VL: 10783 share_irq = 0; 10784 break; 10785 case ASC_IS_EISA: 10786 share_irq = IRQF_SHARED; 10787 break; 10788 #endif /* CONFIG_ISA */ 10789 #ifdef CONFIG_PCI 10790 case ASC_IS_PCI: 10791 share_irq = IRQF_SHARED; 10792 break; 10793 #endif /* CONFIG_PCI */ 10794 default: 10795 shost_printk(KERN_ERR, shost, "unknown adapter type: " 10796 "%d\n", asc_dvc_varp->bus_type); 10797 share_irq = 0; 10798 break; 10799 } 10800 10801 /* 10802 * NOTE: AscInitGetConfig() may change the board's 10803 * bus_type value. The bus_type value should no 10804 * longer be used. If the bus_type field must be 10805 * referenced only use the bit-wise AND operator "&". 10806 */ 10807 ASC_DBG(2, "AscInitGetConfig()\n"); 10808 ret = AscInitGetConfig(shost) ? -ENODEV : 0; 10809 } else { 10810 #ifdef CONFIG_PCI 10811 /* 10812 * For Wide boards set PCI information before calling 10813 * AdvInitGetConfig(). 10814 */ 10815 share_irq = IRQF_SHARED; 10816 ASC_DBG(2, "AdvInitGetConfig()\n"); 10817 10818 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0; 10819 #else 10820 share_irq = 0; 10821 ret = -ENODEV; 10822 #endif /* CONFIG_PCI */ 10823 } 10824 10825 if (ret) 10826 goto err_unmap; 10827 10828 /* 10829 * Save the EEPROM configuration so that it can be displayed 10830 * from /proc/scsi/advansys/[0...]. 10831 */ 10832 if (ASC_NARROW_BOARD(boardp)) { 10833 10834 ASCEEP_CONFIG *ep; 10835 10836 /* 10837 * Set the adapter's target id bit in the 'init_tidmask' field. 10838 */ 10839 boardp->init_tidmask |= 10840 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id); 10841 10842 /* 10843 * Save EEPROM settings for the board. 10844 */ 10845 ep = &boardp->eep_config.asc_eep; 10846 10847 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable; 10848 ep->disc_enable = asc_dvc_varp->cfg->disc_enable; 10849 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled; 10850 ASC_EEP_SET_DMA_SPD(ep, ASC_DEF_ISA_DMA_SPEED); 10851 ep->start_motor = asc_dvc_varp->start_motor; 10852 ep->cntl = asc_dvc_varp->dvc_cntl; 10853 ep->no_scam = asc_dvc_varp->no_scam; 10854 ep->max_total_qng = asc_dvc_varp->max_total_qng; 10855 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id); 10856 /* 'max_tag_qng' is set to the same value for every device. */ 10857 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0]; 10858 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0]; 10859 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1]; 10860 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2]; 10861 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3]; 10862 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4]; 10863 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5]; 10864 10865 /* 10866 * Modify board configuration. 10867 */ 10868 ASC_DBG(2, "AscInitSetConfig()\n"); 10869 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0; 10870 if (ret) 10871 goto err_unmap; 10872 } else { 10873 ADVEEP_3550_CONFIG *ep_3550; 10874 ADVEEP_38C0800_CONFIG *ep_38C0800; 10875 ADVEEP_38C1600_CONFIG *ep_38C1600; 10876 10877 /* 10878 * Save Wide EEP Configuration Information. 10879 */ 10880 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 10881 ep_3550 = &boardp->eep_config.adv_3550_eep; 10882 10883 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id; 10884 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng; 10885 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 10886 ep_3550->termination = adv_dvc_varp->cfg->termination; 10887 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable; 10888 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl; 10889 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able; 10890 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able; 10891 ep_3550->ultra_able = adv_dvc_varp->ultra_able; 10892 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able; 10893 ep_3550->start_motor = adv_dvc_varp->start_motor; 10894 ep_3550->scsi_reset_delay = 10895 adv_dvc_varp->scsi_reset_wait; 10896 ep_3550->serial_number_word1 = 10897 adv_dvc_varp->cfg->serial1; 10898 ep_3550->serial_number_word2 = 10899 adv_dvc_varp->cfg->serial2; 10900 ep_3550->serial_number_word3 = 10901 adv_dvc_varp->cfg->serial3; 10902 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 10903 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep; 10904 10905 ep_38C0800->adapter_scsi_id = 10906 adv_dvc_varp->chip_scsi_id; 10907 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng; 10908 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 10909 ep_38C0800->termination_lvd = 10910 adv_dvc_varp->cfg->termination; 10911 ep_38C0800->disc_enable = 10912 adv_dvc_varp->cfg->disc_enable; 10913 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl; 10914 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able; 10915 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able; 10916 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1; 10917 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2; 10918 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3; 10919 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4; 10920 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able; 10921 ep_38C0800->start_motor = adv_dvc_varp->start_motor; 10922 ep_38C0800->scsi_reset_delay = 10923 adv_dvc_varp->scsi_reset_wait; 10924 ep_38C0800->serial_number_word1 = 10925 adv_dvc_varp->cfg->serial1; 10926 ep_38C0800->serial_number_word2 = 10927 adv_dvc_varp->cfg->serial2; 10928 ep_38C0800->serial_number_word3 = 10929 adv_dvc_varp->cfg->serial3; 10930 } else { 10931 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep; 10932 10933 ep_38C1600->adapter_scsi_id = 10934 adv_dvc_varp->chip_scsi_id; 10935 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng; 10936 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 10937 ep_38C1600->termination_lvd = 10938 adv_dvc_varp->cfg->termination; 10939 ep_38C1600->disc_enable = 10940 adv_dvc_varp->cfg->disc_enable; 10941 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl; 10942 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able; 10943 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able; 10944 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1; 10945 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2; 10946 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3; 10947 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4; 10948 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able; 10949 ep_38C1600->start_motor = adv_dvc_varp->start_motor; 10950 ep_38C1600->scsi_reset_delay = 10951 adv_dvc_varp->scsi_reset_wait; 10952 ep_38C1600->serial_number_word1 = 10953 adv_dvc_varp->cfg->serial1; 10954 ep_38C1600->serial_number_word2 = 10955 adv_dvc_varp->cfg->serial2; 10956 ep_38C1600->serial_number_word3 = 10957 adv_dvc_varp->cfg->serial3; 10958 } 10959 10960 /* 10961 * Set the adapter's target id bit in the 'init_tidmask' field. 10962 */ 10963 boardp->init_tidmask |= 10964 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id); 10965 } 10966 10967 /* 10968 * Channels are numbered beginning with 0. For AdvanSys one host 10969 * structure supports one channel. Multi-channel boards have a 10970 * separate host structure for each channel. 10971 */ 10972 shost->max_channel = 0; 10973 if (ASC_NARROW_BOARD(boardp)) { 10974 shost->max_id = ASC_MAX_TID + 1; 10975 shost->max_lun = ASC_MAX_LUN + 1; 10976 shost->max_cmd_len = ASC_MAX_CDB_LEN; 10977 10978 shost->io_port = asc_dvc_varp->iop_base; 10979 boardp->asc_n_io_port = ASC_IOADR_GAP; 10980 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id; 10981 10982 /* Set maximum number of queues the adapter can handle. */ 10983 shost->can_queue = asc_dvc_varp->max_total_qng; 10984 } else { 10985 shost->max_id = ADV_MAX_TID + 1; 10986 shost->max_lun = ADV_MAX_LUN + 1; 10987 shost->max_cmd_len = ADV_MAX_CDB_LEN; 10988 10989 /* 10990 * Save the I/O Port address and length even though 10991 * I/O ports are not used to access Wide boards. 10992 * Instead the Wide boards are accessed with 10993 * PCI Memory Mapped I/O. 10994 */ 10995 shost->io_port = iop; 10996 10997 shost->this_id = adv_dvc_varp->chip_scsi_id; 10998 10999 /* Set maximum number of queues the adapter can handle. */ 11000 shost->can_queue = adv_dvc_varp->max_host_qng; 11001 } 11002 11003 /* 11004 * Set the maximum number of scatter-gather elements the 11005 * adapter can handle. 11006 */ 11007 if (ASC_NARROW_BOARD(boardp)) { 11008 /* 11009 * Allow two commands with 'sg_tablesize' scatter-gather 11010 * elements to be executed simultaneously. This value is 11011 * the theoretical hardware limit. It may be decreased 11012 * below. 11013 */ 11014 shost->sg_tablesize = 11015 (((asc_dvc_varp->max_total_qng - 2) / 2) * 11016 ASC_SG_LIST_PER_Q) + 1; 11017 } else { 11018 shost->sg_tablesize = ADV_MAX_SG_LIST; 11019 } 11020 11021 /* 11022 * The value of 'sg_tablesize' can not exceed the SCSI 11023 * mid-level driver definition of SG_ALL. SG_ALL also 11024 * must not be exceeded, because it is used to define the 11025 * size of the scatter-gather table in 'struct asc_sg_head'. 11026 */ 11027 if (shost->sg_tablesize > SG_ALL) { 11028 shost->sg_tablesize = SG_ALL; 11029 } 11030 11031 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize); 11032 11033 /* BIOS start address. */ 11034 if (ASC_NARROW_BOARD(boardp)) { 11035 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base, 11036 asc_dvc_varp->bus_type); 11037 } else { 11038 /* 11039 * Fill-in BIOS board variables. The Wide BIOS saves 11040 * information in LRAM that is used by the driver. 11041 */ 11042 AdvReadWordLram(adv_dvc_varp->iop_base, 11043 BIOS_SIGNATURE, boardp->bios_signature); 11044 AdvReadWordLram(adv_dvc_varp->iop_base, 11045 BIOS_VERSION, boardp->bios_version); 11046 AdvReadWordLram(adv_dvc_varp->iop_base, 11047 BIOS_CODESEG, boardp->bios_codeseg); 11048 AdvReadWordLram(adv_dvc_varp->iop_base, 11049 BIOS_CODELEN, boardp->bios_codelen); 11050 11051 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n", 11052 boardp->bios_signature, boardp->bios_version); 11053 11054 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n", 11055 boardp->bios_codeseg, boardp->bios_codelen); 11056 11057 /* 11058 * If the BIOS saved a valid signature, then fill in 11059 * the BIOS code segment base address. 11060 */ 11061 if (boardp->bios_signature == 0x55AA) { 11062 /* 11063 * Convert x86 realmode code segment to a linear 11064 * address by shifting left 4. 11065 */ 11066 shost->base = ((ulong)boardp->bios_codeseg << 4); 11067 } else { 11068 shost->base = 0; 11069 } 11070 } 11071 11072 /* 11073 * Register Board Resources - I/O Port, DMA, IRQ 11074 */ 11075 11076 /* Register DMA Channel for Narrow boards. */ 11077 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */ 11078 11079 /* Register IRQ Number. */ 11080 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost); 11081 11082 ret = request_irq(boardp->irq, advansys_interrupt, share_irq, 11083 DRV_NAME, shost); 11084 11085 if (ret) { 11086 if (ret == -EBUSY) { 11087 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 11088 "already in use\n", boardp->irq); 11089 } else if (ret == -EINVAL) { 11090 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 11091 "not valid\n", boardp->irq); 11092 } else { 11093 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 11094 "failed with %d\n", boardp->irq, ret); 11095 } 11096 goto err_unmap; 11097 } 11098 11099 /* 11100 * Initialize board RISC chip and enable interrupts. 11101 */ 11102 if (ASC_NARROW_BOARD(boardp)) { 11103 ASC_DBG(2, "AscInitAsc1000Driver()\n"); 11104 11105 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL); 11106 if (!asc_dvc_varp->overrun_buf) { 11107 ret = -ENOMEM; 11108 goto err_free_irq; 11109 } 11110 warn_code = AscInitAsc1000Driver(asc_dvc_varp); 11111 11112 if (warn_code || asc_dvc_varp->err_code) { 11113 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, " 11114 "warn 0x%x, error 0x%x\n", 11115 asc_dvc_varp->init_state, warn_code, 11116 asc_dvc_varp->err_code); 11117 if (!asc_dvc_varp->overrun_dma) { 11118 ret = -ENODEV; 11119 goto err_free_mem; 11120 } 11121 } 11122 } else { 11123 if (advansys_wide_init_chip(shost)) { 11124 ret = -ENODEV; 11125 goto err_free_mem; 11126 } 11127 } 11128 11129 ASC_DBG_PRT_SCSI_HOST(2, shost); 11130 11131 ret = scsi_add_host(shost, boardp->dev); 11132 if (ret) 11133 goto err_free_mem; 11134 11135 scsi_scan_host(shost); 11136 return 0; 11137 11138 err_free_mem: 11139 if (ASC_NARROW_BOARD(boardp)) { 11140 if (asc_dvc_varp->overrun_dma) 11141 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma, 11142 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 11143 kfree(asc_dvc_varp->overrun_buf); 11144 } else 11145 advansys_wide_free_mem(boardp); 11146 err_free_irq: 11147 free_irq(boardp->irq, shost); 11148 err_unmap: 11149 if (boardp->ioremap_addr) 11150 iounmap(boardp->ioremap_addr); 11151 #ifdef CONFIG_PCI 11152 err_shost: 11153 #endif 11154 return ret; 11155 } 11156 11157 /* 11158 * advansys_release() 11159 * 11160 * Release resources allocated for a single AdvanSys adapter. 11161 */ 11162 static int advansys_release(struct Scsi_Host *shost) 11163 { 11164 struct asc_board *board = shost_priv(shost); 11165 ASC_DBG(1, "begin\n"); 11166 scsi_remove_host(shost); 11167 free_irq(board->irq, shost); 11168 11169 if (ASC_NARROW_BOARD(board)) { 11170 dma_unmap_single(board->dev, 11171 board->dvc_var.asc_dvc_var.overrun_dma, 11172 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 11173 kfree(board->dvc_var.asc_dvc_var.overrun_buf); 11174 } else { 11175 iounmap(board->ioremap_addr); 11176 advansys_wide_free_mem(board); 11177 } 11178 scsi_host_put(shost); 11179 ASC_DBG(1, "end\n"); 11180 return 0; 11181 } 11182 11183 #define ASC_IOADR_TABLE_MAX_IX 11 11184 11185 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = { 11186 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190, 11187 0x0210, 0x0230, 0x0250, 0x0330 11188 }; 11189 11190 static void advansys_vlb_remove(struct device *dev, unsigned int id) 11191 { 11192 int ioport = _asc_def_iop_base[id]; 11193 advansys_release(dev_get_drvdata(dev)); 11194 release_region(ioport, ASC_IOADR_GAP); 11195 } 11196 11197 /* 11198 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as: 11199 * 000: invalid 11200 * 001: 10 11201 * 010: 11 11202 * 011: 12 11203 * 100: invalid 11204 * 101: 14 11205 * 110: 15 11206 * 111: invalid 11207 */ 11208 static unsigned int advansys_vlb_irq_no(PortAddr iop_base) 11209 { 11210 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base); 11211 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9; 11212 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15)) 11213 return 0; 11214 return chip_irq; 11215 } 11216 11217 static int advansys_vlb_probe(struct device *dev, unsigned int id) 11218 { 11219 int err = -ENODEV; 11220 PortAddr iop_base = _asc_def_iop_base[id]; 11221 struct Scsi_Host *shost; 11222 struct asc_board *board; 11223 11224 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) { 11225 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base); 11226 return -ENODEV; 11227 } 11228 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base); 11229 if (!AscFindSignature(iop_base)) 11230 goto release_region; 11231 /* 11232 * I don't think this condition can actually happen, but the old 11233 * driver did it, and the chances of finding a VLB setup in 2007 11234 * to do testing with is slight to none. 11235 */ 11236 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL) 11237 goto release_region; 11238 11239 err = -ENOMEM; 11240 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 11241 if (!shost) 11242 goto release_region; 11243 11244 board = shost_priv(shost); 11245 board->irq = advansys_vlb_irq_no(iop_base); 11246 board->dev = dev; 11247 board->shost = shost; 11248 11249 err = advansys_board_found(shost, iop_base, ASC_IS_VL); 11250 if (err) 11251 goto free_host; 11252 11253 dev_set_drvdata(dev, shost); 11254 return 0; 11255 11256 free_host: 11257 scsi_host_put(shost); 11258 release_region: 11259 release_region(iop_base, ASC_IOADR_GAP); 11260 return -ENODEV; 11261 } 11262 11263 static struct isa_driver advansys_vlb_driver = { 11264 .probe = advansys_vlb_probe, 11265 .remove = advansys_vlb_remove, 11266 .driver = { 11267 .owner = THIS_MODULE, 11268 .name = "advansys_vlb", 11269 }, 11270 }; 11271 11272 static struct eisa_device_id advansys_eisa_table[] = { 11273 { "ABP7401" }, 11274 { "ABP7501" }, 11275 { "" } 11276 }; 11277 11278 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table); 11279 11280 /* 11281 * EISA is a little more tricky than PCI; each EISA device may have two 11282 * channels, and this driver is written to make each channel its own Scsi_Host 11283 */ 11284 struct eisa_scsi_data { 11285 struct Scsi_Host *host[2]; 11286 }; 11287 11288 /* 11289 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as: 11290 * 000: 10 11291 * 001: 11 11292 * 010: 12 11293 * 011: invalid 11294 * 100: 14 11295 * 101: 15 11296 * 110: invalid 11297 * 111: invalid 11298 */ 11299 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev) 11300 { 11301 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86); 11302 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10; 11303 if ((chip_irq == 13) || (chip_irq > 15)) 11304 return 0; 11305 return chip_irq; 11306 } 11307 11308 static int advansys_eisa_probe(struct device *dev) 11309 { 11310 int i, ioport, irq = 0; 11311 int err; 11312 struct eisa_device *edev = to_eisa_device(dev); 11313 struct eisa_scsi_data *data; 11314 11315 err = -ENOMEM; 11316 data = kzalloc_obj(*data); 11317 if (!data) 11318 goto fail; 11319 ioport = edev->base_addr + 0xc30; 11320 11321 err = -ENODEV; 11322 for (i = 0; i < 2; i++, ioport += 0x20) { 11323 struct asc_board *board; 11324 struct Scsi_Host *shost; 11325 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) { 11326 printk(KERN_WARNING "Region %x-%x busy\n", ioport, 11327 ioport + ASC_IOADR_GAP - 1); 11328 continue; 11329 } 11330 if (!AscFindSignature(ioport)) { 11331 release_region(ioport, ASC_IOADR_GAP); 11332 continue; 11333 } 11334 11335 /* 11336 * I don't know why we need to do this for EISA chips, but 11337 * not for any others. It looks to be equivalent to 11338 * AscGetChipCfgMsw, but I may have overlooked something, 11339 * so I'm not converting it until I get an EISA board to 11340 * test with. 11341 */ 11342 inw(ioport + 4); 11343 11344 if (!irq) 11345 irq = advansys_eisa_irq_no(edev); 11346 11347 err = -ENOMEM; 11348 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 11349 if (!shost) 11350 goto release_region; 11351 11352 board = shost_priv(shost); 11353 board->irq = irq; 11354 board->dev = dev; 11355 board->shost = shost; 11356 11357 err = advansys_board_found(shost, ioport, ASC_IS_EISA); 11358 if (!err) { 11359 data->host[i] = shost; 11360 continue; 11361 } 11362 11363 scsi_host_put(shost); 11364 release_region: 11365 release_region(ioport, ASC_IOADR_GAP); 11366 break; 11367 } 11368 11369 if (err) 11370 goto free_data; 11371 dev_set_drvdata(dev, data); 11372 return 0; 11373 11374 free_data: 11375 kfree(data->host[0]); 11376 kfree(data->host[1]); 11377 kfree(data); 11378 fail: 11379 return err; 11380 } 11381 11382 static int advansys_eisa_remove(struct device *dev) 11383 { 11384 int i; 11385 struct eisa_scsi_data *data = dev_get_drvdata(dev); 11386 11387 for (i = 0; i < 2; i++) { 11388 int ioport; 11389 struct Scsi_Host *shost = data->host[i]; 11390 if (!shost) 11391 continue; 11392 ioport = shost->io_port; 11393 advansys_release(shost); 11394 release_region(ioport, ASC_IOADR_GAP); 11395 } 11396 11397 kfree(data); 11398 return 0; 11399 } 11400 11401 static struct eisa_driver advansys_eisa_driver = { 11402 .id_table = advansys_eisa_table, 11403 .driver = { 11404 .name = DRV_NAME, 11405 .probe = advansys_eisa_probe, 11406 .remove = advansys_eisa_remove, 11407 } 11408 }; 11409 11410 /* PCI Devices supported by this driver */ 11411 static const struct pci_device_id advansys_pci_tbl[] = { 11412 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A, 11413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11414 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940, 11415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11416 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U, 11417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11418 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW, 11419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11420 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1, 11421 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11422 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1, 11423 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11424 {} 11425 }; 11426 11427 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl); 11428 11429 static void advansys_set_latency(struct pci_dev *pdev) 11430 { 11431 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) || 11432 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) { 11433 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0); 11434 } else { 11435 u8 latency; 11436 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency); 11437 if (latency < 0x20) 11438 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20); 11439 } 11440 } 11441 11442 static int advansys_pci_probe(struct pci_dev *pdev, 11443 const struct pci_device_id *ent) 11444 { 11445 int err, ioport; 11446 struct Scsi_Host *shost; 11447 struct asc_board *board; 11448 11449 err = pci_enable_device(pdev); 11450 if (err) 11451 goto fail; 11452 err = pci_request_regions(pdev, DRV_NAME); 11453 if (err) 11454 goto disable_device; 11455 pci_set_master(pdev); 11456 advansys_set_latency(pdev); 11457 11458 err = -ENODEV; 11459 if (pci_resource_len(pdev, 0) == 0) 11460 goto release_region; 11461 11462 ioport = pci_resource_start(pdev, 0); 11463 11464 err = -ENOMEM; 11465 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 11466 if (!shost) 11467 goto release_region; 11468 11469 board = shost_priv(shost); 11470 board->irq = pdev->irq; 11471 board->dev = &pdev->dev; 11472 board->shost = shost; 11473 11474 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW || 11475 pdev->device == PCI_DEVICE_ID_38C0800_REV1 || 11476 pdev->device == PCI_DEVICE_ID_38C1600_REV1) { 11477 board->flags |= ASC_IS_WIDE_BOARD; 11478 } 11479 11480 err = advansys_board_found(shost, ioport, ASC_IS_PCI); 11481 if (err) 11482 goto free_host; 11483 11484 pci_set_drvdata(pdev, shost); 11485 return 0; 11486 11487 free_host: 11488 scsi_host_put(shost); 11489 release_region: 11490 pci_release_regions(pdev); 11491 disable_device: 11492 pci_disable_device(pdev); 11493 fail: 11494 return err; 11495 } 11496 11497 static void advansys_pci_remove(struct pci_dev *pdev) 11498 { 11499 advansys_release(pci_get_drvdata(pdev)); 11500 pci_release_regions(pdev); 11501 pci_disable_device(pdev); 11502 } 11503 11504 static struct pci_driver advansys_pci_driver = { 11505 .name = DRV_NAME, 11506 .id_table = advansys_pci_tbl, 11507 .probe = advansys_pci_probe, 11508 .remove = advansys_pci_remove, 11509 }; 11510 11511 static int __init advansys_init(void) 11512 { 11513 int error; 11514 11515 error = isa_register_driver(&advansys_vlb_driver, 11516 ASC_IOADR_TABLE_MAX_IX); 11517 if (error) 11518 goto fail; 11519 11520 error = eisa_driver_register(&advansys_eisa_driver); 11521 if (error) 11522 goto unregister_vlb; 11523 11524 error = pci_register_driver(&advansys_pci_driver); 11525 if (error) 11526 goto unregister_eisa; 11527 11528 return 0; 11529 11530 unregister_eisa: 11531 eisa_driver_unregister(&advansys_eisa_driver); 11532 unregister_vlb: 11533 isa_unregister_driver(&advansys_vlb_driver); 11534 fail: 11535 return error; 11536 } 11537 11538 static void __exit advansys_exit(void) 11539 { 11540 pci_unregister_driver(&advansys_pci_driver); 11541 eisa_driver_unregister(&advansys_eisa_driver); 11542 isa_unregister_driver(&advansys_vlb_driver); 11543 } 11544 11545 module_init(advansys_init); 11546 module_exit(advansys_exit); 11547 11548 MODULE_DESCRIPTION("AdvanSys SCSI Adapter driver"); 11549 MODULE_LICENSE("GPL"); 11550 MODULE_FIRMWARE("advansys/mcode.bin"); 11551 MODULE_FIRMWARE("advansys/3550.bin"); 11552 MODULE_FIRMWARE("advansys/38C0800.bin"); 11553 MODULE_FIRMWARE("advansys/38C1600.bin"); 11554