1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADRF6780 driver 4 * 5 * Copyright 2021 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/clkdev.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/iio/iio.h> 15 #include <linux/module.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/spi/spi.h> 18 19 #include <linux/unaligned.h> 20 21 /* ADRF6780 Register Map */ 22 #define ADRF6780_REG_CONTROL 0x00 23 #define ADRF6780_REG_ALARM_READBACK 0x01 24 #define ADRF6780_REG_ALARM_MASKS 0x02 25 #define ADRF6780_REG_ENABLE 0x03 26 #define ADRF6780_REG_LINEARIZE 0x04 27 #define ADRF6780_REG_LO_PATH 0x05 28 #define ADRF6780_REG_ADC_CONTROL 0x06 29 #define ADRF6780_REG_ADC_OUTPUT 0x0C 30 31 /* ADRF6780_REG_CONTROL Map */ 32 #define ADRF6780_PARITY_EN_MSK BIT(15) 33 #define ADRF6780_SOFT_RESET_MSK BIT(14) 34 #define ADRF6780_CHIP_ID_MSK GENMASK(11, 4) 35 #define ADRF6780_CHIP_ID 0xA 36 #define ADRF6780_CHIP_REVISION_MSK GENMASK(3, 0) 37 38 /* ADRF6780_REG_ALARM_READBACK Map */ 39 #define ADRF6780_PARITY_ERROR_MSK BIT(15) 40 #define ADRF6780_TOO_FEW_ERRORS_MSK BIT(14) 41 #define ADRF6780_TOO_MANY_ERRORS_MSK BIT(13) 42 #define ADRF6780_ADDRESS_RANGE_ERROR_MSK BIT(12) 43 44 /* ADRF6780_REG_ENABLE Map */ 45 #define ADRF6780_VGA_BUFFER_EN_MSK BIT(8) 46 #define ADRF6780_DETECTOR_EN_MSK BIT(7) 47 #define ADRF6780_LO_BUFFER_EN_MSK BIT(6) 48 #define ADRF6780_IF_MODE_EN_MSK BIT(5) 49 #define ADRF6780_IQ_MODE_EN_MSK BIT(4) 50 #define ADRF6780_LO_X2_EN_MSK BIT(3) 51 #define ADRF6780_LO_PPF_EN_MSK BIT(2) 52 #define ADRF6780_LO_EN_MSK BIT(1) 53 #define ADRF6780_UC_BIAS_EN_MSK BIT(0) 54 55 /* ADRF6780_REG_LINEARIZE Map */ 56 #define ADRF6780_RDAC_LINEARIZE_MSK GENMASK(7, 0) 57 58 /* ADRF6780_REG_LO_PATH Map */ 59 #define ADRF6780_LO_SIDEBAND_MSK BIT(10) 60 #define ADRF6780_Q_PATH_PHASE_ACCURACY_MSK GENMASK(7, 4) 61 #define ADRF6780_I_PATH_PHASE_ACCURACY_MSK GENMASK(3, 0) 62 63 /* ADRF6780_REG_ADC_CONTROL Map */ 64 #define ADRF6780_VDET_OUTPUT_SELECT_MSK BIT(3) 65 #define ADRF6780_ADC_START_MSK BIT(2) 66 #define ADRF6780_ADC_EN_MSK BIT(1) 67 #define ADRF6780_ADC_CLOCK_EN_MSK BIT(0) 68 69 /* ADRF6780_REG_ADC_OUTPUT Map */ 70 #define ADRF6780_ADC_STATUS_MSK BIT(8) 71 #define ADRF6780_ADC_VALUE_MSK GENMASK(7, 0) 72 73 struct adrf6780_state { 74 struct spi_device *spi; 75 struct clk *clkin; 76 /* Protect against concurrent accesses to the device */ 77 struct mutex lock; 78 bool vga_buff_en; 79 bool lo_buff_en; 80 bool if_mode_en; 81 bool iq_mode_en; 82 bool lo_x2_en; 83 bool lo_ppf_en; 84 bool lo_en; 85 bool uc_bias_en; 86 bool lo_sideband; 87 bool vdet_out_en; 88 u8 data[3] __aligned(IIO_DMA_MINALIGN); 89 }; 90 91 static int __adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg, 92 unsigned int *val) 93 { 94 int ret; 95 struct spi_transfer t = {0}; 96 97 st->data[0] = 0x80 | (reg << 1); 98 st->data[1] = 0x0; 99 st->data[2] = 0x0; 100 101 t.rx_buf = &st->data[0]; 102 t.tx_buf = &st->data[0]; 103 t.len = 3; 104 105 ret = spi_sync_transfer(st->spi, &t, 1); 106 if (ret) 107 return ret; 108 109 *val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0); 110 111 return ret; 112 } 113 114 static int adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg, 115 unsigned int *val) 116 { 117 int ret; 118 119 mutex_lock(&st->lock); 120 ret = __adrf6780_spi_read(st, reg, val); 121 mutex_unlock(&st->lock); 122 123 return ret; 124 } 125 126 static int __adrf6780_spi_write(struct adrf6780_state *st, 127 unsigned int reg, 128 unsigned int val) 129 { 130 put_unaligned_be24((val << 1) | (reg << 17), &st->data[0]); 131 132 return spi_write(st->spi, &st->data[0], 3); 133 } 134 135 static int adrf6780_spi_write(struct adrf6780_state *st, unsigned int reg, 136 unsigned int val) 137 { 138 int ret; 139 140 mutex_lock(&st->lock); 141 ret = __adrf6780_spi_write(st, reg, val); 142 mutex_unlock(&st->lock); 143 144 return ret; 145 } 146 147 static int __adrf6780_spi_update_bits(struct adrf6780_state *st, 148 unsigned int reg, unsigned int mask, 149 unsigned int val) 150 { 151 int ret; 152 unsigned int data, temp; 153 154 ret = __adrf6780_spi_read(st, reg, &data); 155 if (ret) 156 return ret; 157 158 temp = (data & ~mask) | (val & mask); 159 160 return __adrf6780_spi_write(st, reg, temp); 161 } 162 163 static int adrf6780_spi_update_bits(struct adrf6780_state *st, unsigned int reg, 164 unsigned int mask, unsigned int val) 165 { 166 int ret; 167 168 mutex_lock(&st->lock); 169 ret = __adrf6780_spi_update_bits(st, reg, mask, val); 170 mutex_unlock(&st->lock); 171 172 return ret; 173 } 174 175 static int adrf6780_read_adc_raw(struct adrf6780_state *st, unsigned int *read_val) 176 { 177 int ret; 178 179 mutex_lock(&st->lock); 180 181 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL, 182 ADRF6780_ADC_EN_MSK | 183 ADRF6780_ADC_CLOCK_EN_MSK | 184 ADRF6780_ADC_START_MSK, 185 FIELD_PREP(ADRF6780_ADC_EN_MSK, 1) | 186 FIELD_PREP(ADRF6780_ADC_CLOCK_EN_MSK, 1) | 187 FIELD_PREP(ADRF6780_ADC_START_MSK, 1)); 188 if (ret) 189 goto exit; 190 191 /* 192 * Per ADRF6780 datasheet (Rev. D, page 23, ADC section), 193 * wait approximately 200 us for the ADC to be ready. 194 */ 195 fsleep(200); 196 197 ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val); 198 if (ret) 199 goto exit; 200 201 if (!(*read_val & ADRF6780_ADC_STATUS_MSK)) { 202 ret = -EINVAL; 203 goto exit; 204 } 205 206 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL, 207 ADRF6780_ADC_START_MSK, 208 FIELD_PREP(ADRF6780_ADC_START_MSK, 0)); 209 if (ret) 210 goto exit; 211 212 ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val); 213 214 exit: 215 mutex_unlock(&st->lock); 216 return ret; 217 } 218 219 static int adrf6780_read_raw(struct iio_dev *indio_dev, 220 struct iio_chan_spec const *chan, 221 int *val, int *val2, long info) 222 { 223 struct adrf6780_state *dev = iio_priv(indio_dev); 224 unsigned int data; 225 int ret; 226 227 switch (info) { 228 case IIO_CHAN_INFO_RAW: 229 ret = adrf6780_read_adc_raw(dev, &data); 230 if (ret) 231 return ret; 232 233 *val = data & ADRF6780_ADC_VALUE_MSK; 234 235 return IIO_VAL_INT; 236 237 case IIO_CHAN_INFO_SCALE: 238 ret = adrf6780_spi_read(dev, ADRF6780_REG_LINEARIZE, &data); 239 if (ret) 240 return ret; 241 242 *val = data & ADRF6780_RDAC_LINEARIZE_MSK; 243 244 return IIO_VAL_INT; 245 case IIO_CHAN_INFO_PHASE: 246 ret = adrf6780_spi_read(dev, ADRF6780_REG_LO_PATH, &data); 247 if (ret) 248 return ret; 249 250 switch (chan->channel2) { 251 case IIO_MOD_I: 252 *val = data & ADRF6780_I_PATH_PHASE_ACCURACY_MSK; 253 254 return IIO_VAL_INT; 255 case IIO_MOD_Q: 256 *val = FIELD_GET(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, 257 data); 258 259 return IIO_VAL_INT; 260 default: 261 return -EINVAL; 262 } 263 default: 264 return -EINVAL; 265 } 266 } 267 268 static int adrf6780_write_raw(struct iio_dev *indio_dev, 269 struct iio_chan_spec const *chan, 270 int val, int val2, long info) 271 { 272 struct adrf6780_state *st = iio_priv(indio_dev); 273 274 switch (info) { 275 case IIO_CHAN_INFO_SCALE: 276 return adrf6780_spi_write(st, ADRF6780_REG_LINEARIZE, val); 277 case IIO_CHAN_INFO_PHASE: 278 switch (chan->channel2) { 279 case IIO_MOD_I: 280 return adrf6780_spi_update_bits(st, 281 ADRF6780_REG_LO_PATH, 282 ADRF6780_I_PATH_PHASE_ACCURACY_MSK, 283 FIELD_PREP(ADRF6780_I_PATH_PHASE_ACCURACY_MSK, val)); 284 case IIO_MOD_Q: 285 return adrf6780_spi_update_bits(st, 286 ADRF6780_REG_LO_PATH, 287 ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, 288 FIELD_PREP(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, val)); 289 default: 290 return -EINVAL; 291 } 292 default: 293 return -EINVAL; 294 } 295 } 296 297 static int adrf6780_reg_access(struct iio_dev *indio_dev, 298 unsigned int reg, 299 unsigned int write_val, 300 unsigned int *read_val) 301 { 302 struct adrf6780_state *st = iio_priv(indio_dev); 303 304 if (read_val) 305 return adrf6780_spi_read(st, reg, read_val); 306 else 307 return adrf6780_spi_write(st, reg, write_val); 308 } 309 310 static const struct iio_info adrf6780_info = { 311 .read_raw = adrf6780_read_raw, 312 .write_raw = adrf6780_write_raw, 313 .debugfs_reg_access = &adrf6780_reg_access, 314 }; 315 316 #define ADRF6780_CHAN_ADC(_channel) { \ 317 .type = IIO_ALTVOLTAGE, \ 318 .output = 0, \ 319 .indexed = 1, \ 320 .channel = _channel, \ 321 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 322 } 323 324 #define ADRF6780_CHAN_RDAC(_channel) { \ 325 .type = IIO_ALTVOLTAGE, \ 326 .output = 1, \ 327 .indexed = 1, \ 328 .channel = _channel, \ 329 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) \ 330 } 331 332 #define ADRF6780_CHAN_IQ_PHASE(_channel, rf_comp) { \ 333 .type = IIO_ALTVOLTAGE, \ 334 .modified = 1, \ 335 .output = 1, \ 336 .indexed = 1, \ 337 .channel2 = IIO_MOD_##rf_comp, \ 338 .channel = _channel, \ 339 .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) \ 340 } 341 342 static const struct iio_chan_spec adrf6780_channels[] = { 343 ADRF6780_CHAN_ADC(0), 344 ADRF6780_CHAN_RDAC(0), 345 ADRF6780_CHAN_IQ_PHASE(0, I), 346 ADRF6780_CHAN_IQ_PHASE(0, Q), 347 }; 348 349 static int adrf6780_reset(struct adrf6780_state *st) 350 { 351 int ret; 352 struct device *dev = &st->spi->dev; 353 354 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL, 355 ADRF6780_SOFT_RESET_MSK, 356 FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 1)); 357 if (ret) 358 return dev_err_probe(dev, ret, 359 "ADRF6780 SPI software reset failed.\n"); 360 361 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL, 362 ADRF6780_SOFT_RESET_MSK, 363 FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 0)); 364 if (ret) 365 return dev_err_probe(dev, ret, 366 "ADRF6780 SPI software reset disable failed.\n"); 367 368 return 0; 369 } 370 371 static int adrf6780_init(struct adrf6780_state *st) 372 { 373 int ret; 374 unsigned int chip_id, enable_reg, enable_reg_msk; 375 struct device *dev = &st->spi->dev; 376 377 /* Perform a software reset */ 378 ret = adrf6780_reset(st); 379 if (ret) 380 return ret; 381 382 ret = __adrf6780_spi_read(st, ADRF6780_REG_CONTROL, &chip_id); 383 if (ret) 384 return ret; 385 386 chip_id = FIELD_GET(ADRF6780_CHIP_ID_MSK, chip_id); 387 if (chip_id != ADRF6780_CHIP_ID) 388 return dev_err_probe(dev, -EINVAL, 389 "ADRF6780 Invalid Chip ID.\n"); 390 391 enable_reg_msk = ADRF6780_VGA_BUFFER_EN_MSK | 392 ADRF6780_DETECTOR_EN_MSK | 393 ADRF6780_LO_BUFFER_EN_MSK | 394 ADRF6780_IF_MODE_EN_MSK | 395 ADRF6780_IQ_MODE_EN_MSK | 396 ADRF6780_LO_X2_EN_MSK | 397 ADRF6780_LO_PPF_EN_MSK | 398 ADRF6780_LO_EN_MSK | 399 ADRF6780_UC_BIAS_EN_MSK; 400 401 enable_reg = FIELD_PREP(ADRF6780_VGA_BUFFER_EN_MSK, st->vga_buff_en) | 402 FIELD_PREP(ADRF6780_DETECTOR_EN_MSK, 1) | 403 FIELD_PREP(ADRF6780_LO_BUFFER_EN_MSK, st->lo_buff_en) | 404 FIELD_PREP(ADRF6780_IF_MODE_EN_MSK, st->if_mode_en) | 405 FIELD_PREP(ADRF6780_IQ_MODE_EN_MSK, st->iq_mode_en) | 406 FIELD_PREP(ADRF6780_LO_X2_EN_MSK, st->lo_x2_en) | 407 FIELD_PREP(ADRF6780_LO_PPF_EN_MSK, st->lo_ppf_en) | 408 FIELD_PREP(ADRF6780_LO_EN_MSK, st->lo_en) | 409 FIELD_PREP(ADRF6780_UC_BIAS_EN_MSK, st->uc_bias_en); 410 411 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ENABLE, 412 enable_reg_msk, enable_reg); 413 if (ret) 414 return ret; 415 416 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_LO_PATH, 417 ADRF6780_LO_SIDEBAND_MSK, 418 FIELD_PREP(ADRF6780_LO_SIDEBAND_MSK, st->lo_sideband)); 419 if (ret) 420 return ret; 421 422 return __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL, 423 ADRF6780_VDET_OUTPUT_SELECT_MSK, 424 FIELD_PREP(ADRF6780_VDET_OUTPUT_SELECT_MSK, st->vdet_out_en)); 425 } 426 427 static void adrf6780_properties_parse(struct adrf6780_state *st) 428 { 429 struct device *dev = &st->spi->dev; 430 431 st->vga_buff_en = device_property_read_bool(dev, "adi,vga-buff-en"); 432 st->lo_buff_en = device_property_read_bool(dev, "adi,lo-buff-en"); 433 st->if_mode_en = device_property_read_bool(dev, "adi,if-mode-en"); 434 st->iq_mode_en = device_property_read_bool(dev, "adi,iq-mode-en"); 435 st->lo_x2_en = device_property_read_bool(dev, "adi,lo-x2-en"); 436 st->lo_ppf_en = device_property_read_bool(dev, "adi,lo-ppf-en"); 437 st->lo_en = device_property_read_bool(dev, "adi,lo-en"); 438 st->uc_bias_en = device_property_read_bool(dev, "adi,uc-bias-en"); 439 st->lo_sideband = device_property_read_bool(dev, "adi,lo-sideband"); 440 st->vdet_out_en = device_property_read_bool(dev, "adi,vdet-out-en"); 441 } 442 443 static void adrf6780_powerdown(void *data) 444 { 445 /* Disable all components in the Enable Register */ 446 adrf6780_spi_write(data, ADRF6780_REG_ENABLE, 0x0); 447 } 448 449 static int adrf6780_probe(struct spi_device *spi) 450 { 451 struct iio_dev *indio_dev; 452 struct adrf6780_state *st; 453 struct device *dev = &spi->dev; 454 int ret; 455 456 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 457 if (!indio_dev) 458 return -ENOMEM; 459 460 st = iio_priv(indio_dev); 461 462 indio_dev->info = &adrf6780_info; 463 indio_dev->name = "adrf6780"; 464 indio_dev->channels = adrf6780_channels; 465 indio_dev->num_channels = ARRAY_SIZE(adrf6780_channels); 466 467 st->spi = spi; 468 469 adrf6780_properties_parse(st); 470 471 st->clkin = devm_clk_get_enabled(dev, "lo_in"); 472 if (IS_ERR(st->clkin)) 473 return dev_err_probe(dev, PTR_ERR(st->clkin), 474 "failed to get the LO input clock\n"); 475 476 mutex_init(&st->lock); 477 478 ret = adrf6780_init(st); 479 if (ret) 480 return ret; 481 482 ret = devm_add_action_or_reset(dev, adrf6780_powerdown, st); 483 if (ret) 484 return ret; 485 486 return devm_iio_device_register(dev, indio_dev); 487 } 488 489 static const struct spi_device_id adrf6780_id[] = { 490 { "adrf6780", 0 }, 491 { } 492 }; 493 MODULE_DEVICE_TABLE(spi, adrf6780_id); 494 495 static const struct of_device_id adrf6780_of_match[] = { 496 { .compatible = "adi,adrf6780" }, 497 { } 498 }; 499 MODULE_DEVICE_TABLE(of, adrf6780_of_match); 500 501 static struct spi_driver adrf6780_driver = { 502 .driver = { 503 .name = "adrf6780", 504 .of_match_table = adrf6780_of_match, 505 }, 506 .probe = adrf6780_probe, 507 .id_table = adrf6780_id, 508 }; 509 module_spi_driver(adrf6780_driver); 510 511 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); 512 MODULE_DESCRIPTION("Analog Devices ADRF6780"); 513 MODULE_LICENSE("GPL v2"); 514