1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
7 */
8
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
11
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
14
15 #include "msm_gpu.h"
16
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
19
20 extern bool snapshot_debugbus;
21 extern bool allow_vram_carveout;
22
23 enum {
24 ADRENO_FW_PM4 = 0,
25 ADRENO_FW_SQE = 0, /* a6xx */
26 ADRENO_FW_PFP = 1,
27 ADRENO_FW_GMU = 1, /* a6xx */
28 ADRENO_FW_GPMU = 2,
29 ADRENO_FW_MAX,
30 };
31
32 /**
33 * @enum adreno_family: identify generation and possibly sub-generation
34 *
35 * In some cases there are distinct sub-generations within a major revision
36 * so it helps to be able to group the GPU devices by generation and if
37 * necessary sub-generation.
38 */
39 enum adreno_family {
40 ADRENO_2XX_GEN1, /* a20x */
41 ADRENO_2XX_GEN2, /* a22x */
42 ADRENO_3XX,
43 ADRENO_4XX,
44 ADRENO_5XX,
45 ADRENO_6XX_GEN1, /* a630 family */
46 ADRENO_6XX_GEN2, /* a640 family */
47 ADRENO_6XX_GEN3, /* a650 family */
48 ADRENO_6XX_GEN4, /* a660 family */
49 ADRENO_7XX_GEN1, /* a730 family */
50 ADRENO_7XX_GEN2, /* a740 family */
51 ADRENO_7XX_GEN3, /* a750 family */
52 };
53
54 #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
55 #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
56 #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
57 #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
58 #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
59
60 /* Helper for formating the chip_id in the way that userspace tools like
61 * crashdec expect.
62 */
63 #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
64 #define ADRENO_CHIPID_ARGS(_c) \
65 (((_c) >> 24) & 0xff), \
66 (((_c) >> 16) & 0xff), \
67 (((_c) >> 8) & 0xff), \
68 ((_c) & 0xff)
69
70 struct adreno_gpu_funcs {
71 struct msm_gpu_funcs base;
72 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
73 };
74
75 struct adreno_reglist {
76 u32 offset;
77 u32 value;
78 };
79
80 struct adreno_speedbin {
81 uint16_t fuse;
82 uint16_t speedbin;
83 };
84
85 struct a6xx_info;
86
87 struct adreno_info {
88 const char *machine;
89 /**
90 * @chipids: Table of matching chip-ids
91 *
92 * Terminated with 0 sentinal
93 */
94 uint32_t *chip_ids;
95 enum adreno_family family;
96 uint32_t revn;
97 const char *fw[ADRENO_FW_MAX];
98 uint32_t gmem;
99 u64 quirks;
100 struct msm_gpu *(*init)(struct drm_device *dev);
101 const char *zapfw;
102 u32 inactive_period;
103 union {
104 const struct a6xx_info *a6xx;
105 };
106 u64 address_space_size;
107 /**
108 * @speedbins: Optional table of fuse to speedbin mappings
109 *
110 * Consists of pairs of fuse, index mappings, terminated with
111 * {SHRT_MAX, 0} sentinal.
112 */
113 struct adreno_speedbin *speedbins;
114 };
115
116 #define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
117
118 struct adreno_gpulist {
119 const struct adreno_info *gpus;
120 unsigned gpus_count;
121 };
122
123 #define DECLARE_ADRENO_GPULIST(name) \
124 const struct adreno_gpulist name ## _gpulist = { \
125 name ## _gpus, ARRAY_SIZE(name ## _gpus) \
126 }
127
128 /*
129 * Helper to build a speedbin table, ie. the table:
130 * fuse | speedbin
131 * -----+---------
132 * 0 | 0
133 * 169 | 1
134 * 174 | 2
135 *
136 * would be declared as:
137 *
138 * .speedbins = ADRENO_SPEEDBINS(
139 * { 0, 0 },
140 * { 169, 1 },
141 * { 174, 2 },
142 * ),
143 */
144 #define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} }
145
146 struct adreno_protect {
147 const uint32_t *regs;
148 uint32_t count;
149 uint32_t count_max;
150 };
151
152 #define DECLARE_ADRENO_PROTECT(name, __count_max) \
153 static const struct adreno_protect name = { \
154 .regs = name ## _regs, \
155 .count = ARRAY_SIZE(name ## _regs), \
156 .count_max = __count_max, \
157 };
158
159 struct adreno_gpu {
160 struct msm_gpu base;
161 const struct adreno_info *info;
162 uint32_t chip_id;
163 uint16_t speedbin;
164 const struct adreno_gpu_funcs *funcs;
165
166 /* interesting register offsets to dump: */
167 const unsigned int *registers;
168
169 /*
170 * Are we loading fw from legacy path? Prior to addition
171 * of gpu firmware to linux-firmware, the fw files were
172 * placed in toplevel firmware directory, following qcom's
173 * android kernel. But linux-firmware preferred they be
174 * placed in a 'qcom' subdirectory.
175 *
176 * For backwards compatibility, we try first to load from
177 * the new path, using request_firmware_direct() to avoid
178 * any potential timeout waiting for usermode helper, then
179 * fall back to the old path (with direct load). And
180 * finally fall back to request_firmware() with the new
181 * path to allow the usermode helper.
182 */
183 enum {
184 FW_LOCATION_UNKNOWN = 0,
185 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */
186 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */
187 FW_LOCATION_HELPER,
188 } fwloc;
189
190 /* firmware: */
191 const struct firmware *fw[ADRENO_FW_MAX];
192
193 struct {
194 /**
195 * @rgb565_predicator: Unknown, introduced with A650 family,
196 * related to UBWC mode/ver 4
197 */
198 u32 rgb565_predicator;
199 /** @uavflagprd_inv: Unknown, introduced with A650 family */
200 u32 uavflagprd_inv;
201 /** @min_acc_len: Whether the minimum access length is 64 bits */
202 u32 min_acc_len;
203 /**
204 * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.
205 *
206 * UBWC 1.0 always enables all three levels.
207 * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
208 * UBWC 4.0 adds the optional ability to disable levels 2 & 3.
209 *
210 * This is a bitmask where BIT(0) enables level 1, BIT(1)
211 * controls level 2, and BIT(2) enables level 3.
212 */
213 u32 ubwc_swizzle;
214 /**
215 * @highest_bank_bit: Highest Bank Bit
216 *
217 * The Highest Bank Bit value represents the bit of the highest
218 * DDR bank. This should ideally use DRAM type detection.
219 */
220 u32 highest_bank_bit;
221 u32 amsbc;
222 /**
223 * @macrotile_mode: Macrotile Mode
224 *
225 * Whether to use 4-channel macrotiling mode or the newer
226 * 8-channel macrotiling mode introduced in UBWC 3.1. 0 is
227 * 4-channel and 1 is 8-channel.
228 */
229 u32 macrotile_mode;
230 } ubwc_config;
231
232 /*
233 * Register offsets are different between some GPUs.
234 * GPU specific offsets will be exported by GPU specific
235 * code (a3xx_gpu.c) and stored in this common location.
236 */
237 const unsigned int *reg_offsets;
238 bool gmu_is_wrapper;
239
240 bool has_ray_tracing;
241 };
242 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
243
244 struct adreno_ocmem {
245 struct ocmem *ocmem;
246 unsigned long base;
247 void *hdl;
248 };
249
250 /* platform config data (ie. from DT, or pdata) */
251 struct adreno_platform_config {
252 uint32_t chip_id;
253 const struct adreno_info *info;
254 };
255
256 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
257
258 #define spin_until(X) ({ \
259 int __ret = -ETIMEDOUT; \
260 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
261 do { \
262 if (X) { \
263 __ret = 0; \
264 break; \
265 } \
266 } while (time_before(jiffies, __t)); \
267 __ret; \
268 })
269
adreno_patchid(const struct adreno_gpu * gpu)270 static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
271 {
272 /* It is probably ok to assume legacy "adreno_rev" format
273 * for all a6xx devices, but probably best to limit this
274 * to older things.
275 */
276 WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
277 return gpu->chip_id & 0xff;
278 }
279
adreno_is_revn(const struct adreno_gpu * gpu,uint32_t revn)280 static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
281 {
282 if (WARN_ON_ONCE(!gpu->info))
283 return false;
284 return gpu->info->revn == revn;
285 }
286
adreno_has_gmu_wrapper(const struct adreno_gpu * gpu)287 static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
288 {
289 return gpu->gmu_is_wrapper;
290 }
291
adreno_is_a2xx(const struct adreno_gpu * gpu)292 static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
293 {
294 if (WARN_ON_ONCE(!gpu->info))
295 return false;
296 return gpu->info->family <= ADRENO_2XX_GEN2;
297 }
298
adreno_is_a20x(const struct adreno_gpu * gpu)299 static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
300 {
301 if (WARN_ON_ONCE(!gpu->info))
302 return false;
303 return gpu->info->family == ADRENO_2XX_GEN1;
304 }
305
adreno_is_a225(const struct adreno_gpu * gpu)306 static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
307 {
308 return adreno_is_revn(gpu, 225);
309 }
310
adreno_is_a305(const struct adreno_gpu * gpu)311 static inline bool adreno_is_a305(const struct adreno_gpu *gpu)
312 {
313 return adreno_is_revn(gpu, 305);
314 }
315
adreno_is_a305b(const struct adreno_gpu * gpu)316 static inline bool adreno_is_a305b(const struct adreno_gpu *gpu)
317 {
318 return gpu->info->chip_ids[0] == 0x03000512;
319 }
320
adreno_is_a306(const struct adreno_gpu * gpu)321 static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
322 {
323 /* yes, 307, because a305c is 306 */
324 return adreno_is_revn(gpu, 307);
325 }
326
adreno_is_a306a(const struct adreno_gpu * gpu)327 static inline bool adreno_is_a306a(const struct adreno_gpu *gpu)
328 {
329 /* a306a (marketing name is a308) */
330 return adreno_is_revn(gpu, 308);
331 }
332
adreno_is_a320(const struct adreno_gpu * gpu)333 static inline bool adreno_is_a320(const struct adreno_gpu *gpu)
334 {
335 return adreno_is_revn(gpu, 320);
336 }
337
adreno_is_a330(const struct adreno_gpu * gpu)338 static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
339 {
340 return adreno_is_revn(gpu, 330);
341 }
342
adreno_is_a330v2(const struct adreno_gpu * gpu)343 static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
344 {
345 return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
346 }
347
adreno_is_a405(const struct adreno_gpu * gpu)348 static inline int adreno_is_a405(const struct adreno_gpu *gpu)
349 {
350 return adreno_is_revn(gpu, 405);
351 }
352
adreno_is_a420(const struct adreno_gpu * gpu)353 static inline int adreno_is_a420(const struct adreno_gpu *gpu)
354 {
355 return adreno_is_revn(gpu, 420);
356 }
357
adreno_is_a430(const struct adreno_gpu * gpu)358 static inline int adreno_is_a430(const struct adreno_gpu *gpu)
359 {
360 return adreno_is_revn(gpu, 430);
361 }
362
adreno_is_a505(const struct adreno_gpu * gpu)363 static inline int adreno_is_a505(const struct adreno_gpu *gpu)
364 {
365 return adreno_is_revn(gpu, 505);
366 }
367
adreno_is_a506(const struct adreno_gpu * gpu)368 static inline int adreno_is_a506(const struct adreno_gpu *gpu)
369 {
370 return adreno_is_revn(gpu, 506);
371 }
372
adreno_is_a508(const struct adreno_gpu * gpu)373 static inline int adreno_is_a508(const struct adreno_gpu *gpu)
374 {
375 return adreno_is_revn(gpu, 508);
376 }
377
adreno_is_a509(const struct adreno_gpu * gpu)378 static inline int adreno_is_a509(const struct adreno_gpu *gpu)
379 {
380 return adreno_is_revn(gpu, 509);
381 }
382
adreno_is_a510(const struct adreno_gpu * gpu)383 static inline int adreno_is_a510(const struct adreno_gpu *gpu)
384 {
385 return adreno_is_revn(gpu, 510);
386 }
387
adreno_is_a512(const struct adreno_gpu * gpu)388 static inline int adreno_is_a512(const struct adreno_gpu *gpu)
389 {
390 return adreno_is_revn(gpu, 512);
391 }
392
adreno_is_a530(const struct adreno_gpu * gpu)393 static inline int adreno_is_a530(const struct adreno_gpu *gpu)
394 {
395 return adreno_is_revn(gpu, 530);
396 }
397
adreno_is_a540(const struct adreno_gpu * gpu)398 static inline int adreno_is_a540(const struct adreno_gpu *gpu)
399 {
400 return adreno_is_revn(gpu, 540);
401 }
402
adreno_is_a610(const struct adreno_gpu * gpu)403 static inline int adreno_is_a610(const struct adreno_gpu *gpu)
404 {
405 return adreno_is_revn(gpu, 610);
406 }
407
adreno_is_a618(const struct adreno_gpu * gpu)408 static inline int adreno_is_a618(const struct adreno_gpu *gpu)
409 {
410 return adreno_is_revn(gpu, 618);
411 }
412
adreno_is_a619(const struct adreno_gpu * gpu)413 static inline int adreno_is_a619(const struct adreno_gpu *gpu)
414 {
415 return adreno_is_revn(gpu, 619);
416 }
417
adreno_is_a619_holi(const struct adreno_gpu * gpu)418 static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu)
419 {
420 return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu);
421 }
422
adreno_is_a621(const struct adreno_gpu * gpu)423 static inline int adreno_is_a621(const struct adreno_gpu *gpu)
424 {
425 return gpu->info->chip_ids[0] == 0x06020100;
426 }
427
adreno_is_a630(const struct adreno_gpu * gpu)428 static inline int adreno_is_a630(const struct adreno_gpu *gpu)
429 {
430 return adreno_is_revn(gpu, 630);
431 }
432
adreno_is_a640(const struct adreno_gpu * gpu)433 static inline int adreno_is_a640(const struct adreno_gpu *gpu)
434 {
435 return adreno_is_revn(gpu, 640);
436 }
437
adreno_is_a650(const struct adreno_gpu * gpu)438 static inline int adreno_is_a650(const struct adreno_gpu *gpu)
439 {
440 return adreno_is_revn(gpu, 650);
441 }
442
adreno_is_7c3(const struct adreno_gpu * gpu)443 static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
444 {
445 return gpu->info->chip_ids[0] == 0x06030500;
446 }
447
adreno_is_a660(const struct adreno_gpu * gpu)448 static inline int adreno_is_a660(const struct adreno_gpu *gpu)
449 {
450 return adreno_is_revn(gpu, 660);
451 }
452
adreno_is_a680(const struct adreno_gpu * gpu)453 static inline int adreno_is_a680(const struct adreno_gpu *gpu)
454 {
455 return adreno_is_revn(gpu, 680);
456 }
457
adreno_is_a690(const struct adreno_gpu * gpu)458 static inline int adreno_is_a690(const struct adreno_gpu *gpu)
459 {
460 return gpu->info->chip_ids[0] == 0x06090000;
461 }
462
adreno_is_a702(const struct adreno_gpu * gpu)463 static inline int adreno_is_a702(const struct adreno_gpu *gpu)
464 {
465 return gpu->info->chip_ids[0] == 0x07000200;
466 }
467
adreno_is_a610_family(const struct adreno_gpu * gpu)468 static inline int adreno_is_a610_family(const struct adreno_gpu *gpu)
469 {
470 if (WARN_ON_ONCE(!gpu->info))
471 return false;
472
473 /* TODO: A612 */
474 return adreno_is_a610(gpu) || adreno_is_a702(gpu);
475 }
476
477 /* TODO: 615/616 */
adreno_is_a615_family(const struct adreno_gpu * gpu)478 static inline int adreno_is_a615_family(const struct adreno_gpu *gpu)
479 {
480 return adreno_is_a618(gpu) ||
481 adreno_is_a619(gpu);
482 }
483
adreno_is_a630_family(const struct adreno_gpu * gpu)484 static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
485 {
486 if (WARN_ON_ONCE(!gpu->info))
487 return false;
488 return gpu->info->family == ADRENO_6XX_GEN1;
489 }
490
adreno_is_a660_family(const struct adreno_gpu * gpu)491 static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
492 {
493 if (WARN_ON_ONCE(!gpu->info))
494 return false;
495 return gpu->info->family == ADRENO_6XX_GEN4;
496 }
497
498 /* check for a650, a660, or any derivatives */
adreno_is_a650_family(const struct adreno_gpu * gpu)499 static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
500 {
501 if (WARN_ON_ONCE(!gpu->info))
502 return false;
503 return gpu->info->family == ADRENO_6XX_GEN3 ||
504 gpu->info->family == ADRENO_6XX_GEN4;
505 }
506
adreno_is_a640_family(const struct adreno_gpu * gpu)507 static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
508 {
509 if (WARN_ON_ONCE(!gpu->info))
510 return false;
511 return gpu->info->family == ADRENO_6XX_GEN2;
512 }
513
adreno_is_a730(struct adreno_gpu * gpu)514 static inline int adreno_is_a730(struct adreno_gpu *gpu)
515 {
516 return gpu->info->chip_ids[0] == 0x07030001;
517 }
518
adreno_is_a740(struct adreno_gpu * gpu)519 static inline int adreno_is_a740(struct adreno_gpu *gpu)
520 {
521 return gpu->info->chip_ids[0] == 0x43050a01;
522 }
523
adreno_is_a750(struct adreno_gpu * gpu)524 static inline int adreno_is_a750(struct adreno_gpu *gpu)
525 {
526 return gpu->info->chip_ids[0] == 0x43051401;
527 }
528
adreno_is_x185(struct adreno_gpu * gpu)529 static inline int adreno_is_x185(struct adreno_gpu *gpu)
530 {
531 return gpu->info->chip_ids[0] == 0x43050c01;
532 }
533
adreno_is_a740_family(struct adreno_gpu * gpu)534 static inline int adreno_is_a740_family(struct adreno_gpu *gpu)
535 {
536 if (WARN_ON_ONCE(!gpu->info))
537 return false;
538 return gpu->info->family == ADRENO_7XX_GEN2 ||
539 gpu->info->family == ADRENO_7XX_GEN3;
540 }
541
adreno_is_a7xx(struct adreno_gpu * gpu)542 static inline int adreno_is_a7xx(struct adreno_gpu *gpu)
543 {
544 /* Update with non-fake (i.e. non-A702) Gen 7 GPUs */
545 return gpu->info->family == ADRENO_7XX_GEN1 ||
546 adreno_is_a740_family(gpu);
547 }
548
549 u64 adreno_private_address_space_size(struct msm_gpu *gpu);
550 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
551 uint32_t param, uint64_t *value, uint32_t *len);
552 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
553 uint32_t param, uint64_t value, uint32_t len);
554 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
555 const char *fwname);
556 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
557 const struct firmware *fw, u64 *iova);
558 int adreno_hw_init(struct msm_gpu *gpu);
559 void adreno_recover(struct msm_gpu *gpu);
560 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
561 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
562 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
563 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
564 struct drm_printer *p);
565 #endif
566 void adreno_dump_info(struct msm_gpu *gpu);
567 void adreno_dump(struct msm_gpu *gpu);
568 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
569 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
570
571 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
572 struct adreno_ocmem *ocmem);
573 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
574
575 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
576 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
577 int nr_rings);
578 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
579 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
580
581 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
582
583 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
584 int adreno_gpu_state_put(struct msm_gpu_state *state);
585 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
586 bool *encoded);
587
588 /*
589 * Common helper function to initialize the default address space for arm-smmu
590 * attached targets
591 */
592 struct msm_gem_address_space *
593 adreno_create_address_space(struct msm_gpu *gpu,
594 struct platform_device *pdev);
595
596 struct msm_gem_address_space *
597 adreno_iommu_create_address_space(struct msm_gpu *gpu,
598 struct platform_device *pdev,
599 unsigned long quirks);
600
601 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
602 struct adreno_smmu_fault_info *info, const char *block,
603 u32 scratch[4]);
604
605 int adreno_read_speedbin(struct device *dev, u32 *speedbin);
606
607 /*
608 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
609 * out of secure mode
610 */
611 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
612
613 /* ringbuffer helpers (the parts that are adreno specific) */
614
615 static inline void
OUT_PKT0(struct msm_ringbuffer * ring,uint16_t regindx,uint16_t cnt)616 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
617 {
618 adreno_wait_ring(ring, cnt+1);
619 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
620 }
621
622 /* no-op packet: */
623 static inline void
OUT_PKT2(struct msm_ringbuffer * ring)624 OUT_PKT2(struct msm_ringbuffer *ring)
625 {
626 adreno_wait_ring(ring, 1);
627 OUT_RING(ring, CP_TYPE2_PKT);
628 }
629
630 static inline void
OUT_PKT3(struct msm_ringbuffer * ring,uint8_t opcode,uint16_t cnt)631 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
632 {
633 adreno_wait_ring(ring, cnt+1);
634 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
635 }
636
PM4_PARITY(u32 val)637 static inline u32 PM4_PARITY(u32 val)
638 {
639 return (0x9669 >> (0xF & (val ^
640 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^
641 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
642 (val >> 28)))) & 1;
643 }
644
645 /* Maximum number of values that can be executed for one opcode */
646 #define TYPE4_MAX_PAYLOAD 127
647
648 #define PKT4(_reg, _cnt) \
649 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
650 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
651
652 static inline void
OUT_PKT4(struct msm_ringbuffer * ring,uint16_t regindx,uint16_t cnt)653 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
654 {
655 adreno_wait_ring(ring, cnt + 1);
656 OUT_RING(ring, PKT4(regindx, cnt));
657 }
658
659 static inline void
OUT_PKT7(struct msm_ringbuffer * ring,uint8_t opcode,uint16_t cnt)660 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
661 {
662 adreno_wait_ring(ring, cnt + 1);
663 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
664 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
665 }
666
667 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
668 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
669 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
670 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
671 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
672
get_wptr(struct msm_ringbuffer * ring)673 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
674 {
675 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
676 }
677
678 /*
679 * Given a register and a count, return a value to program into
680 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
681 * registers starting at _reg.
682 *
683 * The register base needs to be a multiple of the length. If it is not, the
684 * hardware will quietly mask off the bits for you and shift the size. For
685 * example, if you intend the protection to start at 0x07 for a length of 4
686 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
687 * expose registers you intended to protect!
688 */
689 #define ADRENO_PROTECT_RW(_reg, _len) \
690 ((1 << 30) | (1 << 29) | \
691 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
692
693 /*
694 * Same as above, but allow reads over the range. For areas of mixed use (such
695 * as performance counters) this allows us to protect a much larger range with a
696 * single register
697 */
698 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
699 ((1 << 29) \
700 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
701
702
703 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
704 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
705 interval, timeout)
706
707 #endif /* __ADRENO_GPU_H__ */
708