1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Common library for ADIS16XXX devices
4 *
5 * Copyright 2012 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 */
8
9 #ifndef __IIO_ADIS_H__
10 #define __IIO_ADIS_H__
11
12 #include <linux/cleanup.h>
13 #include <linux/spi/spi.h>
14 #include <linux/interrupt.h>
15 #include <linux/iio/iio.h>
16 #include <linux/iio/types.h>
17
18 #define ADIS_WRITE_REG(reg) ((0x80 | (reg)))
19 #define ADIS_READ_REG(reg) ((reg) & 0x7f)
20
21 #define ADIS_PAGE_SIZE 0x80
22 #define ADIS_REG_PAGE_ID 0x00
23
24 struct adis;
25 struct iio_dev_attr;
26
27 /**
28 * struct adis_timeouts - ADIS chip variant timeouts
29 * @reset_ms - Wait time after rst pin goes inactive
30 * @sw_reset_ms - Wait time after sw reset command
31 * @self_test_ms - Wait time after self test command
32 */
33 struct adis_timeout {
34 u16 reset_ms;
35 u16 sw_reset_ms;
36 u16 self_test_ms;
37 };
38
39 /**
40 * struct adis_data - ADIS chip variant specific data
41 * @read_delay: SPI delay for read operations in us
42 * @write_delay: SPI delay for write operations in us
43 * @cs_change_delay: SPI delay between CS changes in us
44 * @glob_cmd_reg: Register address of the GLOB_CMD register
45 * @msc_ctrl_reg: Register address of the MSC_CTRL register
46 * @diag_stat_reg: Register address of the DIAG_STAT register
47 * @diag_stat_size: Length (in bytes) of the DIAG_STAT register. If 0 the
48 * default length is 2 bytes long.
49 * @prod_id_reg: Register address of the PROD_ID register
50 * @prod_id: Product ID code that should be expected when reading @prod_id_reg
51 * @self_test_mask: Bitmask of supported self-test operations
52 * @self_test_reg: Register address to request self test command
53 * @self_test_no_autoclear: True if device's self-test needs clear of ctrl reg
54 * @status_error_msgs: Array of error messages
55 * @status_error_mask: Bitmask of errors supported by the device
56 * @timeouts: Chip specific delays
57 * @enable_irq: Hook for ADIS devices that have a special IRQ enable/disable
58 * @unmasked_drdy: True for devices that cannot mask/unmask the data ready pin
59 * @has_paging: True if ADIS device has paged registers
60 * @has_fifo: True if ADIS device has a hardware FIFO
61 * @burst_reg_cmd: Register command that triggers burst
62 * @burst_len: Burst size in the SPI RX buffer. If @burst_max_len is defined,
63 * this should be the minimum size supported by the device.
64 * @burst_max_len: Holds the maximum burst size when the device supports
65 * more than one burst mode with different sizes
66 * @burst_max_speed_hz: Maximum spi speed that can be used in burst mode
67 */
68 struct adis_data {
69 unsigned int read_delay;
70 unsigned int write_delay;
71 unsigned int cs_change_delay;
72
73 unsigned int glob_cmd_reg;
74 unsigned int msc_ctrl_reg;
75 unsigned int diag_stat_reg;
76 unsigned int diag_stat_size;
77 unsigned int prod_id_reg;
78
79 unsigned int prod_id;
80
81 unsigned int self_test_mask;
82 unsigned int self_test_reg;
83 bool self_test_no_autoclear;
84 const struct adis_timeout *timeouts;
85
86 const char * const *status_error_msgs;
87 unsigned int status_error_mask;
88
89 int (*enable_irq)(struct adis *adis, bool enable);
90 bool unmasked_drdy;
91
92 bool has_paging;
93 bool has_fifo;
94
95 unsigned int burst_reg_cmd;
96 unsigned int burst_len;
97 unsigned int burst_max_len;
98 unsigned int burst_max_speed_hz;
99 };
100
101 /**
102 * struct adis_ops: Custom ops for adis devices.
103 * @write: Custom spi write implementation.
104 * @read: Custom spi read implementation.
105 * @reset: Custom sw reset implementation. The custom implementation does not
106 * need to sleep after the reset. It's done by the library already.
107 */
108 struct adis_ops {
109 int (*write)(struct adis *adis, unsigned int reg, unsigned int value,
110 unsigned int size);
111 int (*read)(struct adis *adis, unsigned int reg, unsigned int *value,
112 unsigned int size);
113 int (*reset)(struct adis *adis);
114 };
115
116 /**
117 * struct adis - ADIS device instance data
118 * @spi: Reference to SPI device which owns this ADIS IIO device
119 * @trig: IIO trigger object data
120 * @data: ADIS chip variant specific data
121 * @burst_extra_len: Burst extra length. Should only be used by devices that can
122 * dynamically change their burst mode length.
123 * @ops: ops struct for custom read and write functions
124 * @state_lock: Lock used by the device to protect state
125 * @msg: SPI message object
126 * @xfer: SPI transfer objects to be used for a @msg
127 * @current_page: Some ADIS devices have registers, this selects current page
128 * @irq_flag: IRQ handling flags as passed to request_irq()
129 * @buffer: Data buffer for information read from the device
130 * @tx: DMA safe TX buffer for SPI transfers
131 * @rx: DMA safe RX buffer for SPI transfers
132 */
133 struct adis {
134 struct spi_device *spi;
135 struct iio_trigger *trig;
136
137 const struct adis_data *data;
138 unsigned int burst_extra_len;
139 const struct adis_ops *ops;
140 /*
141 * The state_lock is meant to be used during operations that require
142 * a sequence of SPI R/W in order to protect the SPI transfer
143 * information (fields 'xfer', 'msg' & 'current_page') between
144 * potential concurrent accesses.
145 * This lock is used by all "adis_{functions}" that have to read/write
146 * registers. These functions also have unlocked variants
147 * (see "__adis_{functions}"), which don't hold this lock.
148 * This allows users of the ADIS library to group SPI R/W into
149 * the drivers, but they also must manage this lock themselves.
150 */
151 struct mutex state_lock;
152 struct spi_message msg;
153 struct spi_transfer *xfer;
154 unsigned int current_page;
155 unsigned long irq_flag;
156 void *buffer;
157
158 u8 tx[10] __aligned(IIO_DMA_MINALIGN);
159 u8 rx[4];
160 };
161
162 int adis_init(struct adis *adis, struct iio_dev *indio_dev,
163 struct spi_device *spi, const struct adis_data *data);
164 int __adis_reset(struct adis *adis);
165
166 /**
167 * adis_reset() - Reset the device
168 * @adis: The adis device
169 *
170 * Returns: %0 on success, a negative error code otherwise
171 */
adis_reset(struct adis * adis)172 static inline int adis_reset(struct adis *adis)
173 {
174 guard(mutex)(&adis->state_lock);
175 return __adis_reset(adis);
176 }
177
178 int __adis_write_reg(struct adis *adis, unsigned int reg,
179 unsigned int val, unsigned int size);
180 int __adis_read_reg(struct adis *adis, unsigned int reg,
181 unsigned int *val, unsigned int size);
182
183 /**
184 * __adis_write_reg_8() - Write single byte to a register (unlocked)
185 * @adis: The adis device
186 * @reg: The address of the register to be written
187 * @val: The value to write
188 *
189 * Returns: %0 on success, a negative error code otherwise
190 */
__adis_write_reg_8(struct adis * adis,unsigned int reg,u8 val)191 static inline int __adis_write_reg_8(struct adis *adis, unsigned int reg,
192 u8 val)
193 {
194 return adis->ops->write(adis, reg, val, 1);
195 }
196
197 /**
198 * __adis_write_reg_16() - Write 2 bytes to a pair of registers (unlocked)
199 * @adis: The adis device
200 * @reg: The address of the lower of the two registers
201 * @val: Value to be written
202 *
203 * Returns: %0 on success, a negative error code otherwise
204 */
__adis_write_reg_16(struct adis * adis,unsigned int reg,u16 val)205 static inline int __adis_write_reg_16(struct adis *adis, unsigned int reg,
206 u16 val)
207 {
208 return adis->ops->write(adis, reg, val, 2);
209 }
210
211 /**
212 * __adis_write_reg_32() - write 4 bytes to four registers (unlocked)
213 * @adis: The adis device
214 * @reg: The address of the lower of the four register
215 * @val: Value to be written
216 *
217 * Returns: %0 on success, a negative error code otherwise
218 */
__adis_write_reg_32(struct adis * adis,unsigned int reg,u32 val)219 static inline int __adis_write_reg_32(struct adis *adis, unsigned int reg,
220 u32 val)
221 {
222 return adis->ops->write(adis, reg, val, 4);
223 }
224
225 /**
226 * __adis_read_reg_16() - read 2 bytes from a 16-bit register (unlocked)
227 * @adis: The adis device
228 * @reg: The address of the lower of the two registers
229 * @val: The value read back from the device
230 *
231 * Returns: %0 on success, a negative error code otherwise
232 */
__adis_read_reg_16(struct adis * adis,unsigned int reg,u16 * val)233 static inline int __adis_read_reg_16(struct adis *adis, unsigned int reg,
234 u16 *val)
235 {
236 unsigned int tmp;
237 int ret;
238
239 ret = adis->ops->read(adis, reg, &tmp, 2);
240 if (ret == 0)
241 *val = tmp;
242
243 return ret;
244 }
245
246 /**
247 * __adis_read_reg_32() - read 4 bytes from a 32-bit register (unlocked)
248 * @adis: The adis device
249 * @reg: The address of the lower of the two registers
250 * @val: The value read back from the device
251 *
252 * Returns: %0 on success, a negative error code otherwise
253 */
__adis_read_reg_32(struct adis * adis,unsigned int reg,u32 * val)254 static inline int __adis_read_reg_32(struct adis *adis, unsigned int reg,
255 u32 *val)
256 {
257 unsigned int tmp;
258 int ret;
259
260 ret = adis->ops->read(adis, reg, &tmp, 4);
261 if (ret == 0)
262 *val = tmp;
263
264 return ret;
265 }
266
267 /**
268 * adis_write_reg() - write N bytes to register
269 * @adis: The adis device
270 * @reg: The address of the lower of the two registers
271 * @val: The value to write to device (up to 4 bytes)
272 * @size: The size of the @value (in bytes)
273 *
274 * Returns: %0 on success, a negative error code otherwise
275 */
adis_write_reg(struct adis * adis,unsigned int reg,unsigned int val,unsigned int size)276 static inline int adis_write_reg(struct adis *adis, unsigned int reg,
277 unsigned int val, unsigned int size)
278 {
279 guard(mutex)(&adis->state_lock);
280 return adis->ops->write(adis, reg, val, size);
281 }
282
283 /**
284 * adis_read_reg() - read N bytes from register
285 * @adis: The adis device
286 * @reg: The address of the lower of the two registers
287 * @val: The value read back from the device
288 * @size: The size of the @val buffer
289 *
290 * Returns: %0 on success, a negative error code otherwise
291 */
adis_read_reg(struct adis * adis,unsigned int reg,unsigned int * val,unsigned int size)292 static int adis_read_reg(struct adis *adis, unsigned int reg,
293 unsigned int *val, unsigned int size)
294 {
295 guard(mutex)(&adis->state_lock);
296 return adis->ops->read(adis, reg, val, size);
297 }
298
299 /**
300 * adis_write_reg_8() - Write single byte to a register
301 * @adis: The adis device
302 * @reg: The address of the register to be written
303 * @val: The value to write
304 *
305 * Returns: %0 on success, a negative error code otherwise
306 */
adis_write_reg_8(struct adis * adis,unsigned int reg,u8 val)307 static inline int adis_write_reg_8(struct adis *adis, unsigned int reg,
308 u8 val)
309 {
310 return adis_write_reg(adis, reg, val, 1);
311 }
312
313 /**
314 * adis_write_reg_16() - Write 2 bytes to a pair of registers
315 * @adis: The adis device
316 * @reg: The address of the lower of the two registers
317 * @val: Value to be written
318 *
319 * Returns: %0 on success, a negative error code otherwise
320 */
adis_write_reg_16(struct adis * adis,unsigned int reg,u16 val)321 static inline int adis_write_reg_16(struct adis *adis, unsigned int reg,
322 u16 val)
323 {
324 return adis_write_reg(adis, reg, val, 2);
325 }
326
327 /**
328 * adis_write_reg_32() - write 4 bytes to four registers
329 * @adis: The adis device
330 * @reg: The address of the lower of the four register
331 * @val: Value to be written
332 *
333 * Returns: %0 on success, a negative error code otherwise
334 */
adis_write_reg_32(struct adis * adis,unsigned int reg,u32 val)335 static inline int adis_write_reg_32(struct adis *adis, unsigned int reg,
336 u32 val)
337 {
338 return adis_write_reg(adis, reg, val, 4);
339 }
340
341 /**
342 * adis_read_reg_16() - read 2 bytes from a 16-bit register
343 * @adis: The adis device
344 * @reg: The address of the lower of the two registers
345 * @val: The value read back from the device
346 *
347 * Returns: %0 on success, a negative error code otherwise
348 */
adis_read_reg_16(struct adis * adis,unsigned int reg,u16 * val)349 static inline int adis_read_reg_16(struct adis *adis, unsigned int reg,
350 u16 *val)
351 {
352 unsigned int tmp;
353 int ret;
354
355 ret = adis_read_reg(adis, reg, &tmp, 2);
356 if (ret == 0)
357 *val = tmp;
358
359 return ret;
360 }
361
362 /**
363 * adis_read_reg_32() - read 4 bytes from a 32-bit register
364 * @adis: The adis device
365 * @reg: The address of the lower of the two registers
366 * @val: The value read back from the device
367 *
368 * Returns: %0 on success, a negative error code otherwise
369 */
adis_read_reg_32(struct adis * adis,unsigned int reg,u32 * val)370 static inline int adis_read_reg_32(struct adis *adis, unsigned int reg,
371 u32 *val)
372 {
373 unsigned int tmp;
374 int ret;
375
376 ret = adis_read_reg(adis, reg, &tmp, 4);
377 if (ret == 0)
378 *val = tmp;
379
380 return ret;
381 }
382
383 int __adis_update_bits_base(struct adis *adis, unsigned int reg, const u32 mask,
384 const u32 val, u8 size);
385 /**
386 * adis_update_bits_base() - ADIS Update bits function - Locked version
387 * @adis: The adis device
388 * @reg: The address of the lower of the two registers
389 * @mask: Bitmask to change
390 * @val: Value to be written
391 * @size: Size of the register to update
392 *
393 * Updates the desired bits of @reg in accordance with @mask and @val.
394 *
395 * Returns: %0 on success, a negative error code otherwise
396 */
adis_update_bits_base(struct adis * adis,unsigned int reg,const u32 mask,const u32 val,u8 size)397 static inline int adis_update_bits_base(struct adis *adis, unsigned int reg,
398 const u32 mask, const u32 val, u8 size)
399 {
400 guard(mutex)(&adis->state_lock);
401 return __adis_update_bits_base(adis, reg, mask, val, size);
402 }
403
404 /**
405 * adis_update_bits() - Wrapper macro for adis_update_bits_base - Locked version
406 * @adis: The adis device
407 * @reg: The address of the lower of the two registers
408 * @mask: Bitmask to change
409 * @val: Value to be written
410 *
411 * This macro evaluates the sizeof of @val at compile time and calls
412 * adis_update_bits_base() accordingly. Be aware that using MACROS/DEFINES for
413 * @val can lead to undesired behavior if the register to update is 16bit.
414 */
415 #define adis_update_bits(adis, reg, mask, val) ({ \
416 BUILD_BUG_ON(sizeof(val) != 2 && sizeof(val) != 4); \
417 adis_update_bits_base(adis, reg, mask, val, sizeof(val)); \
418 })
419
420 /**
421 * adis_update_bits() - Wrapper macro for adis_update_bits_base
422 * @adis: The adis device
423 * @reg: The address of the lower of the two registers
424 * @mask: Bitmask to change
425 * @val: Value to be written
426 *
427 * This macro evaluates the sizeof of @val at compile time and calls
428 * adis_update_bits_base() accordingly. Be aware that using MACROS/DEFINES for
429 * @val can lead to undesired behavior if the register to update is 16bit.
430 */
431 #define __adis_update_bits(adis, reg, mask, val) ({ \
432 BUILD_BUG_ON(sizeof(val) != 2 && sizeof(val) != 4); \
433 __adis_update_bits_base(adis, reg, mask, val, sizeof(val)); \
434 })
435
436 int __adis_check_status(struct adis *adis);
437 int __adis_initial_startup(struct adis *adis);
438 int __adis_enable_irq(struct adis *adis, bool enable);
439
adis_enable_irq(struct adis * adis,bool enable)440 static inline int adis_enable_irq(struct adis *adis, bool enable)
441 {
442 guard(mutex)(&adis->state_lock);
443 return __adis_enable_irq(adis, enable);
444 }
445
adis_check_status(struct adis * adis)446 static inline int adis_check_status(struct adis *adis)
447 {
448 guard(mutex)(&adis->state_lock);
449 return __adis_check_status(adis);
450 }
451
452 #define adis_dev_auto_lock(adis) guard(mutex)(&(adis)->state_lock)
453 #define adis_dev_auto_scoped_lock(adis) \
454 scoped_guard(mutex, &(adis)->state_lock)
455
456 int adis_single_conversion(struct iio_dev *indio_dev,
457 const struct iio_chan_spec *chan,
458 unsigned int error_mask, int *val);
459
460 #define ADIS_VOLTAGE_CHAN(addr, si, chan, name, info_all, bits) { \
461 .type = IIO_VOLTAGE, \
462 .indexed = 1, \
463 .channel = (chan), \
464 .extend_name = name, \
465 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
466 BIT(IIO_CHAN_INFO_SCALE), \
467 .info_mask_shared_by_all = info_all, \
468 .address = (addr), \
469 .scan_index = (si), \
470 .scan_type = { \
471 .sign = 'u', \
472 .realbits = (bits), \
473 .storagebits = 16, \
474 .endianness = IIO_BE, \
475 }, \
476 }
477
478 #define ADIS_SUPPLY_CHAN(addr, si, info_all, bits) \
479 ADIS_VOLTAGE_CHAN(addr, si, 0, "supply", info_all, bits)
480
481 #define ADIS_AUX_ADC_CHAN(addr, si, info_all, bits) \
482 ADIS_VOLTAGE_CHAN(addr, si, 1, NULL, info_all, bits)
483
484 #define ADIS_TEMP_CHAN(addr, si, info_all, bits) { \
485 .type = IIO_TEMP, \
486 .indexed = 1, \
487 .channel = 0, \
488 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
489 BIT(IIO_CHAN_INFO_SCALE) | \
490 BIT(IIO_CHAN_INFO_OFFSET), \
491 .info_mask_shared_by_all = info_all, \
492 .address = (addr), \
493 .scan_index = (si), \
494 .scan_type = { \
495 .sign = 'u', \
496 .realbits = (bits), \
497 .storagebits = 16, \
498 .endianness = IIO_BE, \
499 }, \
500 }
501
502 #define ADIS_MOD_CHAN(_type, mod, addr, si, info_sep, info_all, bits) { \
503 .type = (_type), \
504 .modified = 1, \
505 .channel2 = IIO_MOD_ ## mod, \
506 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
507 (info_sep), \
508 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
509 .info_mask_shared_by_all = info_all, \
510 .address = (addr), \
511 .scan_index = (si), \
512 .scan_type = { \
513 .sign = 's', \
514 .realbits = (bits), \
515 .storagebits = 16, \
516 .endianness = IIO_BE, \
517 }, \
518 }
519
520 #define ADIS_ACCEL_CHAN(mod, addr, si, info_sep, info_all, bits) \
521 ADIS_MOD_CHAN(IIO_ACCEL, mod, addr, si, info_sep, info_all, bits)
522
523 #define ADIS_GYRO_CHAN(mod, addr, si, info_sep, info_all, bits) \
524 ADIS_MOD_CHAN(IIO_ANGL_VEL, mod, addr, si, info_sep, info_all, bits)
525
526 #define ADIS_INCLI_CHAN(mod, addr, si, info_sep, info_all, bits) \
527 ADIS_MOD_CHAN(IIO_INCLI, mod, addr, si, info_sep, info_all, bits)
528
529 #define ADIS_ROT_CHAN(mod, addr, si, info_sep, info_all, bits) \
530 ADIS_MOD_CHAN(IIO_ROT, mod, addr, si, info_sep, info_all, bits)
531
532 #define devm_adis_setup_buffer_and_trigger(adis, indio_dev, trigger_handler) \
533 devm_adis_setup_buffer_and_trigger_with_attrs((adis), (indio_dev), \
534 (trigger_handler), NULL, \
535 NULL)
536
537 #ifdef CONFIG_IIO_ADIS_LIB_BUFFER
538
539 int
540 devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis,
541 struct iio_dev *indio_dev,
542 irq_handler_t trigger_handler,
543 const struct iio_buffer_setup_ops *ops,
544 const struct iio_dev_attr **buffer_attrs);
545
546 int devm_adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev);
547
548 int adis_update_scan_mode(struct iio_dev *indio_dev,
549 const unsigned long *scan_mask);
550
551 #else /* CONFIG_IIO_BUFFER */
552
553 static inline int
devm_adis_setup_buffer_and_trigger_with_attrs(struct adis * adis,struct iio_dev * indio_dev,irq_handler_t trigger_handler,const struct iio_buffer_setup_ops * ops,const struct iio_dev_attr ** buffer_attrs)554 devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis,
555 struct iio_dev *indio_dev,
556 irq_handler_t trigger_handler,
557 const struct iio_buffer_setup_ops *ops,
558 const struct iio_dev_attr **buffer_attrs)
559 {
560 return 0;
561 }
562
devm_adis_probe_trigger(struct adis * adis,struct iio_dev * indio_dev)563 static inline int devm_adis_probe_trigger(struct adis *adis,
564 struct iio_dev *indio_dev)
565 {
566 return 0;
567 }
568
569 #define adis_update_scan_mode NULL
570
571 #endif /* CONFIG_IIO_BUFFER */
572
573 #ifdef CONFIG_DEBUG_FS
574
575 int adis_debugfs_reg_access(struct iio_dev *indio_dev,
576 unsigned int reg, unsigned int writeval,
577 unsigned int *readval);
578
579 #else
580
581 #define adis_debugfs_reg_access NULL
582
583 #endif
584
585 #endif
586