1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2020 Intel Corporation */ 3 #ifndef ADF_GEN2_HW_DATA_H_ 4 #define ADF_GEN2_HW_DATA_H_ 5 6 #include "adf_accel_devices.h" 7 #include "adf_cfg_common.h" 8 9 #define ADF_GEN2_RX_RINGS_OFFSET 8 10 #define ADF_GEN2_TX_RINGS_MASK 0xFF 11 12 /* AE to function map */ 13 #define AE2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190) 14 #define AE2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310) 15 #define AE2FUNCTION_MAP_REG_SIZE 4 16 #define AE2FUNCTION_MAP_VALID BIT(7) 17 18 #define READ_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index) \ 19 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \ 20 AE2FUNCTION_MAP_REG_SIZE * (index)) 21 #define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \ 22 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \ 23 AE2FUNCTION_MAP_REG_SIZE * (index), value) 24 #define READ_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index) \ 25 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \ 26 AE2FUNCTION_MAP_REG_SIZE * (index)) 27 #define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \ 28 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \ 29 AE2FUNCTION_MAP_REG_SIZE * (index), value) 30 31 /* Admin Interface Offsets */ 32 #define ADF_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 33 #define ADF_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 34 #define ADF_MAILBOX_BASE_OFFSET 0x20970 35 36 /* Arbiter configuration */ 37 #define ADF_ARB_OFFSET 0x30000 38 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180 39 #define ADF_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0)) 40 41 /* Power gating */ 42 #define ADF_POWERGATE_DC BIT(23) 43 #define ADF_POWERGATE_PKE BIT(24) 44 45 /* Default ring mapping */ 46 #define ADF_GEN2_DEFAULT_RING_TO_SRV_MAP \ 47 (CRYPTO << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \ 48 CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \ 49 UNUSED << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \ 50 COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT) 51 52 /* WDT timers 53 * 54 * Timeout is in cycles. Clock speed may vary across products but this 55 * value should be a few milli-seconds. 56 */ 57 #define ADF_SSM_WDT_DEFAULT_VALUE 0x200000 58 #define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x2000000 59 #define ADF_SSMWDT_OFFSET 0x54 60 #define ADF_SSMWDTPKE_OFFSET 0x58 61 #define ADF_SSMWDT(i) (ADF_SSMWDT_OFFSET + ((i) * 0x4000)) 62 #define ADF_SSMWDTPKE(i) (ADF_SSMWDTPKE_OFFSET + ((i) * 0x4000)) 63 64 /* Error detection and correction */ 65 #define ADF_GEN2_AE_CTX_ENABLES(i) ((i) * 0x1000 + 0x20818) 66 #define ADF_GEN2_AE_MISC_CONTROL(i) ((i) * 0x1000 + 0x20960) 67 #define ADF_GEN2_ENABLE_AE_ECC_ERR BIT(28) 68 #define ADF_GEN2_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 69 #define ADF_GEN2_UERRSSMSH(i) ((i) * 0x4000 + 0x18) 70 #define ADF_GEN2_CERRSSMSH(i) ((i) * 0x4000 + 0x10) 71 #define ADF_GEN2_ERRSSMSH_EN BIT(3) 72 73 /* Number of heartbeat counter pairs */ 74 #define ADF_NUM_HB_CNT_PER_AE ADF_NUM_THREADS_PER_AE 75 76 /* Interrupts */ 77 #define ADF_GEN2_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28) 78 #define ADF_GEN2_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) 79 #define ADF_GEN2_SMIA1_MASK 0x1 80 81 u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self); 82 u32 adf_gen2_get_num_aes(struct adf_hw_device_data *self); 83 void adf_gen2_enable_error_correction(struct adf_accel_dev *accel_dev); 84 void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable, 85 int num_a_regs, int num_b_regs); 86 void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info); 87 void adf_gen2_get_arb_info(struct arb_info *arb_info); 88 void adf_gen2_enable_ints(struct adf_accel_dev *accel_dev); 89 u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev); 90 void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev); 91 92 #endif 93