1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADF4377 driver
4 *
5 * Copyright 2022 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/container_of.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/module.h>
18 #include <linux/notifier.h>
19 #include <linux/property.h>
20 #include <linux/spi/spi.h>
21 #include <linux/iio/iio.h>
22 #include <linux/regmap.h>
23 #include <linux/units.h>
24
25 #include <linux/unaligned.h>
26
27 /* ADF4377 REG0000 Map */
28 #define ADF4377_0000_SOFT_RESET_R_MSK BIT(7)
29 #define ADF4377_0000_LSB_FIRST_R_MSK BIT(6)
30 #define ADF4377_0000_ADDRESS_ASC_R_MSK BIT(5)
31 #define ADF4377_0000_SDO_ACTIVE_R_MSK BIT(4)
32 #define ADF4377_0000_SDO_ACTIVE_MSK BIT(3)
33 #define ADF4377_0000_ADDRESS_ASC_MSK BIT(2)
34 #define ADF4377_0000_LSB_FIRST_MSK BIT(1)
35 #define ADF4377_0000_SOFT_RESET_MSK BIT(0)
36
37 /* ADF4377 REG0000 Bit Definition */
38 #define ADF4377_0000_SDO_ACTIVE_SPI_3W 0x0
39 #define ADF4377_0000_SDO_ACTIVE_SPI_4W 0x1
40
41 #define ADF4377_0000_ADDR_ASC_AUTO_DECR 0x0
42 #define ADF4377_0000_ADDR_ASC_AUTO_INCR 0x1
43
44 #define ADF4377_0000_LSB_FIRST_MSB 0x0
45 #define ADF4377_0000_LSB_FIRST_LSB 0x1
46
47 #define ADF4377_0000_SOFT_RESET_N_OP 0x0
48 #define ADF4377_0000_SOFT_RESET_EN 0x1
49
50 /* ADF4377 REG0001 Map */
51 #define ADF4377_0001_SINGLE_INSTR_MSK BIT(7)
52 #define ADF4377_0001_MASTER_RB_CTRL_MSK BIT(5)
53
54 /* ADF4377 REG0003 Bit Definition */
55 #define ADF4377_0003_CHIP_TYPE 0x06
56
57 /* ADF4377 REG0004 Bit Definition */
58 #define ADF4377_0004_PRODUCT_ID_LSB 0x0005
59
60 /* ADF4377 REG0005 Bit Definition */
61 #define ADF4377_0005_PRODUCT_ID_MSB 0x0005
62
63 /* ADF4377 REG000A Map */
64 #define ADF4377_000A_SCRATCHPAD_MSK GENMASK(7, 0)
65
66 /* ADF4377 REG000C Bit Definition */
67 #define ADF4377_000C_VENDOR_ID_LSB 0x56
68
69 /* ADF4377 REG000D Bit Definition */
70 #define ADF4377_000D_VENDOR_ID_MSB 0x04
71
72 /* ADF4377 REG000F Bit Definition */
73 #define ADF4377_000F_R00F_RSV1_MSK GENMASK(7, 0)
74
75 /* ADF4377 REG0010 Map*/
76 #define ADF4377_0010_N_INT_LSB_MSK GENMASK(7, 0)
77
78 /* ADF4377 REG0011 Map*/
79 #define ADF4377_0011_EN_AUTOCAL_MSK BIT(7)
80 #define ADF4377_0011_EN_RDBLR_MSK BIT(6)
81 #define ADF4377_0011_DCLK_DIV2_MSK GENMASK(5, 4)
82 #define ADF4377_0011_N_INT_MSB_MSK GENMASK(3, 0)
83
84 /* ADF4377 REG0011 Bit Definition */
85 #define ADF4377_0011_DCLK_DIV2_1 0x0
86 #define ADF4377_0011_DCLK_DIV2_2 0x1
87 #define ADF4377_0011_DCLK_DIV2_4 0x2
88 #define ADF4377_0011_DCLK_DIV2_8 0x3
89
90 /* ADF4377 REG0012 Map*/
91 #define ADF4377_0012_CLKOUT_DIV_MSK GENMASK(7, 6)
92 #define ADF4377_0012_R_DIV_MSK GENMASK(5, 0)
93
94 /* ADF4377 REG0012 Bit Definition */
95 #define ADF4377_0012_CLKOUT_DIV_1 0x0
96 #define ADF4377_0012_CLKOUT_DIV_2 0x1
97 #define ADF4377_0012_CLKOUT_DIV_4 0x2
98 #define ADF4377_0012_CLKOUT_DIV_8 0x3
99
100 /* ADF4377 REG0013 Map */
101 #define ADF4377_0013_M_VCO_CORE_MSK GENMASK(5, 4)
102 #define ADF4377_0013_VCO_BIAS_MSK GENMASK(3, 0)
103
104 /* ADF4377 REG0013 Bit Definition */
105 #define ADF4377_0013_M_VCO_0 0x0
106 #define ADF4377_0013_M_VCO_1 0x1
107 #define ADF4377_0013_M_VCO_2 0x2
108 #define ADF4377_0013_M_VCO_3 0x3
109
110 /* ADF4377 REG0014 Map */
111 #define ADF4377_0014_M_VCO_BAND_MSK GENMASK(7, 0)
112
113 /* ADF4377 REG0015 Map */
114 #define ADF4377_0015_BLEED_I_LSB_MSK GENMASK(7, 6)
115 #define ADF4377_0015_BLEED_POL_MSK BIT(5)
116 #define ADF4377_0015_EN_BLEED_MSK BIT(4)
117 #define ADF4377_0015_CP_I_MSK GENMASK(3, 0)
118
119 /* ADF4377 REG0015 Bit Definition */
120 #define ADF4377_CURRENT_SINK 0x0
121 #define ADF4377_CURRENT_SOURCE 0x1
122
123 #define ADF4377_0015_CP_0MA7 0x0
124 #define ADF4377_0015_CP_0MA9 0x1
125 #define ADF4377_0015_CP_1MA1 0x2
126 #define ADF4377_0015_CP_1MA3 0x3
127 #define ADF4377_0015_CP_1MA4 0x4
128 #define ADF4377_0015_CP_1MA8 0x5
129 #define ADF4377_0015_CP_2MA2 0x6
130 #define ADF4377_0015_CP_2MA5 0x7
131 #define ADF4377_0015_CP_2MA9 0x8
132 #define ADF4377_0015_CP_3MA6 0x9
133 #define ADF4377_0015_CP_4MA3 0xA
134 #define ADF4377_0015_CP_5MA0 0xB
135 #define ADF4377_0015_CP_5MA7 0xC
136 #define ADF4377_0015_CP_7MA2 0xD
137 #define ADF4377_0015_CP_8MA6 0xE
138 #define ADF4377_0015_CP_10MA1 0xF
139
140 /* ADF4377 REG0016 Map */
141 #define ADF4377_0016_BLEED_I_MSB_MSK GENMASK(7, 0)
142
143 /* ADF4377 REG0017 Map */
144 #define ADF4377_0016_INV_CLKOUT_MSK BIT(7)
145 #define ADF4377_0016_N_DEL_MSK GENMASK(6, 0)
146
147 /* ADF4377 REG0018 Map */
148 #define ADF4377_0018_CMOS_OV_MSK BIT(7)
149 #define ADF4377_0018_R_DEL_MSK GENMASK(6, 0)
150
151 /* ADF4377 REG0018 Bit Definition */
152 #define ADF4377_0018_1V8_LOGIC 0x0
153 #define ADF4377_0018_3V3_LOGIC 0x1
154
155 /* ADF4377 REG0019 Map */
156 #define ADF4377_0019_CLKOUT2_OP_MSK GENMASK(7, 6)
157 #define ADF4377_0019_CLKOUT1_OP_MSK GENMASK(5, 4)
158 #define ADF4377_0019_PD_CLK_MSK BIT(3)
159 #define ADF4377_0019_PD_RDET_MSK BIT(2)
160 #define ADF4377_0019_PD_ADC_MSK BIT(1)
161 #define ADF4377_0019_PD_CALADC_MSK BIT(0)
162
163 /* ADF4377 REG0019 Bit Definition */
164 #define ADF4377_0019_CLKOUT_320MV 0x0
165 #define ADF4377_0019_CLKOUT_420MV 0x1
166 #define ADF4377_0019_CLKOUT_530MV 0x2
167 #define ADF4377_0019_CLKOUT_640MV 0x3
168
169 /* ADF4377 REG001A Map */
170 #define ADF4377_001A_PD_ALL_MSK BIT(7)
171 #define ADF4377_001A_PD_RDIV_MSK BIT(6)
172 #define ADF4377_001A_PD_NDIV_MSK BIT(5)
173 #define ADF4377_001A_PD_VCO_MSK BIT(4)
174 #define ADF4377_001A_PD_LD_MSK BIT(3)
175 #define ADF4377_001A_PD_PFDCP_MSK BIT(2)
176 #define ADF4377_001A_PD_CLKOUT1_MSK BIT(1)
177 #define ADF4377_001A_PD_CLKOUT2_MSK BIT(0)
178
179 /* ADF4377 REG001B Map */
180 #define ADF4377_001B_EN_LOL_MSK BIT(7)
181 #define ADF4377_001B_LDWIN_PW_MSK BIT(6)
182 #define ADF4377_001B_EN_LDWIN_MSK BIT(5)
183 #define ADF4377_001B_LD_COUNT_MSK GENMASK(4, 0)
184
185 /* ADF4377 REG001B Bit Definition */
186 #define ADF4377_001B_LDWIN_PW_NARROW 0x0
187 #define ADF4377_001B_LDWIN_PW_WIDE 0x1
188
189 /* ADF4377 REG001C Map */
190 #define ADF4377_001C_EN_DNCLK_MSK BIT(7)
191 #define ADF4377_001C_EN_DRCLK_MSK BIT(6)
192 #define ADF4377_001C_RST_LD_MSK BIT(2)
193 #define ADF4377_001C_R01C_RSV1_MSK BIT(0)
194
195 /* ADF4377 REG001C Bit Definition */
196 #define ADF4377_001C_RST_LD_INACTIVE 0x0
197 #define ADF4377_001C_RST_LD_ACTIVE 0x1
198
199 #define ADF4377_001C_R01C_RSV1 0x1
200
201 /* ADF4377 REG001D Map */
202 #define ADF4377_001D_MUXOUT_MSK GENMASK(7, 4)
203 #define ADF4377_001D_EN_CPTEST_MSK BIT(2)
204 #define ADF4377_001D_CP_DOWN_MSK BIT(1)
205 #define ADF4377_001D_CP_UP_MSK BIT(0)
206
207 #define ADF4377_001D_EN_CPTEST_OFF 0x0
208 #define ADF4377_001D_EN_CPTEST_ON 0x1
209
210 #define ADF4377_001D_CP_DOWN_OFF 0x0
211 #define ADF4377_001D_CP_DOWN_ON 0x1
212
213 #define ADF4377_001D_CP_UP_OFF 0x0
214 #define ADF4377_001D_CP_UP_ON 0x1
215
216 /* ADF4377 REG001F Map */
217 #define ADF4377_001F_BST_REF_MSK BIT(7)
218 #define ADF4377_001F_FILT_REF_MSK BIT(6)
219 #define ADF4377_001F_REF_SEL_MSK BIT(5)
220 #define ADF4377_001F_R01F_RSV1_MSK GENMASK(4, 0)
221
222 /* ADF4377 REG001F Bit Definition */
223 #define ADF4377_001F_BST_LARGE_REF_IN 0x0
224 #define ADF4377_001F_BST_SMALL_REF_IN 0x1
225
226 #define ADF4377_001F_FILT_REF_OFF 0x0
227 #define ADF4377_001F_FILT_REF_ON 0x1
228
229 #define ADF4377_001F_REF_SEL_DMA 0x0
230 #define ADF4377_001F_REF_SEL_LNA 0x1
231
232 #define ADF4377_001F_R01F_RSV1 0x7
233
234 /* ADF4377 REG0020 Map */
235 #define ADF4377_0020_RST_SYS_MSK BIT(4)
236 #define ADF4377_0020_EN_ADC_CLK_MSK BIT(3)
237 #define ADF4377_0020_R020_RSV1_MSK BIT(0)
238
239 /* ADF4377 REG0021 Bit Definition */
240 #define ADF4377_0021_R021_RSV1 0xD3
241
242 /* ADF4377 REG0022 Bit Definition */
243 #define ADF4377_0022_R022_RSV1 0x32
244
245 /* ADF4377 REG0023 Map */
246 #define ADF4377_0023_CAT_CT_SEL BIT(7)
247 #define ADF4377_0023_R023_RSV1_MSK GENMASK(6, 0)
248
249 /* ADF4377 REG0023 Bit Definition */
250 #define ADF4377_0023_R023_RSV1 0x18
251
252 /* ADF4377 REG0024 Map */
253 #define ADF4377_0024_DCLK_MODE_MSK BIT(2)
254
255 /* ADF4377 REG0025 Map */
256 #define ADF4377_0025_CLKODIV_DB_MSK BIT(7)
257 #define ADF4377_0025_DCLK_DB_MSK BIT(6)
258 #define ADF4377_0025_R025_RSV1_MSK GENMASK(5, 0)
259
260 /* ADF4377 REG0025 Bit Definition */
261 #define ADF4377_0025_R025_RSV1 0x16
262
263 /* ADF4377 REG0026 Map */
264 #define ADF4377_0026_VCO_BAND_DIV_MSK GENMASK(7, 0)
265
266 /* ADF4377 REG0027 Map */
267 #define ADF4377_0027_SYNTH_LOCK_TO_LSB_MSK GENMASK(7, 0)
268
269 /* ADF4377 REG0028 Map */
270 #define ADF4377_0028_O_VCO_DB_MSK BIT(7)
271 #define ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK GENMASK(6, 0)
272
273 /* ADF4377 REG0029 Map */
274 #define ADF4377_0029_VCO_ALC_TO_LSB_MSK GENMASK(7, 0)
275
276 /* ADF4377 REG002A Map */
277 #define ADF4377_002A_DEL_CTRL_DB_MSK BIT(7)
278 #define ADF4377_002A_VCO_ALC_TO_MSB_MSK GENMASK(6, 0)
279
280 /* ADF4377 REG002C Map */
281 #define ADF4377_002C_R02C_RSV1 0xC0
282
283 /* ADF4377 REG002D Map */
284 #define ADF4377_002D_ADC_CLK_DIV_MSK GENMASK(7, 0)
285
286 /* ADF4377 REG002E Map */
287 #define ADF4377_002E_EN_ADC_CNV_MSK BIT(7)
288 #define ADF4377_002E_EN_ADC_MSK BIT(1)
289 #define ADF4377_002E_ADC_A_CONV_MSK BIT(0)
290
291 /* ADF4377 REG002E Bit Definition */
292 #define ADF4377_002E_ADC_A_CONV_ADC_ST_CNV 0x0
293 #define ADF4377_002E_ADC_A_CONV_VCO_CALIB 0x1
294
295 /* ADF4377 REG002F Map */
296 #define ADF4377_002F_DCLK_DIV1_MSK GENMASK(1, 0)
297
298 /* ADF4377 REG002F Bit Definition */
299 #define ADF4377_002F_DCLK_DIV1_1 0x0
300 #define ADF4377_002F_DCLK_DIV1_2 0x1
301 #define ADF4377_002F_DCLK_DIV1_8 0x2
302 #define ADF4377_002F_DCLK_DIV1_32 0x3
303
304 /* ADF4377 REG0031 Bit Definition */
305 #define ADF4377_0031_R031_RSV1 0x09
306
307 /* ADF4377 REG0032 Map */
308 #define ADF4377_0032_ADC_CLK_SEL_MSK BIT(6)
309 #define ADF4377_0032_R032_RSV1_MSK GENMASK(5, 0)
310
311 /* ADF4377 REG0032 Bit Definition */
312 #define ADF4377_0032_ADC_CLK_SEL_N_OP 0x0
313 #define ADF4377_0032_ADC_CLK_SEL_SPI_CLK 0x1
314
315 #define ADF4377_0032_R032_RSV1 0x9
316
317 /* ADF4377 REG0033 Bit Definition */
318 #define ADF4377_0033_R033_RSV1 0x18
319
320 /* ADF4377 REG0034 Bit Definition */
321 #define ADF4377_0034_R034_RSV1 0x08
322
323 /* ADF4377 REG003A Bit Definition */
324 #define ADF4377_003A_R03A_RSV1 0x5D
325
326 /* ADF4377 REG003B Bit Definition */
327 #define ADF4377_003B_R03B_RSV1 0x2B
328
329 /* ADF4377 REG003D Map */
330 #define ADF4377_003D_O_VCO_BAND_MSK BIT(3)
331 #define ADF4377_003D_O_VCO_CORE_MSK BIT(2)
332 #define ADF4377_003D_O_VCO_BIAS_MSK BIT(1)
333
334 /* ADF4377 REG003D Bit Definition */
335 #define ADF4377_003D_O_VCO_BAND_VCO_CALIB 0x0
336 #define ADF4377_003D_O_VCO_BAND_M_VCO 0x1
337
338 #define ADF4377_003D_O_VCO_CORE_VCO_CALIB 0x0
339 #define ADF4377_003D_O_VCO_CORE_M_VCO 0x1
340
341 #define ADF4377_003D_O_VCO_BIAS_VCO_CALIB 0x0
342 #define ADF4377_003D_O_VCO_BIAS_M_VCO 0x1
343
344 /* ADF4377 REG0042 Map */
345 #define ADF4377_0042_R042_RSV1 0x05
346
347 /* ADF4377 REG0045 Map */
348 #define ADF4377_0045_ADC_ST_CNV_MSK BIT(0)
349
350 /* ADF4377 REG0049 Map */
351 #define ADF4377_0049_EN_CLK2_MSK BIT(7)
352 #define ADF4377_0049_EN_CLK1_MSK BIT(6)
353 #define ADF4377_0049_REF_OK_MSK BIT(3)
354 #define ADF4377_0049_ADC_BUSY_MSK BIT(2)
355 #define ADF4377_0049_FSM_BUSY_MSK BIT(1)
356 #define ADF4377_0049_LOCKED_MSK BIT(0)
357
358 /* ADF4377 REG004B Map */
359 #define ADF4377_004B_VCO_CORE_MSK GENMASK(1, 0)
360
361 /* ADF4377 REG004C Map */
362 #define ADF4377_004C_CHIP_TEMP_LSB_MSK GENMASK(7, 0)
363
364 /* ADF4377 REG004D Map */
365 #define ADF4377_004D_CHIP_TEMP_MSB_MSK BIT(0)
366
367 /* ADF4377 REG004F Map */
368 #define ADF4377_004F_VCO_BAND_MSK GENMASK(7, 0)
369
370 /* ADF4377 REG0051 Map */
371 #define ADF4377_0051_VCO_BIAS_MSK GENMASK(3, 0)
372
373 /* ADF4377 REG0054 Map */
374 #define ADF4377_0054_CHIP_VERSION_MSK GENMASK(7, 0)
375
376 /* Specifications */
377 #define ADF4377_SPI_READ_CMD BIT(7)
378 #define ADF4377_MAX_VCO_FREQ (12800ULL * HZ_PER_MHZ)
379 #define ADF4377_MIN_VCO_FREQ (6400ULL * HZ_PER_MHZ)
380 #define ADF4377_MAX_REFIN_FREQ (1000 * HZ_PER_MHZ)
381 #define ADF4377_MIN_REFIN_FREQ (10 * HZ_PER_MHZ)
382 #define ADF4377_MAX_FREQ_PFD (500 * HZ_PER_MHZ)
383 #define ADF4377_MIN_FREQ_PFD (3 * HZ_PER_MHZ)
384 #define ADF4377_MAX_CLKPN_FREQ ADF4377_MAX_VCO_FREQ
385 #define ADF4377_MIN_CLKPN_FREQ (ADF4377_MIN_VCO_FREQ / 8)
386 #define ADF4377_FREQ_PFD_80MHZ (80 * HZ_PER_MHZ)
387 #define ADF4377_FREQ_PFD_125MHZ (125 * HZ_PER_MHZ)
388 #define ADF4377_FREQ_PFD_160MHZ (160 * HZ_PER_MHZ)
389 #define ADF4377_FREQ_PFD_250MHZ (250 * HZ_PER_MHZ)
390 #define ADF4377_FREQ_PFD_320MHZ (320 * HZ_PER_MHZ)
391
392 enum {
393 ADF4377_FREQ,
394 };
395
396 enum muxout_select_mode {
397 ADF4377_MUXOUT_HIGH_Z = 0x0,
398 ADF4377_MUXOUT_LKDET = 0x1,
399 ADF4377_MUXOUT_LOW = 0x2,
400 ADF4377_MUXOUT_DIV_RCLK_2 = 0x4,
401 ADF4377_MUXOUT_DIV_NCLK_2 = 0x5,
402 ADF4377_MUXOUT_HIGH = 0x8,
403 };
404
405 struct adf4377_chip_info {
406 const char *name;
407 bool has_gpio_enclk2;
408 };
409
410 struct adf4377_state {
411 const struct adf4377_chip_info *chip_info;
412 struct spi_device *spi;
413 struct regmap *regmap;
414 struct clk *clkin;
415 /* Protect against concurrent accesses to the device and data content */
416 struct mutex lock;
417 struct notifier_block nb;
418 /* Reference Divider */
419 unsigned int ref_div_factor;
420 /* PFD Frequency */
421 unsigned int f_pfd;
422 /* Input Reference Clock */
423 unsigned int clkin_freq;
424 /* CLKOUT Divider */
425 u8 clkout_div_sel;
426 /* Feedback Divider (N) */
427 u16 n_int;
428 u16 synth_lock_timeout;
429 u16 vco_alc_timeout;
430 u16 adc_clk_div;
431 u16 vco_band_div;
432 u8 dclk_div1;
433 u8 dclk_div2;
434 u8 dclk_mode;
435 unsigned int f_div_rclk;
436 enum muxout_select_mode muxout_select;
437 struct gpio_desc *gpio_ce;
438 struct gpio_desc *gpio_enclk1;
439 struct gpio_desc *gpio_enclk2;
440 struct clk *clk;
441 struct clk *clkout;
442 struct clk_hw hw;
443 u8 buf[2] __aligned(IIO_DMA_MINALIGN);
444 };
445
446 #define to_adf4377_state(h) container_of(h, struct adf4377_state, hw)
447
448 static const char * const adf4377_muxout_modes[] = {
449 [ADF4377_MUXOUT_HIGH_Z] = "high_z",
450 [ADF4377_MUXOUT_LKDET] = "lock_detect",
451 [ADF4377_MUXOUT_LOW] = "muxout_low",
452 [ADF4377_MUXOUT_DIV_RCLK_2] = "f_div_rclk_2",
453 [ADF4377_MUXOUT_DIV_NCLK_2] = "f_div_nclk_2",
454 [ADF4377_MUXOUT_HIGH] = "muxout_high",
455 };
456
457 static const struct reg_sequence adf4377_reg_defaults[] = {
458 { 0x42, ADF4377_0042_R042_RSV1 },
459 { 0x3B, ADF4377_003B_R03B_RSV1 },
460 { 0x3A, ADF4377_003A_R03A_RSV1 },
461 { 0x34, ADF4377_0034_R034_RSV1 },
462 { 0x33, ADF4377_0033_R033_RSV1 },
463 { 0x32, ADF4377_0032_R032_RSV1 },
464 { 0x31, ADF4377_0031_R031_RSV1 },
465 { 0x2C, ADF4377_002C_R02C_RSV1 },
466 { 0x25, ADF4377_0025_R025_RSV1 },
467 { 0x23, ADF4377_0023_R023_RSV1 },
468 { 0x22, ADF4377_0022_R022_RSV1 },
469 { 0x21, ADF4377_0021_R021_RSV1 },
470 { 0x1f, ADF4377_001F_R01F_RSV1 },
471 { 0x1c, ADF4377_001C_R01C_RSV1 },
472 };
473
474 static const struct regmap_config adf4377_regmap_config = {
475 .reg_bits = 16,
476 .val_bits = 8,
477 .read_flag_mask = BIT(7),
478 .max_register = 0x54,
479 };
480
adf4377_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int write_val,unsigned int * read_val)481 static int adf4377_reg_access(struct iio_dev *indio_dev,
482 unsigned int reg,
483 unsigned int write_val,
484 unsigned int *read_val)
485 {
486 struct adf4377_state *st = iio_priv(indio_dev);
487
488 if (read_val)
489 return regmap_read(st->regmap, reg, read_val);
490
491 return regmap_write(st->regmap, reg, write_val);
492 }
493
494 static const struct iio_info adf4377_info = {
495 .debugfs_reg_access = &adf4377_reg_access,
496 };
497
adf4377_soft_reset(struct adf4377_state * st)498 static int adf4377_soft_reset(struct adf4377_state *st)
499 {
500 unsigned int read_val;
501 int ret;
502
503 ret = regmap_update_bits(st->regmap, 0x0, ADF4377_0000_SOFT_RESET_MSK |
504 ADF4377_0000_SOFT_RESET_R_MSK,
505 FIELD_PREP(ADF4377_0000_SOFT_RESET_MSK, 1) |
506 FIELD_PREP(ADF4377_0000_SOFT_RESET_R_MSK, 1));
507 if (ret)
508 return ret;
509
510 return regmap_read_poll_timeout(st->regmap, 0x0, read_val,
511 !(read_val & (ADF4377_0000_SOFT_RESET_MSK |
512 ADF4377_0000_SOFT_RESET_R_MSK)), 200, 200 * 100);
513 }
514
adf4377_get_freq(struct adf4377_state * st,u64 * freq)515 static int adf4377_get_freq(struct adf4377_state *st, u64 *freq)
516 {
517 unsigned int ref_div_factor, n_int;
518 u64 clkin_freq;
519 int ret;
520
521 mutex_lock(&st->lock);
522 ret = regmap_read(st->regmap, 0x12, &ref_div_factor);
523 if (ret)
524 goto exit;
525
526 ret = regmap_bulk_read(st->regmap, 0x10, st->buf, sizeof(st->buf));
527 if (ret)
528 goto exit;
529
530 clkin_freq = clk_get_rate(st->clkin);
531 ref_div_factor = FIELD_GET(ADF4377_0012_R_DIV_MSK, ref_div_factor);
532 n_int = FIELD_GET(ADF4377_0010_N_INT_LSB_MSK | ADF4377_0011_N_INT_MSB_MSK,
533 get_unaligned_le16(&st->buf));
534
535 *freq = div_u64(clkin_freq, ref_div_factor) * n_int;
536 exit:
537 mutex_unlock(&st->lock);
538
539 return ret;
540 }
541
adf4377_set_freq(struct adf4377_state * st,u64 freq)542 static int adf4377_set_freq(struct adf4377_state *st, u64 freq)
543 {
544 unsigned int read_val;
545 u64 f_vco;
546 int ret;
547
548 mutex_lock(&st->lock);
549
550 if (freq > ADF4377_MAX_CLKPN_FREQ || freq < ADF4377_MIN_CLKPN_FREQ) {
551 ret = -EINVAL;
552 goto exit;
553 }
554
555 ret = regmap_update_bits(st->regmap, 0x1C, ADF4377_001C_EN_DNCLK_MSK |
556 ADF4377_001C_EN_DRCLK_MSK,
557 FIELD_PREP(ADF4377_001C_EN_DNCLK_MSK, 1) |
558 FIELD_PREP(ADF4377_001C_EN_DRCLK_MSK, 1));
559 if (ret)
560 goto exit;
561
562 ret = regmap_update_bits(st->regmap, 0x11, ADF4377_0011_EN_AUTOCAL_MSK |
563 ADF4377_0011_DCLK_DIV2_MSK,
564 FIELD_PREP(ADF4377_0011_EN_AUTOCAL_MSK, 1) |
565 FIELD_PREP(ADF4377_0011_DCLK_DIV2_MSK, st->dclk_div2));
566 if (ret)
567 goto exit;
568
569 ret = regmap_update_bits(st->regmap, 0x2E, ADF4377_002E_EN_ADC_CNV_MSK |
570 ADF4377_002E_EN_ADC_MSK |
571 ADF4377_002E_ADC_A_CONV_MSK,
572 FIELD_PREP(ADF4377_002E_EN_ADC_CNV_MSK, 1) |
573 FIELD_PREP(ADF4377_002E_EN_ADC_MSK, 1) |
574 FIELD_PREP(ADF4377_002E_ADC_A_CONV_MSK,
575 ADF4377_002E_ADC_A_CONV_VCO_CALIB));
576 if (ret)
577 goto exit;
578
579 ret = regmap_update_bits(st->regmap, 0x20, ADF4377_0020_EN_ADC_CLK_MSK,
580 FIELD_PREP(ADF4377_0020_EN_ADC_CLK_MSK, 1));
581 if (ret)
582 goto exit;
583
584 ret = regmap_update_bits(st->regmap, 0x2F, ADF4377_002F_DCLK_DIV1_MSK,
585 FIELD_PREP(ADF4377_002F_DCLK_DIV1_MSK, st->dclk_div1));
586 if (ret)
587 goto exit;
588
589 ret = regmap_update_bits(st->regmap, 0x24, ADF4377_0024_DCLK_MODE_MSK,
590 FIELD_PREP(ADF4377_0024_DCLK_MODE_MSK, st->dclk_mode));
591 if (ret)
592 goto exit;
593
594 ret = regmap_write(st->regmap, 0x27,
595 FIELD_PREP(ADF4377_0027_SYNTH_LOCK_TO_LSB_MSK,
596 st->synth_lock_timeout));
597 if (ret)
598 goto exit;
599
600 ret = regmap_update_bits(st->regmap, 0x28, ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK,
601 FIELD_PREP(ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK,
602 st->synth_lock_timeout >> 8));
603 if (ret)
604 goto exit;
605
606 ret = regmap_write(st->regmap, 0x29,
607 FIELD_PREP(ADF4377_0029_VCO_ALC_TO_LSB_MSK,
608 st->vco_alc_timeout));
609 if (ret)
610 goto exit;
611
612 ret = regmap_update_bits(st->regmap, 0x2A, ADF4377_002A_VCO_ALC_TO_MSB_MSK,
613 FIELD_PREP(ADF4377_002A_VCO_ALC_TO_MSB_MSK,
614 st->vco_alc_timeout >> 8));
615 if (ret)
616 goto exit;
617
618 ret = regmap_write(st->regmap, 0x26,
619 FIELD_PREP(ADF4377_0026_VCO_BAND_DIV_MSK, st->vco_band_div));
620 if (ret)
621 goto exit;
622
623 ret = regmap_write(st->regmap, 0x2D,
624 FIELD_PREP(ADF4377_002D_ADC_CLK_DIV_MSK, st->adc_clk_div));
625 if (ret)
626 goto exit;
627
628 st->clkout_div_sel = 0;
629
630 f_vco = freq;
631
632 while (f_vco < ADF4377_MIN_VCO_FREQ) {
633 f_vco <<= 1;
634 st->clkout_div_sel++;
635 }
636
637 st->n_int = div_u64(freq, st->f_pfd);
638
639 ret = regmap_update_bits(st->regmap, 0x11, ADF4377_0011_EN_RDBLR_MSK |
640 ADF4377_0011_N_INT_MSB_MSK,
641 FIELD_PREP(ADF4377_0011_EN_RDBLR_MSK, 0) |
642 FIELD_PREP(ADF4377_0011_N_INT_MSB_MSK, st->n_int >> 8));
643 if (ret)
644 goto exit;
645
646 ret = regmap_update_bits(st->regmap, 0x12, ADF4377_0012_R_DIV_MSK |
647 ADF4377_0012_CLKOUT_DIV_MSK,
648 FIELD_PREP(ADF4377_0012_CLKOUT_DIV_MSK, st->clkout_div_sel) |
649 FIELD_PREP(ADF4377_0012_R_DIV_MSK, st->ref_div_factor));
650 if (ret)
651 goto exit;
652
653 ret = regmap_write(st->regmap, 0x10,
654 FIELD_PREP(ADF4377_0010_N_INT_LSB_MSK, st->n_int));
655 if (ret)
656 goto exit;
657
658 ret = regmap_read_poll_timeout(st->regmap, 0x49, read_val,
659 !(read_val & (ADF4377_0049_FSM_BUSY_MSK)), 200, 200 * 100);
660 if (ret)
661 goto exit;
662
663 /* Disable EN_DNCLK, EN_DRCLK */
664 ret = regmap_update_bits(st->regmap, 0x1C, ADF4377_001C_EN_DNCLK_MSK |
665 ADF4377_001C_EN_DRCLK_MSK,
666 FIELD_PREP(ADF4377_001C_EN_DNCLK_MSK, 0) |
667 FIELD_PREP(ADF4377_001C_EN_DRCLK_MSK, 0));
668 if (ret)
669 goto exit;
670
671 /* Disable EN_ADC_CLK */
672 ret = regmap_update_bits(st->regmap, 0x20, ADF4377_0020_EN_ADC_CLK_MSK,
673 FIELD_PREP(ADF4377_0020_EN_ADC_CLK_MSK, 0));
674 if (ret)
675 goto exit;
676
677 /* Set output Amplitude */
678 ret = regmap_update_bits(st->regmap, 0x19, ADF4377_0019_CLKOUT2_OP_MSK |
679 ADF4377_0019_CLKOUT1_OP_MSK,
680 FIELD_PREP(ADF4377_0019_CLKOUT1_OP_MSK,
681 ADF4377_0019_CLKOUT_420MV) |
682 FIELD_PREP(ADF4377_0019_CLKOUT2_OP_MSK,
683 ADF4377_0019_CLKOUT_420MV));
684
685 exit:
686 mutex_unlock(&st->lock);
687
688 return ret;
689 }
690
adf4377_gpio_init(struct adf4377_state * st)691 static void adf4377_gpio_init(struct adf4377_state *st)
692 {
693 if (st->gpio_ce) {
694 gpiod_set_value(st->gpio_ce, 1);
695
696 /* Delay for SPI register bits to settle to their power-on reset state */
697 fsleep(200);
698 }
699
700 if (st->gpio_enclk1)
701 gpiod_set_value(st->gpio_enclk1, 1);
702
703 if (st->gpio_enclk2)
704 gpiod_set_value(st->gpio_enclk2, 1);
705 }
706
adf4377_init(struct adf4377_state * st)707 static int adf4377_init(struct adf4377_state *st)
708 {
709 struct device *dev = &st->spi->dev;
710 int ret;
711
712 adf4377_gpio_init(st);
713
714 ret = adf4377_soft_reset(st);
715 if (ret)
716 return dev_err_probe(dev, ret, "Failed to soft reset.\n");
717
718 ret = regmap_multi_reg_write(st->regmap, adf4377_reg_defaults,
719 ARRAY_SIZE(adf4377_reg_defaults));
720 if (ret)
721 return dev_err_probe(dev, ret,
722 "Failed to set default registers.\n");
723
724 ret = regmap_update_bits(st->regmap, 0x00,
725 ADF4377_0000_SDO_ACTIVE_MSK | ADF4377_0000_SDO_ACTIVE_R_MSK,
726 FIELD_PREP(ADF4377_0000_SDO_ACTIVE_MSK,
727 ADF4377_0000_SDO_ACTIVE_SPI_4W) |
728 FIELD_PREP(ADF4377_0000_SDO_ACTIVE_R_MSK,
729 ADF4377_0000_SDO_ACTIVE_SPI_4W));
730 if (ret)
731 return dev_err_probe(dev, ret,
732 "Failed to set 4-Wire Operation.\n");
733
734 st->clkin_freq = clk_get_rate(st->clkin);
735
736 /* Power Up */
737 ret = regmap_write(st->regmap, 0x1a,
738 FIELD_PREP(ADF4377_001A_PD_ALL_MSK, 0) |
739 FIELD_PREP(ADF4377_001A_PD_RDIV_MSK, 0) |
740 FIELD_PREP(ADF4377_001A_PD_NDIV_MSK, 0) |
741 FIELD_PREP(ADF4377_001A_PD_VCO_MSK, 0) |
742 FIELD_PREP(ADF4377_001A_PD_LD_MSK, 0) |
743 FIELD_PREP(ADF4377_001A_PD_PFDCP_MSK, 0) |
744 FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 0) |
745 FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 0));
746 if (ret)
747 return dev_err_probe(dev, ret,
748 "Failed to set power down registers.\n");
749
750 /* Set Mux Output */
751 ret = regmap_update_bits(st->regmap, 0x1D,
752 ADF4377_001D_MUXOUT_MSK,
753 FIELD_PREP(ADF4377_001D_MUXOUT_MSK, st->muxout_select));
754 if (ret)
755 return ret;
756
757 /* Compute PFD */
758 st->ref_div_factor = 0;
759 do {
760 st->ref_div_factor++;
761 st->f_pfd = st->clkin_freq / st->ref_div_factor;
762 } while (st->f_pfd > ADF4377_MAX_FREQ_PFD);
763
764 if (st->f_pfd > ADF4377_MAX_FREQ_PFD || st->f_pfd < ADF4377_MIN_FREQ_PFD)
765 return -EINVAL;
766
767 st->f_div_rclk = st->f_pfd;
768
769 if (st->f_pfd <= ADF4377_FREQ_PFD_80MHZ) {
770 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_1;
771 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1;
772 st->dclk_mode = 0;
773 } else if (st->f_pfd <= ADF4377_FREQ_PFD_125MHZ) {
774 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_1;
775 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1;
776 st->dclk_mode = 1;
777 } else if (st->f_pfd <= ADF4377_FREQ_PFD_160MHZ) {
778 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2;
779 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1;
780 st->dclk_mode = 0;
781 st->f_div_rclk /= 2;
782 } else if (st->f_pfd <= ADF4377_FREQ_PFD_250MHZ) {
783 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2;
784 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1;
785 st->dclk_mode = 1;
786 st->f_div_rclk /= 2;
787 } else if (st->f_pfd <= ADF4377_FREQ_PFD_320MHZ) {
788 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2;
789 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_2;
790 st->dclk_mode = 0;
791 st->f_div_rclk /= 4;
792 } else {
793 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2;
794 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_2;
795 st->dclk_mode = 1;
796 st->f_div_rclk /= 4;
797 }
798
799 st->synth_lock_timeout = DIV_ROUND_UP(st->f_div_rclk, 50000);
800 st->vco_alc_timeout = DIV_ROUND_UP(st->f_div_rclk, 20000);
801 st->vco_band_div = DIV_ROUND_UP(st->f_div_rclk, 150000 * 16 * (1 << st->dclk_mode));
802 st->adc_clk_div = DIV_ROUND_UP((st->f_div_rclk / 400000 - 2), 4);
803
804 return 0;
805 }
806
adf4377_read(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)807 static ssize_t adf4377_read(struct iio_dev *indio_dev, uintptr_t private,
808 const struct iio_chan_spec *chan, char *buf)
809 {
810 struct adf4377_state *st = iio_priv(indio_dev);
811 u64 val = 0;
812 int ret;
813
814 switch ((u32)private) {
815 case ADF4377_FREQ:
816 ret = adf4377_get_freq(st, &val);
817 if (ret)
818 return ret;
819
820 return sysfs_emit(buf, "%llu\n", val);
821 default:
822 return -EINVAL;
823 }
824 }
825
adf4377_write(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)826 static ssize_t adf4377_write(struct iio_dev *indio_dev, uintptr_t private,
827 const struct iio_chan_spec *chan, const char *buf,
828 size_t len)
829 {
830 struct adf4377_state *st = iio_priv(indio_dev);
831 unsigned long long freq;
832 int ret;
833
834 switch ((u32)private) {
835 case ADF4377_FREQ:
836 ret = kstrtoull(buf, 10, &freq);
837 if (ret)
838 return ret;
839
840 ret = adf4377_set_freq(st, freq);
841 if (ret)
842 return ret;
843
844 return len;
845 default:
846 return -EINVAL;
847 }
848 }
849
850 #define _ADF4377_EXT_INFO(_name, _shared, _ident) { \
851 .name = _name, \
852 .read = adf4377_read, \
853 .write = adf4377_write, \
854 .private = _ident, \
855 .shared = _shared, \
856 }
857
858 static const struct iio_chan_spec_ext_info adf4377_ext_info[] = {
859 /*
860 * Usually we use IIO_CHAN_INFO_FREQUENCY, but there are
861 * values > 2^32 in order to support the entire frequency range
862 * in Hz.
863 */
864 _ADF4377_EXT_INFO("frequency", IIO_SEPARATE, ADF4377_FREQ),
865 { }
866 };
867
868 static const struct iio_chan_spec adf4377_channels[] = {
869 {
870 .type = IIO_ALTVOLTAGE,
871 .indexed = 1,
872 .output = 1,
873 .channel = 0,
874 .ext_info = adf4377_ext_info,
875 },
876 };
877
adf4377_properties_parse(struct adf4377_state * st)878 static int adf4377_properties_parse(struct adf4377_state *st)
879 {
880 struct device *dev = &st->spi->dev;
881 int ret;
882
883 st->clkin = devm_clk_get_enabled(dev, "ref_in");
884 if (IS_ERR(st->clkin))
885 return dev_err_probe(dev, PTR_ERR(st->clkin),
886 "failed to get the reference input clock\n");
887
888 st->gpio_ce = devm_gpiod_get_optional(dev, "chip-enable",
889 GPIOD_OUT_LOW);
890 if (IS_ERR(st->gpio_ce))
891 return dev_err_probe(dev, PTR_ERR(st->gpio_ce),
892 "failed to get the CE GPIO\n");
893
894 st->gpio_enclk1 = devm_gpiod_get_optional(dev, "clk1-enable",
895 GPIOD_OUT_LOW);
896 if (IS_ERR(st->gpio_enclk1))
897 return dev_err_probe(dev, PTR_ERR(st->gpio_enclk1),
898 "failed to get the CE GPIO\n");
899
900 if (st->chip_info->has_gpio_enclk2) {
901 st->gpio_enclk2 = devm_gpiod_get_optional(dev, "clk2-enable",
902 GPIOD_OUT_LOW);
903 if (IS_ERR(st->gpio_enclk2))
904 return dev_err_probe(dev, PTR_ERR(st->gpio_enclk2),
905 "failed to get the CE GPIO\n");
906 }
907
908 ret = device_property_match_property_string(dev, "adi,muxout-select",
909 adf4377_muxout_modes,
910 ARRAY_SIZE(adf4377_muxout_modes));
911 if (ret >= 0)
912 st->muxout_select = ret;
913 else
914 st->muxout_select = ADF4377_MUXOUT_HIGH_Z;
915
916 return 0;
917 }
918
adf4377_freq_change(struct notifier_block * nb,unsigned long action,void * data)919 static int adf4377_freq_change(struct notifier_block *nb, unsigned long action, void *data)
920 {
921 struct adf4377_state *st = container_of(nb, struct adf4377_state, nb);
922 int ret;
923
924 if (action == POST_RATE_CHANGE) {
925 mutex_lock(&st->lock);
926 ret = notifier_from_errno(adf4377_init(st));
927 mutex_unlock(&st->lock);
928 return ret;
929 }
930
931 return NOTIFY_OK;
932 }
933
adf4377_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)934 static unsigned long adf4377_clk_recalc_rate(struct clk_hw *hw,
935 unsigned long parent_rate)
936 {
937 struct adf4377_state *st = to_adf4377_state(hw);
938 u64 freq;
939 int ret;
940
941 ret = adf4377_get_freq(st, &freq);
942 if (ret)
943 return 0;
944
945 return freq;
946 }
947
adf4377_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)948 static int adf4377_clk_set_rate(struct clk_hw *hw,
949 unsigned long rate,
950 unsigned long parent_rate)
951 {
952 struct adf4377_state *st = to_adf4377_state(hw);
953
954 return adf4377_set_freq(st, rate);
955 }
956
adf4377_clk_prepare(struct clk_hw * hw)957 static int adf4377_clk_prepare(struct clk_hw *hw)
958 {
959 struct adf4377_state *st = to_adf4377_state(hw);
960
961 return regmap_update_bits(st->regmap, 0x1a, ADF4377_001A_PD_CLKOUT1_MSK |
962 ADF4377_001A_PD_CLKOUT2_MSK,
963 FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 0) |
964 FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 0));
965 }
966
adf4377_clk_unprepare(struct clk_hw * hw)967 static void adf4377_clk_unprepare(struct clk_hw *hw)
968 {
969 struct adf4377_state *st = to_adf4377_state(hw);
970
971 regmap_update_bits(st->regmap, 0x1a, ADF4377_001A_PD_CLKOUT1_MSK |
972 ADF4377_001A_PD_CLKOUT2_MSK,
973 FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 1) |
974 FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 1));
975 }
976
adf4377_clk_is_prepared(struct clk_hw * hw)977 static int adf4377_clk_is_prepared(struct clk_hw *hw)
978 {
979 struct adf4377_state *st = to_adf4377_state(hw);
980 unsigned int readval;
981 int ret;
982
983 ret = regmap_read(st->regmap, 0x1a, &readval);
984 if (ret)
985 return ret;
986
987 return !(readval & (ADF4377_001A_PD_CLKOUT1_MSK | ADF4377_001A_PD_CLKOUT2_MSK));
988 }
989
990 static const struct clk_ops adf4377_clk_ops = {
991 .recalc_rate = adf4377_clk_recalc_rate,
992 .set_rate = adf4377_clk_set_rate,
993 .prepare = adf4377_clk_prepare,
994 .unprepare = adf4377_clk_unprepare,
995 .is_prepared = adf4377_clk_is_prepared,
996 };
997
adf4377_clk_register(struct adf4377_state * st)998 static int adf4377_clk_register(struct adf4377_state *st)
999 {
1000 struct spi_device *spi = st->spi;
1001 struct device *dev = &spi->dev;
1002 struct clk_init_data init;
1003 struct clk_parent_data parent_data;
1004 int ret;
1005
1006 if (!device_property_present(dev, "#clock-cells"))
1007 return 0;
1008
1009 ret = device_property_read_string(dev, "clock-output-names", &init.name);
1010 if (ret) {
1011 init.name = devm_kasprintf(dev, GFP_KERNEL, "%pfw-clk",
1012 dev_fwnode(dev));
1013 if (!init.name)
1014 return -ENOMEM;
1015 }
1016
1017 parent_data.fw_name = "ref_in";
1018
1019 init.ops = &adf4377_clk_ops;
1020 init.parent_data = &parent_data;
1021 init.num_parents = 1;
1022 init.flags = CLK_SET_RATE_PARENT;
1023
1024 st->hw.init = &init;
1025 ret = devm_clk_hw_register(dev, &st->hw);
1026 if (ret)
1027 return ret;
1028
1029 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &st->hw);
1030 if (ret)
1031 return ret;
1032
1033 st->clkout = st->hw.clk;
1034
1035 return 0;
1036 }
1037
1038 static const struct adf4377_chip_info adf4377_chip_info = {
1039 .name = "adf4377",
1040 .has_gpio_enclk2 = true,
1041 };
1042
1043 static const struct adf4377_chip_info adf4378_chip_info = {
1044 .name = "adf4378",
1045 .has_gpio_enclk2 = false,
1046 };
1047
adf4377_probe(struct spi_device * spi)1048 static int adf4377_probe(struct spi_device *spi)
1049 {
1050 struct iio_dev *indio_dev;
1051 struct regmap *regmap;
1052 struct adf4377_state *st;
1053 struct device *dev = &spi->dev;
1054 int ret;
1055
1056 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1057 if (!indio_dev)
1058 return -ENOMEM;
1059
1060 regmap = devm_regmap_init_spi(spi, &adf4377_regmap_config);
1061 if (IS_ERR(regmap))
1062 return PTR_ERR(regmap);
1063
1064 st = iio_priv(indio_dev);
1065
1066 indio_dev->info = &adf4377_info;
1067 indio_dev->name = "adf4377";
1068
1069 st->regmap = regmap;
1070 st->spi = spi;
1071 st->chip_info = spi_get_device_match_data(spi);
1072 mutex_init(&st->lock);
1073
1074 ret = adf4377_properties_parse(st);
1075 if (ret)
1076 return ret;
1077
1078 st->nb.notifier_call = adf4377_freq_change;
1079 ret = devm_clk_notifier_register(dev, st->clkin, &st->nb);
1080 if (ret)
1081 return ret;
1082
1083 ret = adf4377_init(st);
1084 if (ret)
1085 return ret;
1086
1087 ret = adf4377_clk_register(st);
1088 if (ret)
1089 return ret;
1090
1091 if (!st->clkout) {
1092 indio_dev->channels = adf4377_channels;
1093 indio_dev->num_channels = ARRAY_SIZE(adf4377_channels);
1094 }
1095
1096 return devm_iio_device_register(dev, indio_dev);
1097 }
1098
1099 static const struct spi_device_id adf4377_id[] = {
1100 { "adf4377", (kernel_ulong_t)&adf4377_chip_info },
1101 { "adf4378", (kernel_ulong_t)&adf4378_chip_info },
1102 { }
1103 };
1104 MODULE_DEVICE_TABLE(spi, adf4377_id);
1105
1106 static const struct of_device_id adf4377_of_match[] = {
1107 { .compatible = "adi,adf4377", .data = &adf4377_chip_info },
1108 { .compatible = "adi,adf4378", .data = &adf4378_chip_info },
1109 { }
1110 };
1111 MODULE_DEVICE_TABLE(of, adf4377_of_match);
1112
1113 static struct spi_driver adf4377_driver = {
1114 .driver = {
1115 .name = "adf4377",
1116 .of_match_table = adf4377_of_match,
1117 },
1118 .probe = adf4377_probe,
1119 .id_table = adf4377_id,
1120 };
1121 module_spi_driver(adf4377_driver);
1122
1123 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>");
1124 MODULE_DESCRIPTION("Analog Devices ADF4377");
1125 MODULE_LICENSE("GPL");
1126