1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 #define CREATE_TRACE_POINTS 5 #include <trace/events/qcom_geni_i2c.h> 6 7 #include <linux/acpi.h> 8 #include <linux/clk.h> 9 #include <linux/dmaengine.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/dma/qcom-gpi-dma.h> 12 #include <linux/err.h> 13 #include <linux/i2c.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/soc/qcom/geni-se.h> 21 #include <linux/spinlock.h> 22 #include <linux/units.h> 23 24 #define SE_I2C_TX_TRANS_LEN 0x26c 25 #define SE_I2C_RX_TRANS_LEN 0x270 26 #define SE_I2C_SCL_COUNTERS 0x278 27 28 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\ 29 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN) 30 #define SE_I2C_ABORT BIT(1) 31 32 /* M_CMD OP codes for I2C */ 33 #define I2C_WRITE 0x1 34 #define I2C_READ 0x2 35 #define I2C_WRITE_READ 0x3 36 #define I2C_ADDR_ONLY 0x4 37 #define I2C_BUS_CLEAR 0x6 38 #define I2C_STOP_ON_BUS 0x7 39 /* M_CMD params for I2C */ 40 #define PRE_CMD_DELAY BIT(0) 41 #define TIMESTAMP_BEFORE BIT(1) 42 #define STOP_STRETCH BIT(2) 43 #define TIMESTAMP_AFTER BIT(3) 44 #define POST_COMMAND_DELAY BIT(4) 45 #define IGNORE_ADD_NACK BIT(6) 46 #define READ_FINISHED_WITH_ACK BIT(7) 47 #define BYPASS_ADDR_PHASE BIT(8) 48 #define SLV_ADDR_MSK GENMASK(15, 9) 49 #define SLV_ADDR_SHFT 9 50 /* I2C SCL COUNTER fields */ 51 #define HIGH_COUNTER_MSK GENMASK(29, 20) 52 #define HIGH_COUNTER_SHFT 20 53 #define LOW_COUNTER_MSK GENMASK(19, 10) 54 #define LOW_COUNTER_SHFT 10 55 #define CYCLE_COUNTER_MSK GENMASK(9, 0) 56 57 #define I2C_PACK_TX BIT(0) 58 #define I2C_PACK_RX BIT(1) 59 60 enum geni_i2c_err_code { 61 GP_IRQ0, 62 ADDR_NACK, 63 DATA_NACK, 64 GP_IRQ2, 65 BUS_PROTO, 66 ARB_LOST, 67 GP_IRQ5, 68 GENI_OVERRUN, 69 GENI_ILLEGAL_CMD, 70 GENI_ABORT_DONE, 71 GENI_TIMEOUT, 72 }; 73 74 #define DM_I2C_CB_ERR ((BIT(ADDR_NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \ 75 << 5) 76 77 #define I2C_AUTO_SUSPEND_DELAY 250 78 #define PACKING_BYTES_PW 4 79 80 #define ABORT_TIMEOUT HZ 81 #define CANCEL_TIMEOUT HZ 82 #define RST_TIMEOUT HZ 83 84 /* 9 bits per byte (8 data + 1 ACK), 10x safety margin */ 85 #define I2C_TIMEOUT_SAFETY_COEFFICIENT 10 86 87 /* 300ms floor: budget for clock stretching; slave may hold SCL low indefinitely */ 88 #define I2C_TIMEOUT_MIN_USEC 300000 89 90 #define GENI_SE_CLK_32MHZ (32 * HZ_PER_MHZ) 91 #define GENI_SE_CLK_19P2MHZ 19200000UL 92 93 struct geni_i2c_desc { 94 bool no_dma_support; 95 unsigned int tx_fifo_depth; 96 int (*resources_init)(struct geni_se *se); 97 int (*set_rate)(struct geni_se *se, unsigned long freq); 98 int (*power_on)(struct geni_se *se); 99 int (*power_off)(struct geni_se *se); 100 }; 101 102 #define QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC 2 103 104 /** 105 * struct geni_i2c_gpi_multi_desc_xfer - Structure for multi transfer support 106 * 107 * @msg_idx_cnt: Current message index being processed in the transfer 108 * @unmap_msg_cnt: Number of messages that have been unmapped 109 * @irq_cnt: Number of transfer completion interrupts received 110 * @dma_buf: Array of virtual addresses for DMA-safe buffers 111 * @dma_addr: Array of DMA addresses corresponding to the buffers 112 */ 113 struct geni_i2c_gpi_multi_desc_xfer { 114 u32 msg_idx_cnt; 115 u32 unmap_msg_cnt; 116 u32 irq_cnt; 117 void **dma_buf; 118 dma_addr_t *dma_addr; 119 }; 120 121 struct geni_i2c_dev { 122 struct geni_se se; 123 u32 tx_wm; 124 int irq; 125 int err; 126 struct i2c_adapter adap; 127 struct completion done; 128 struct completion abort_done; 129 struct completion cancel_done; 130 struct completion tx_reset_done; 131 struct completion rx_reset_done; 132 struct i2c_msg *cur; 133 int cur_wr; 134 int cur_rd; 135 spinlock_t lock; 136 u32 clk_freq_out; 137 const struct geni_i2c_clk_fld *clk_fld; 138 u32 clk_idx; 139 void *dma_buf; 140 size_t xfer_len; 141 dma_addr_t dma_addr; 142 struct dma_chan *tx_c; 143 struct dma_chan *rx_c; 144 bool no_dma; 145 bool gpi_mode; 146 bool is_tx_multi_desc_xfer; 147 u32 num_msgs; 148 struct geni_i2c_gpi_multi_desc_xfer i2c_multi_desc_config; 149 const struct geni_i2c_desc *dev_data; 150 }; 151 152 struct geni_i2c_err_log { 153 int err; 154 const char *msg; 155 }; 156 157 static const struct geni_i2c_err_log gi2c_log[] = { 158 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"}, 159 [ADDR_NACK] = {-ENXIO, "NACK: target device unresponsive, check its power/reset-ln"}, 160 [DATA_NACK] = {-EIO, "Data NACK: TX transfer NACK"}, 161 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"}, 162 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"}, 163 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"}, 164 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"}, 165 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"}, 166 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"}, 167 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"}, 168 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"}, 169 }; 170 171 struct geni_i2c_clk_fld { 172 u32 clk_freq_out; 173 u8 clk_div; 174 u8 t_high_cnt; 175 u8 t_low_cnt; 176 u8 t_cycle_cnt; 177 }; 178 179 /* 180 * Hardware uses the underlying formula to calculate time periods of 181 * SCL clock cycle. Firmware uses some additional cycles excluded from the 182 * below formula and it is confirmed that the time periods are within 183 * specification limits. 184 * 185 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock 186 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock 187 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock 188 * clk_freq_out = t / t_cycle 189 * source_clock = 19.2 MHz 190 */ 191 static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = { 192 { I2C_MAX_STANDARD_MODE_FREQ, 7, 10, 12, 26 }, 193 { I2C_MAX_FAST_MODE_FREQ, 2, 5, 11, 22 }, 194 { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 2, 8, 18 }, 195 {} 196 }; 197 198 /* source_clock = 32 MHz */ 199 static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { 200 { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 }, 201 { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 }, 202 { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 }, 203 {} 204 }; 205 206 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) 207 { 208 const struct geni_i2c_clk_fld *itr; 209 unsigned long req_freq, res_freq; 210 int ret; 211 212 /* 213 * Use 32 MHz only if already selected, otherwise use 19.2 MHz. 214 * Preferring 32 MHz merely because DFS supports it breaks I2C 215 * transfers on X1E80100 CRD. 216 */ 217 if (clk_get_rate(gi2c->se.clk) == GENI_SE_CLK_32MHZ) { 218 req_freq = GENI_SE_CLK_32MHZ; 219 itr = geni_i2c_clk_map_32mhz; 220 } else { 221 req_freq = GENI_SE_CLK_19P2MHZ; 222 itr = geni_i2c_clk_map_19p2mhz; 223 } 224 225 ret = geni_se_clk_freq_match(&gi2c->se, req_freq, &gi2c->clk_idx, 226 &res_freq, true); 227 if (ret) 228 return dev_err_probe(gi2c->se.dev, ret, 229 "Failed to find SE source clock %lu Hz\n", 230 req_freq); 231 if (res_freq != req_freq) { 232 dev_err(gi2c->se.dev, "Unsupported SE source clock %lu Hz\n", 233 res_freq); 234 return -EINVAL; 235 } 236 237 while (itr->clk_freq_out != 0) { 238 if (itr->clk_freq_out == gi2c->clk_freq_out) { 239 gi2c->clk_fld = itr; 240 dev_dbg(gi2c->se.dev, 241 "I2C clk selected: freq: %u Hz, clk_idx: %u\n", 242 gi2c->clk_freq_out, gi2c->clk_idx); 243 return 0; 244 } 245 itr++; 246 } 247 248 dev_err(gi2c->se.dev, "Unsupported I2C output frequency %u Hz\n", gi2c->clk_freq_out); 249 250 return -EINVAL; 251 } 252 253 static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) 254 { 255 struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev); 256 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 257 u32 val; 258 259 writel_relaxed(gi2c->clk_idx, gi2c->se.base + SE_GENI_CLK_SEL); 260 261 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; 262 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); 263 264 val = itr->t_high_cnt << HIGH_COUNTER_SHFT; 265 val |= itr->t_low_cnt << LOW_COUNTER_SHFT; 266 val |= itr->t_cycle_cnt; 267 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); 268 trace_geni_i2c_bus_setup(gi2c->se.dev, gi2c->clk_freq_out, 269 itr->clk_div, itr->t_high_cnt, 270 itr->t_low_cnt, itr->t_cycle_cnt); 271 return 0; 272 } 273 274 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) 275 { 276 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); 277 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 278 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); 279 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); 280 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); 281 u32 rx_st, tx_st; 282 283 if (dma) { 284 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 285 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 286 } else { 287 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS); 288 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS); 289 } 290 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n", 291 dma, tx_st, rx_st, m_stat); 292 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n", 293 m_cmd, geni_s, geni_ios); 294 } 295 296 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err) 297 { 298 if (!gi2c->err) 299 gi2c->err = gi2c_log[err].err; 300 if (gi2c->cur) 301 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n", 302 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags); 303 304 trace_geni_i2c_err(gi2c->se.dev, gi2c_log[err].err, gi2c_log[err].msg); 305 306 switch (err) { 307 case GENI_ABORT_DONE: 308 case ADDR_NACK: 309 case DATA_NACK: 310 case GENI_TIMEOUT: 311 dev_dbg(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 312 break; 313 default: 314 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 315 geni_i2c_err_misc(gi2c); 316 break; 317 } 318 } 319 320 static void geni_i2c_check_addr_data_nack(struct geni_i2c_dev *gi2c) 321 { 322 if (!readl_relaxed(gi2c->se.base + SE_GENI_M_GP_LENGTH)) 323 geni_i2c_err(gi2c, ADDR_NACK); 324 else if (!(gi2c->cur->flags & I2C_M_RD)) 325 geni_i2c_err(gi2c, DATA_NACK); 326 } 327 328 static irqreturn_t geni_i2c_irq(int irq, void *dev) 329 { 330 struct geni_i2c_dev *gi2c = dev; 331 void __iomem *base = gi2c->se.base; 332 int j, p; 333 u32 m_stat; 334 u32 rx_st; 335 u32 dm_tx_st; 336 u32 dm_rx_st; 337 u32 dma; 338 u32 val; 339 struct i2c_msg *cur; 340 341 spin_lock(&gi2c->lock); 342 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS); 343 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS); 344 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT); 345 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT); 346 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 347 cur = gi2c->cur; 348 349 trace_geni_i2c_irq(gi2c->se.dev, m_stat, rx_st, dm_tx_st, dm_rx_st); 350 351 if (!cur || 352 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) || 353 dm_rx_st & (DM_I2C_CB_ERR)) { 354 if (m_stat & M_GP_IRQ_1_EN) 355 geni_i2c_check_addr_data_nack(gi2c); 356 if (m_stat & M_GP_IRQ_3_EN) 357 geni_i2c_err(gi2c, BUS_PROTO); 358 if (m_stat & M_GP_IRQ_4_EN) 359 geni_i2c_err(gi2c, ARB_LOST); 360 if (m_stat & M_CMD_OVERRUN_EN) 361 geni_i2c_err(gi2c, GENI_OVERRUN); 362 if (m_stat & M_ILLEGAL_CMD_EN) 363 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD); 364 if (m_stat & M_CMD_ABORT_EN) 365 geni_i2c_err(gi2c, GENI_ABORT_DONE); 366 if (m_stat & M_GP_IRQ_0_EN) 367 geni_i2c_err(gi2c, GP_IRQ0); 368 369 /* Disable the TX Watermark interrupt to stop TX */ 370 if (!dma) 371 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 372 } else if (dma) { 373 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n", 374 dm_tx_st, dm_rx_st); 375 } else if (cur->flags & I2C_M_RD && 376 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) { 377 u32 rxcnt = rx_st & RX_FIFO_WC_MSK; 378 379 for (j = 0; j < rxcnt; j++) { 380 p = 0; 381 val = readl_relaxed(base + SE_GENI_RX_FIFOn); 382 while (gi2c->cur_rd < cur->len && p < sizeof(val)) { 383 cur->buf[gi2c->cur_rd++] = val & 0xff; 384 val >>= 8; 385 p++; 386 } 387 if (gi2c->cur_rd == cur->len) 388 break; 389 } 390 } else if (!(cur->flags & I2C_M_RD) && 391 m_stat & M_TX_FIFO_WATERMARK_EN) { 392 for (j = 0; j < gi2c->tx_wm; j++) { 393 u32 temp; 394 395 val = 0; 396 p = 0; 397 while (gi2c->cur_wr < cur->len && p < sizeof(val)) { 398 temp = cur->buf[gi2c->cur_wr++]; 399 val |= temp << (p * 8); 400 p++; 401 } 402 writel_relaxed(val, base + SE_GENI_TX_FIFOn); 403 /* TX Complete, Disable the TX Watermark interrupt */ 404 if (gi2c->cur_wr == cur->len) { 405 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 406 break; 407 } 408 } 409 } 410 411 if (m_stat) 412 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR); 413 414 if (dma && dm_tx_st) 415 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR); 416 if (dma && dm_rx_st) 417 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR); 418 419 /* if this is err with done-bit not set, handle that through timeout. */ 420 if (m_stat & M_CMD_DONE_EN || 421 dm_tx_st & TX_DMA_DONE || 422 dm_rx_st & RX_DMA_DONE) 423 complete(&gi2c->done); 424 if (m_stat & M_CMD_CANCEL_EN) 425 complete(&gi2c->cancel_done); 426 if (m_stat & M_CMD_ABORT_EN) 427 complete(&gi2c->abort_done); 428 if (dm_tx_st & TX_RESET_DONE) 429 complete(&gi2c->tx_reset_done); 430 if (dm_rx_st & RX_RESET_DONE) 431 complete(&gi2c->rx_reset_done); 432 433 spin_unlock(&gi2c->lock); 434 435 return IRQ_HANDLED; 436 } 437 438 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c) 439 { 440 unsigned long time_left = ABORT_TIMEOUT; 441 unsigned long flags; 442 443 reinit_completion(&gi2c->abort_done); 444 445 spin_lock_irqsave(&gi2c->lock, flags); 446 geni_se_abort_m_cmd(&gi2c->se); 447 spin_unlock_irqrestore(&gi2c->lock, flags); 448 449 time_left = wait_for_completion_timeout(&gi2c->abort_done, time_left); 450 if (!time_left) 451 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n"); 452 } 453 454 static void geni_i2c_cancel_xfer(struct geni_i2c_dev *gi2c) 455 { 456 unsigned long time_left = msecs_to_jiffies(CANCEL_TIMEOUT); 457 unsigned long flags; 458 459 reinit_completion(&gi2c->cancel_done); 460 461 spin_lock_irqsave(&gi2c->lock, flags); 462 if (!gi2c->err) 463 geni_i2c_err(gi2c, GENI_TIMEOUT); 464 gi2c->cur = NULL; 465 geni_se_cancel_m_cmd(&gi2c->se); 466 spin_unlock_irqrestore(&gi2c->lock, flags); 467 468 time_left = wait_for_completion_timeout(&gi2c->cancel_done, time_left); 469 if (!time_left) { 470 dev_err(gi2c->se.dev, "Timeout cancel_m_cmd\n"); 471 geni_i2c_abort_xfer(gi2c); 472 } 473 } 474 475 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c) 476 { 477 unsigned long time_left = RST_TIMEOUT; 478 479 reinit_completion(&gi2c->rx_reset_done); 480 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST); 481 482 time_left = wait_for_completion_timeout(&gi2c->rx_reset_done, time_left); 483 if (!time_left) 484 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n"); 485 } 486 487 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c) 488 { 489 unsigned long time_left = RST_TIMEOUT; 490 491 reinit_completion(&gi2c->tx_reset_done); 492 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST); 493 494 time_left = wait_for_completion_timeout(&gi2c->tx_reset_done, time_left); 495 if (!time_left) 496 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n"); 497 } 498 499 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c, 500 struct i2c_msg *cur) 501 { 502 gi2c->cur_rd = 0; 503 if (gi2c->dma_buf) { 504 if (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err) 505 geni_i2c_rx_fsm_rst(gi2c); 506 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 507 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 508 } 509 } 510 511 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c, 512 struct i2c_msg *cur) 513 { 514 gi2c->cur_wr = 0; 515 if (gi2c->dma_buf) { 516 if (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err) 517 geni_i2c_tx_fsm_rst(gi2c); 518 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 519 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 520 } 521 } 522 523 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 524 u32 m_param) 525 { 526 dma_addr_t rx_dma = 0; 527 unsigned long time_left; 528 void *dma_buf; 529 struct geni_se *se = &gi2c->se; 530 size_t len = msg->len; 531 struct i2c_msg *cur; 532 533 dma_buf = gi2c->no_dma ? NULL : i2c_get_dma_safe_msg_buf(msg, 32); 534 if (dma_buf) 535 geni_se_select_mode(se, GENI_SE_DMA); 536 else 537 geni_se_select_mode(se, GENI_SE_FIFO); 538 539 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); 540 geni_se_setup_m_cmd(se, I2C_READ, m_param); 541 542 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { 543 geni_se_select_mode(se, GENI_SE_FIFO); 544 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 545 dma_buf = NULL; 546 } else { 547 gi2c->xfer_len = len; 548 gi2c->dma_addr = rx_dma; 549 gi2c->dma_buf = dma_buf; 550 } 551 552 cur = gi2c->cur; 553 i2c_update_timeout(&gi2c->adap, gi2c->clk_freq_out, len, 554 I2C_TIMEOUT_SAFETY_COEFFICIENT, 555 I2C_TIMEOUT_MIN_USEC); 556 time_left = wait_for_completion_timeout(&gi2c->done, gi2c->adap.timeout); 557 if (!time_left || (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err)) 558 geni_i2c_cancel_xfer(gi2c); 559 560 geni_i2c_rx_msg_cleanup(gi2c, cur); 561 562 return gi2c->err; 563 } 564 565 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 566 u32 m_param) 567 { 568 dma_addr_t tx_dma = 0; 569 unsigned long time_left; 570 void *dma_buf; 571 struct geni_se *se = &gi2c->se; 572 size_t len = msg->len; 573 struct i2c_msg *cur; 574 575 dma_buf = gi2c->no_dma ? NULL : i2c_get_dma_safe_msg_buf(msg, 32); 576 if (dma_buf) 577 geni_se_select_mode(se, GENI_SE_DMA); 578 else 579 geni_se_select_mode(se, GENI_SE_FIFO); 580 581 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); 582 geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 583 584 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { 585 geni_se_select_mode(se, GENI_SE_FIFO); 586 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 587 dma_buf = NULL; 588 } else { 589 gi2c->xfer_len = len; 590 gi2c->dma_addr = tx_dma; 591 gi2c->dma_buf = dma_buf; 592 } 593 594 if (!dma_buf) /* Get FIFO IRQ */ 595 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG); 596 597 cur = gi2c->cur; 598 i2c_update_timeout(&gi2c->adap, gi2c->clk_freq_out, len, 599 I2C_TIMEOUT_SAFETY_COEFFICIENT, 600 I2C_TIMEOUT_MIN_USEC); 601 time_left = wait_for_completion_timeout(&gi2c->done, gi2c->adap.timeout); 602 if (!time_left || (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err)) 603 geni_i2c_cancel_xfer(gi2c); 604 605 geni_i2c_tx_msg_cleanup(gi2c, cur); 606 607 return gi2c->err; 608 } 609 610 static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result) 611 { 612 struct geni_i2c_dev *gi2c = cb; 613 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer; 614 615 if (result->result != DMA_TRANS_NOERROR) { 616 dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result); 617 gi2c->err = -EIO; 618 } else if (result->residue) { 619 dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue); 620 } 621 622 if (gi2c->is_tx_multi_desc_xfer) { 623 tx_multi_xfer = &gi2c->i2c_multi_desc_config; 624 tx_multi_xfer->irq_cnt++; 625 } 626 627 complete(&gi2c->done); 628 } 629 630 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 631 void *tx_buf, dma_addr_t tx_addr, 632 void *rx_buf, dma_addr_t rx_addr) 633 { 634 if (tx_buf) { 635 dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE); 636 i2c_put_dma_safe_msg_buf(tx_buf, msg, !gi2c->err); 637 } 638 639 if (rx_buf) { 640 dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE); 641 i2c_put_dma_safe_msg_buf(rx_buf, msg, !gi2c->err); 642 } 643 } 644 645 /** 646 * geni_i2c_gpi_multi_desc_unmap() - Unmaps DMA buffers post multi message TX transfers 647 * @gi2c: I2C dev handle 648 * @msgs: Array of I2C messages 649 * @peripheral: Pointer to gpi_i2c_config 650 */ 651 static void geni_i2c_gpi_multi_desc_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], 652 struct gpi_i2c_config *peripheral) 653 { 654 u32 msg_xfer_cnt, wr_idx = 0; 655 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer = &gi2c->i2c_multi_desc_config; 656 657 msg_xfer_cnt = gi2c->err ? tx_multi_xfer->msg_idx_cnt : tx_multi_xfer->irq_cnt; 658 659 /* Unmap the processed DMA buffers based on the received interrupt count */ 660 for (; tx_multi_xfer->unmap_msg_cnt < msg_xfer_cnt; tx_multi_xfer->unmap_msg_cnt++) { 661 wr_idx = tx_multi_xfer->unmap_msg_cnt; 662 geni_i2c_gpi_unmap(gi2c, &msgs[wr_idx], 663 tx_multi_xfer->dma_buf[wr_idx], 664 tx_multi_xfer->dma_addr[wr_idx], 665 NULL, 0); 666 667 if (tx_multi_xfer->unmap_msg_cnt == gi2c->num_msgs - 1) { 668 kfree(tx_multi_xfer->dma_buf); 669 kfree(tx_multi_xfer->dma_addr); 670 break; 671 } 672 } 673 } 674 675 /** 676 * geni_i2c_gpi_multi_xfer_timeout_handler() - Handles multi message transfer timeout 677 * @dev: Pointer to the corresponding dev node 678 * @multi_xfer: Pointer to the geni_i2c_gpi_multi_desc_xfer 679 * @timeout_jiffies: Per-message completion timeout in jiffies 680 * @transfer_comp: Completion object of the transfer 681 * 682 * This function waits for the completion of each processed transfer messages 683 * based on the interrupts generated upon transfer completion. 684 * 685 * Return: On success returns 0, -ETIMEDOUT on timeout. 686 */ 687 static int geni_i2c_gpi_multi_xfer_timeout_handler(struct device *dev, 688 struct geni_i2c_gpi_multi_desc_xfer *multi_xfer, 689 unsigned long timeout_jiffies, 690 struct completion *transfer_comp) 691 { 692 int i; 693 unsigned long time_left; 694 695 for (i = 0; i < multi_xfer->msg_idx_cnt - 1; i++) { 696 reinit_completion(transfer_comp); 697 698 if (multi_xfer->msg_idx_cnt != multi_xfer->irq_cnt) { 699 time_left = wait_for_completion_timeout(transfer_comp, 700 timeout_jiffies); 701 if (!time_left) { 702 dev_err(dev, "%s: Transfer timeout\n", __func__); 703 return -ETIMEDOUT; 704 } 705 } 706 } 707 return 0; 708 } 709 710 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], 711 struct dma_slave_config *config, dma_addr_t *dma_addr_p, 712 void **buf, unsigned int op, struct dma_chan *dma_chan) 713 { 714 struct gpi_i2c_config *peripheral; 715 unsigned int flags; 716 void *dma_buf = NULL; 717 dma_addr_t addr = 0; 718 enum dma_data_direction map_dirn; 719 enum dma_transfer_direction dma_dirn; 720 struct dma_async_tx_descriptor *desc; 721 int ret; 722 struct geni_i2c_gpi_multi_desc_xfer *gi2c_gpi_xfer; 723 dma_cookie_t cookie; 724 u32 msg_idx; 725 726 peripheral = config->peripheral_config; 727 gi2c_gpi_xfer = &gi2c->i2c_multi_desc_config; 728 msg_idx = gi2c_gpi_xfer->msg_idx_cnt; 729 730 /* 731 * Skip TX DMA mapping for a read message (I2C_M_RD) to avoid 732 * programming an extra TX DMA TRE that would cause an unintended 733 * write cycle on the I2C bus before the actual read operation. 734 */ 735 if (op == I2C_WRITE && msgs[msg_idx].flags & I2C_M_RD) { 736 peripheral->multi_msg = true; 737 goto skip_tx_dma_map; 738 } 739 740 dma_buf = i2c_get_dma_safe_msg_buf(&msgs[msg_idx], 1); 741 if (!dma_buf) { 742 ret = -ENOMEM; 743 goto out; 744 } 745 746 if (op == I2C_WRITE) 747 map_dirn = DMA_TO_DEVICE; 748 else 749 map_dirn = DMA_FROM_DEVICE; 750 751 addr = dma_map_single(gi2c->se.dev->parent, dma_buf, 752 msgs[msg_idx].len, map_dirn); 753 if (dma_mapping_error(gi2c->se.dev->parent, addr)) { 754 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); 755 ret = -ENOMEM; 756 goto out; 757 } 758 759 skip_tx_dma_map: 760 if (gi2c->is_tx_multi_desc_xfer) { 761 flags = DMA_CTRL_ACK; 762 763 /* BEI bit to be cleared for last TRE */ 764 if (msg_idx == gi2c->num_msgs - 1) 765 flags |= DMA_PREP_INTERRUPT; 766 } else { 767 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 768 } 769 770 /* set the length as message for rx txn */ 771 peripheral->rx_len = msgs[msg_idx].len; 772 peripheral->op = op; 773 774 ret = dmaengine_slave_config(dma_chan, config); 775 if (ret) { 776 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op); 777 goto err_config; 778 } 779 780 peripheral->set_config = 0; 781 peripheral->multi_msg = true; 782 783 if (op == I2C_WRITE) 784 dma_dirn = DMA_MEM_TO_DEV; 785 else 786 dma_dirn = DMA_DEV_TO_MEM; 787 788 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len, 789 dma_dirn, flags); 790 if (!desc && !(flags & DMA_PREP_INTERRUPT)) { 791 /* Retry with interrupt if not enough TREs */ 792 flags |= DMA_PREP_INTERRUPT; 793 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len, 794 dma_dirn, flags); 795 } 796 797 if (!desc) { 798 dev_err(gi2c->se.dev, "prep_slave_sg failed\n"); 799 ret = -EIO; 800 goto err_config; 801 } 802 803 desc->callback_result = i2c_gpi_cb_result; 804 desc->callback_param = gi2c; 805 806 if (!((msgs[msg_idx].flags & I2C_M_RD) && op == I2C_WRITE)) 807 gi2c_gpi_xfer->msg_idx_cnt++; 808 809 cookie = dmaengine_submit(desc); 810 if (dma_submit_error(cookie)) { 811 dev_err(gi2c->se.dev, 812 "%s: dmaengine_submit failed (%d)\n", __func__, cookie); 813 ret = -EINVAL; 814 goto err_config; 815 } 816 817 if (gi2c->is_tx_multi_desc_xfer) { 818 gi2c_gpi_xfer->dma_buf[msg_idx] = dma_buf; 819 gi2c_gpi_xfer->dma_addr[msg_idx] = addr; 820 821 dma_async_issue_pending(gi2c->tx_c); 822 823 if ((msg_idx == (gi2c->num_msgs - 1)) || flags & DMA_PREP_INTERRUPT) { 824 size_t total_len = 0; 825 int j; 826 827 /* 828 * All TREs except the last carry the BEI bit, so a single 829 * completion interrupt fires only after the entire batch has 830 * drained on the wire. The timeout budget must therefore cover 831 * the combined wire time of every message in the batch. 832 */ 833 for (j = 0; j < gi2c->num_msgs; j++) 834 total_len += msgs[j].len; 835 836 i2c_update_timeout(&gi2c->adap, gi2c->clk_freq_out, total_len, 837 I2C_TIMEOUT_SAFETY_COEFFICIENT, 838 I2C_TIMEOUT_MIN_USEC); 839 ret = geni_i2c_gpi_multi_xfer_timeout_handler(gi2c->se.dev, gi2c_gpi_xfer, 840 gi2c->adap.timeout, 841 &gi2c->done); 842 if (ret) { 843 dev_err(gi2c->se.dev, 844 "I2C multi write msg transfer timeout: %d\n", 845 ret); 846 gi2c->err = ret; 847 return ret; 848 } 849 } 850 } else { 851 /* Non multi descriptor message transfer */ 852 *buf = dma_buf; 853 *dma_addr_p = addr; 854 } 855 return 0; 856 857 err_config: 858 /* Avoid DMA unmap as the write operation skipped DMA mapping */ 859 if (dma_buf) { 860 dma_unmap_single(gi2c->se.dev->parent, addr, 861 msgs[msg_idx].len, map_dirn); 862 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); 863 } 864 865 out: 866 gi2c->err = ret; 867 return ret; 868 } 869 870 static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num) 871 { 872 struct dma_slave_config config = {}; 873 struct gpi_i2c_config peripheral = {}; 874 int i, ret = 0; 875 unsigned long time_left; 876 dma_addr_t tx_addr, rx_addr; 877 void *tx_buf = NULL, *rx_buf = NULL; 878 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer; 879 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 880 881 config.peripheral_config = &peripheral; 882 config.peripheral_size = sizeof(peripheral); 883 884 peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX; 885 peripheral.cycle_count = itr->t_cycle_cnt; 886 peripheral.high_count = itr->t_high_cnt; 887 peripheral.low_count = itr->t_low_cnt; 888 peripheral.clk_div = itr->clk_div; 889 peripheral.set_config = 1; 890 peripheral.multi_msg = false; 891 892 trace_geni_i2c_bus_setup(gi2c->se.dev, gi2c->clk_freq_out, 893 itr->clk_div, itr->t_high_cnt, 894 itr->t_low_cnt, itr->t_cycle_cnt); 895 896 gi2c->num_msgs = num; 897 gi2c->is_tx_multi_desc_xfer = false; 898 899 tx_multi_xfer = &gi2c->i2c_multi_desc_config; 900 memset(tx_multi_xfer, 0, sizeof(struct geni_i2c_gpi_multi_desc_xfer)); 901 902 /* 903 * If number of write messages are two and higher then 904 * configure hardware for multi descriptor transfers with BEI. 905 */ 906 if (num >= QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC) { 907 gi2c->is_tx_multi_desc_xfer = true; 908 for (i = 0; i < num; i++) { 909 if (msgs[i].flags & I2C_M_RD) { 910 /* 911 * Multi descriptor transfer with BEI 912 * support is enabled for write transfers. 913 * TODO: Add BEI optimization support for 914 * read transfers later. 915 */ 916 gi2c->is_tx_multi_desc_xfer = false; 917 break; 918 } 919 } 920 } 921 922 if (gi2c->is_tx_multi_desc_xfer) { 923 tx_multi_xfer->dma_buf = kcalloc(num, sizeof(void *), GFP_KERNEL); 924 tx_multi_xfer->dma_addr = kzalloc_objs(dma_addr_t, num); 925 if (!tx_multi_xfer->dma_buf || !tx_multi_xfer->dma_addr) { 926 ret = -ENOMEM; 927 goto err; 928 } 929 } 930 931 for (i = 0; i < num; i++) { 932 gi2c->cur = &msgs[i]; 933 gi2c->err = 0; 934 reinit_completion(&gi2c->done); 935 dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len); 936 937 peripheral.stretch = 0; 938 if (i < num - 1) 939 peripheral.stretch = 1; 940 941 peripheral.addr = msgs[i].addr; 942 if (i > 0 && (!(msgs[i].flags & I2C_M_RD))) 943 peripheral.multi_msg = false; 944 945 ret = geni_i2c_gpi(gi2c, msgs, &config, 946 &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); 947 if (ret) 948 goto err; 949 950 if (msgs[i].flags & I2C_M_RD) { 951 ret = geni_i2c_gpi(gi2c, msgs, &config, 952 &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c); 953 if (ret) 954 goto err; 955 956 dma_async_issue_pending(gi2c->rx_c); 957 } 958 959 if (!gi2c->is_tx_multi_desc_xfer) { 960 dma_async_issue_pending(gi2c->tx_c); 961 i2c_update_timeout(&gi2c->adap, gi2c->clk_freq_out, msgs[i].len, 962 I2C_TIMEOUT_SAFETY_COEFFICIENT, 963 I2C_TIMEOUT_MIN_USEC); 964 time_left = wait_for_completion_timeout(&gi2c->done, gi2c->adap.timeout); 965 if (!time_left) { 966 dev_err(gi2c->se.dev, "%s:I2C timeout\n", __func__); 967 gi2c->err = -ETIMEDOUT; 968 } 969 } 970 971 if (gi2c->err) { 972 ret = gi2c->err; 973 goto err; 974 } 975 976 if (!gi2c->is_tx_multi_desc_xfer) 977 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); 978 else if (tx_multi_xfer->unmap_msg_cnt != tx_multi_xfer->irq_cnt) 979 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral); 980 } 981 982 return num; 983 984 err: 985 dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret); 986 dmaengine_terminate_sync(gi2c->rx_c); 987 dmaengine_terminate_sync(gi2c->tx_c); 988 if (gi2c->is_tx_multi_desc_xfer) 989 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral); 990 else 991 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); 992 993 return ret; 994 } 995 996 static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c, 997 struct i2c_msg msgs[], int num) 998 { 999 int i, ret = 0; 1000 1001 for (i = 0; i < num; i++) { 1002 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; 1003 1004 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); 1005 1006 gi2c->cur = &msgs[i]; 1007 gi2c->err = 0; 1008 reinit_completion(&gi2c->done); 1009 if (msgs[i].flags & I2C_M_RD) 1010 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param); 1011 else 1012 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param); 1013 1014 if (ret) 1015 return ret; 1016 } 1017 1018 return num; 1019 } 1020 1021 static int geni_i2c_xfer(struct i2c_adapter *adap, 1022 struct i2c_msg msgs[], 1023 int num) 1024 { 1025 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap); 1026 int ret; 1027 1028 ret = pm_runtime_resume_and_get(gi2c->se.dev); 1029 if (ret < 0) { 1030 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret); 1031 /* Set device in suspended since resume failed */ 1032 pm_runtime_set_suspended(gi2c->se.dev); 1033 return ret; 1034 } 1035 1036 ret = gi2c->dev_data->set_rate(&gi2c->se, gi2c->clk_freq_out); 1037 if (ret) 1038 goto out_pm; 1039 1040 if (gi2c->gpi_mode) 1041 ret = geni_i2c_gpi_xfer(gi2c, msgs, num); 1042 else 1043 ret = geni_i2c_fifo_xfer(gi2c, msgs, num); 1044 1045 out_pm: 1046 pm_runtime_put_autosuspend(gi2c->se.dev); 1047 gi2c->cur = NULL; 1048 gi2c->err = 0; 1049 return ret; 1050 } 1051 1052 static u32 geni_i2c_func(struct i2c_adapter *adap) 1053 { 1054 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1055 } 1056 1057 static const struct i2c_algorithm geni_i2c_algo = { 1058 .xfer = geni_i2c_xfer, 1059 .functionality = geni_i2c_func, 1060 }; 1061 1062 static void release_gpi_dma(struct geni_i2c_dev *gi2c) 1063 { 1064 if (gi2c->rx_c) 1065 dma_release_channel(gi2c->rx_c); 1066 1067 if (gi2c->tx_c) 1068 dma_release_channel(gi2c->tx_c); 1069 } 1070 1071 static int setup_gpi_dma(struct geni_i2c_dev *gi2c) 1072 { 1073 int ret; 1074 1075 geni_se_select_mode(&gi2c->se, GENI_GPI_DMA); 1076 gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx"); 1077 if (IS_ERR(gi2c->tx_c)) { 1078 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c), 1079 "Failed to get tx DMA ch\n"); 1080 goto err_tx; 1081 } 1082 1083 gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx"); 1084 if (IS_ERR(gi2c->rx_c)) { 1085 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c), 1086 "Failed to get rx DMA ch\n"); 1087 goto err_rx; 1088 } 1089 1090 dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n"); 1091 return 0; 1092 1093 err_rx: 1094 dma_release_channel(gi2c->tx_c); 1095 err_tx: 1096 return ret; 1097 } 1098 1099 static int geni_i2c_init(struct geni_i2c_dev *gi2c) 1100 { 1101 u32 proto, tx_depth; 1102 bool fifo_disable; 1103 int ret; 1104 1105 ret = pm_runtime_resume_and_get(gi2c->se.dev); 1106 if (ret < 0) 1107 return dev_err_probe(gi2c->se.dev, ret, "error turning on device\n"); 1108 1109 proto = geni_se_read_proto(&gi2c->se); 1110 if (proto == GENI_SE_INVALID_PROTO) { 1111 ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C); 1112 if (ret) { 1113 dev_err_probe(gi2c->se.dev, ret, "i2c firmware load failed ret: %d\n", ret); 1114 goto err; 1115 } 1116 } else if (proto != GENI_SE_I2C) { 1117 ret = dev_err_probe(gi2c->se.dev, -ENXIO, "Invalid proto %d\n", proto); 1118 goto err; 1119 } 1120 1121 if (gi2c->dev_data->no_dma_support) { 1122 fifo_disable = false; 1123 gi2c->no_dma = true; 1124 } else { 1125 fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 1126 } 1127 1128 if (fifo_disable) { 1129 /* FIFO is disabled, so we can only use GPI DMA */ 1130 gi2c->gpi_mode = true; 1131 ret = setup_gpi_dma(gi2c); 1132 if (ret) 1133 goto err; 1134 1135 dev_dbg(gi2c->se.dev, "Using GPI DMA mode for I2C\n"); 1136 } else { 1137 gi2c->gpi_mode = false; 1138 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); 1139 1140 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ 1141 if (!tx_depth && gi2c->se.core_clk) 1142 tx_depth = gi2c->dev_data->tx_fifo_depth; 1143 1144 if (!tx_depth) { 1145 ret = dev_err_probe(gi2c->se.dev, -EINVAL, 1146 "Invalid TX FIFO depth\n"); 1147 goto err; 1148 } 1149 1150 gi2c->tx_wm = tx_depth - 1; 1151 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); 1152 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, 1153 PACKING_BYTES_PW, true, true, true); 1154 1155 dev_dbg(gi2c->se.dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); 1156 } 1157 1158 err: 1159 pm_runtime_put(gi2c->se.dev); 1160 return ret; 1161 } 1162 1163 static int geni_i2c_resources_init(struct geni_se *se) 1164 { 1165 struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev); 1166 int ret; 1167 1168 ret = geni_se_resources_init(&gi2c->se); 1169 if (ret) 1170 return ret; 1171 1172 ret = geni_i2c_clk_map_idx(gi2c); 1173 if (ret) 1174 return ret; 1175 1176 return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, 1177 Bps_to_icc(gi2c->clk_freq_out)); 1178 } 1179 1180 static int geni_i2c_probe(struct platform_device *pdev) 1181 { 1182 struct geni_i2c_dev *gi2c; 1183 int ret; 1184 struct device *dev = &pdev->dev; 1185 1186 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL); 1187 if (!gi2c) 1188 return -ENOMEM; 1189 1190 gi2c->se.dev = dev; 1191 gi2c->se.wrapper = dev_get_drvdata(dev->parent); 1192 gi2c->se.base = devm_platform_ioremap_resource(pdev, 0); 1193 if (IS_ERR(gi2c->se.base)) 1194 return PTR_ERR(gi2c->se.base); 1195 1196 gi2c->dev_data = device_get_match_data(&pdev->dev); 1197 if (!gi2c->dev_data) 1198 return -EINVAL; 1199 1200 ret = device_property_read_u32(dev, "clock-frequency", 1201 &gi2c->clk_freq_out); 1202 if (ret) { 1203 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n"); 1204 gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ; 1205 } 1206 1207 gi2c->irq = platform_get_irq(pdev, 0); 1208 if (gi2c->irq < 0) 1209 return gi2c->irq; 1210 1211 gi2c->adap.algo = &geni_i2c_algo; 1212 init_completion(&gi2c->done); 1213 init_completion(&gi2c->abort_done); 1214 init_completion(&gi2c->cancel_done); 1215 init_completion(&gi2c->tx_reset_done); 1216 init_completion(&gi2c->rx_reset_done); 1217 spin_lock_init(&gi2c->lock); 1218 platform_set_drvdata(pdev, gi2c); 1219 1220 ret = gi2c->dev_data->resources_init(&gi2c->se); 1221 if (ret) 1222 return ret; 1223 1224 /* Keep interrupts disabled initially to allow for low-power modes */ 1225 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN, 1226 dev_name(dev), gi2c); 1227 if (ret) 1228 return ret; 1229 1230 i2c_set_adapdata(&gi2c->adap, gi2c); 1231 gi2c->adap.dev.parent = dev; 1232 device_set_node(&gi2c->adap.dev, dev_fwnode(dev)); 1233 strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); 1234 1235 pm_runtime_set_suspended(dev); 1236 pm_runtime_set_autosuspend_delay(dev, I2C_AUTO_SUSPEND_DELAY); 1237 pm_runtime_use_autosuspend(dev); 1238 1239 ret = devm_pm_runtime_enable(dev); 1240 if (ret) 1241 return ret; 1242 1243 ret = geni_i2c_init(gi2c); 1244 if (ret < 0) 1245 return ret; 1246 1247 ret = i2c_add_adapter(&gi2c->adap); 1248 if (ret) { 1249 release_gpi_dma(gi2c); 1250 return dev_err_probe(dev, ret, "Error adding i2c adapter\n"); 1251 } 1252 1253 dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); 1254 1255 return 0; 1256 } 1257 1258 static void geni_i2c_remove(struct platform_device *pdev) 1259 { 1260 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 1261 1262 i2c_del_adapter(&gi2c->adap); 1263 release_gpi_dma(gi2c); 1264 } 1265 1266 static void geni_i2c_shutdown(struct platform_device *pdev) 1267 { 1268 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 1269 1270 /* Make client i2c transfers start failing */ 1271 i2c_mark_adapter_suspended(&gi2c->adap); 1272 } 1273 1274 static int geni_i2c_runtime_suspend(struct device *dev) 1275 { 1276 int ret = 0; 1277 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1278 1279 disable_irq(gi2c->irq); 1280 1281 if (gi2c->dev_data->power_off) { 1282 ret = gi2c->dev_data->power_off(&gi2c->se); 1283 if (ret) { 1284 enable_irq(gi2c->irq); 1285 return ret; 1286 } 1287 } 1288 1289 return 0; 1290 } 1291 1292 static int geni_i2c_runtime_resume(struct device *dev) 1293 { 1294 int ret = 0; 1295 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1296 1297 if (gi2c->dev_data->power_on) { 1298 ret = gi2c->dev_data->power_on(&gi2c->se); 1299 if (ret) 1300 return ret; 1301 } 1302 1303 enable_irq(gi2c->irq); 1304 1305 return 0; 1306 } 1307 1308 static int geni_i2c_suspend_noirq(struct device *dev) 1309 { 1310 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1311 int ret; 1312 1313 i2c_mark_adapter_suspended(&gi2c->adap); 1314 1315 ret = pm_runtime_force_suspend(dev); 1316 if (ret) 1317 i2c_mark_adapter_resumed(&gi2c->adap); 1318 1319 return ret; 1320 } 1321 1322 static int geni_i2c_resume_noirq(struct device *dev) 1323 { 1324 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1325 int ret; 1326 1327 ret = pm_runtime_force_resume(dev); 1328 if (ret) 1329 return ret; 1330 1331 i2c_mark_adapter_resumed(&gi2c->adap); 1332 return 0; 1333 } 1334 1335 static const struct dev_pm_ops geni_i2c_pm_ops = { 1336 NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, 1337 geni_i2c_resume_noirq) 1338 RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume, 1339 NULL) 1340 }; 1341 1342 static const struct geni_i2c_desc geni_i2c = { 1343 .resources_init = geni_i2c_resources_init, 1344 .set_rate = qcom_geni_i2c_conf, 1345 .power_on = geni_se_resources_activate, 1346 .power_off = geni_se_resources_deactivate, 1347 }; 1348 1349 static const struct geni_i2c_desc i2c_master_hub = { 1350 .no_dma_support = true, 1351 .tx_fifo_depth = 16, 1352 .resources_init = geni_i2c_resources_init, 1353 .set_rate = qcom_geni_i2c_conf, 1354 .power_on = geni_se_resources_activate, 1355 .power_off = geni_se_resources_deactivate, 1356 }; 1357 1358 static const struct geni_i2c_desc sa8255p_geni_i2c = { 1359 .resources_init = geni_se_domain_attach, 1360 .set_rate = geni_se_set_perf_opp, 1361 }; 1362 1363 #ifdef CONFIG_ACPI 1364 static const struct acpi_device_id geni_i2c_acpi_match[] = { 1365 { .id = "QCOM0220", .driver_data = (kernel_ulong_t)&geni_i2c }, 1366 { .id = "QCOM0411", .driver_data = (kernel_ulong_t)&geni_i2c }, 1367 { } 1368 }; 1369 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match); 1370 #endif 1371 1372 static const struct of_device_id geni_i2c_dt_match[] = { 1373 { .compatible = "qcom,geni-i2c", .data = &geni_i2c }, 1374 { .compatible = "qcom,geni-i2c-master-hub", .data = &i2c_master_hub }, 1375 { .compatible = "qcom,sa8255p-geni-i2c", .data = &sa8255p_geni_i2c }, 1376 {} 1377 }; 1378 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); 1379 1380 static struct platform_driver geni_i2c_driver = { 1381 .probe = geni_i2c_probe, 1382 .remove = geni_i2c_remove, 1383 .shutdown = geni_i2c_shutdown, 1384 .driver = { 1385 .name = "geni_i2c", 1386 .pm = &geni_i2c_pm_ops, 1387 .of_match_table = geni_i2c_dt_match, 1388 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match), 1389 }, 1390 }; 1391 1392 module_platform_driver(geni_i2c_driver); 1393 1394 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores"); 1395 MODULE_LICENSE("GPL v2"); 1396