1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD9833/AD9834/AD9837/AD9838 SPI DDS driver 4 * 5 * Copyright 2010-2011 Analog Devices Inc. 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/clk.h> 10 #include <linux/dev_printk.h> 11 #include <linux/err.h> 12 #include <linux/kstrtox.h> 13 #include <linux/mod_devicetable.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/spi/spi.h> 18 #include <linux/string.h> 19 #include <linux/sysfs.h> 20 #include <linux/types.h> 21 22 #include <asm/byteorder.h> 23 #include <asm/div64.h> 24 25 #include <linux/iio/iio.h> 26 #include <linux/iio/sysfs.h> 27 28 #include "dds.h" 29 30 /* Registers */ 31 32 #define AD9834_REG_CMD 0 33 #define AD9834_REG_FREQ0 BIT(14) 34 #define AD9834_REG_FREQ1 BIT(15) 35 #define AD9834_REG_PHASE0 (BIT(15) | BIT(14)) 36 #define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13)) 37 38 /* Command Control Bits */ 39 40 #define AD9834_B28 BIT(13) 41 #define AD9834_HLB BIT(12) 42 #define AD9834_FSEL BIT(11) 43 #define AD9834_PSEL BIT(10) 44 #define AD9834_PIN_SW BIT(9) 45 #define AD9834_RESET BIT(8) 46 #define AD9834_SLEEP1 BIT(7) 47 #define AD9834_SLEEP12 BIT(6) 48 #define AD9834_OPBITEN BIT(5) 49 #define AD9834_SIGN_PIB BIT(4) 50 #define AD9834_DIV2 BIT(3) 51 #define AD9834_MODE BIT(1) 52 53 #define AD9834_FREQ_BITS 28 54 #define AD9834_PHASE_BITS 12 55 56 #define RES_MASK(bits) (BIT(bits) - 1) 57 58 /** 59 * struct ad9834_state - driver instance specific data 60 * @spi: spi_device 61 * @mclk: external master clock 62 * @control: cached control word 63 * @devid: device id 64 * @xfer: default spi transfer 65 * @msg: default spi message 66 * @freq_xfer: tuning word spi transfer 67 * @freq_msg: tuning word spi message 68 * @lock: protect sensor state 69 * @data: spi transmit buffer 70 * @freq_data: tuning word spi transmit buffer 71 */ 72 73 struct ad9834_state { 74 struct spi_device *spi; 75 struct clk *mclk; 76 unsigned short control; 77 unsigned short devid; 78 struct spi_transfer xfer; 79 struct spi_message msg; 80 struct spi_transfer freq_xfer[2]; 81 struct spi_message freq_msg; 82 struct mutex lock; /* protect sensor state */ 83 84 /* 85 * DMA (thus cache coherency maintenance) requires the 86 * transfer buffers to live in their own cache lines. 87 */ 88 __be16 data __aligned(IIO_DMA_MINALIGN); 89 __be16 freq_data[2]; 90 }; 91 92 /* 93 * ad9834_supported_device_ids: 94 */ 95 96 enum ad9834_supported_device_ids { 97 ID_AD9833, 98 ID_AD9834, 99 ID_AD9837, 100 ID_AD9838, 101 }; 102 103 static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout) 104 { 105 unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS); 106 107 do_div(freqreg, mclk); 108 return freqreg; 109 } 110 111 static int ad9834_write_frequency(struct ad9834_state *st, 112 unsigned long addr, unsigned long fout) 113 { 114 unsigned long clk_freq; 115 unsigned long regval; 116 117 clk_freq = clk_get_rate(st->mclk); 118 119 if (!clk_freq || fout > (clk_freq / 2)) 120 return -EINVAL; 121 122 regval = ad9834_calc_freqreg(clk_freq, fout); 123 124 st->freq_data[0] = cpu_to_be16(addr | (regval & 125 RES_MASK(AD9834_FREQ_BITS / 2))); 126 st->freq_data[1] = cpu_to_be16(addr | ((regval >> 127 (AD9834_FREQ_BITS / 2)) & 128 RES_MASK(AD9834_FREQ_BITS / 2))); 129 130 return spi_sync(st->spi, &st->freq_msg); 131 } 132 133 static int ad9834_write_phase(struct ad9834_state *st, 134 unsigned long addr, unsigned long phase) 135 { 136 if (phase >= BIT(AD9834_PHASE_BITS)) 137 return -EINVAL; 138 st->data = cpu_to_be16(addr | phase); 139 140 return spi_sync(st->spi, &st->msg); 141 } 142 143 static ssize_t ad9834_write(struct device *dev, 144 struct device_attribute *attr, 145 const char *buf, 146 size_t len) 147 { 148 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 149 struct ad9834_state *st = iio_priv(indio_dev); 150 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 151 int ret; 152 unsigned long val; 153 154 ret = kstrtoul(buf, 10, &val); 155 if (ret) 156 return ret; 157 158 mutex_lock(&st->lock); 159 switch ((u32)this_attr->address) { 160 case AD9834_REG_FREQ0: 161 case AD9834_REG_FREQ1: 162 ret = ad9834_write_frequency(st, this_attr->address, val); 163 break; 164 case AD9834_REG_PHASE0: 165 case AD9834_REG_PHASE1: 166 ret = ad9834_write_phase(st, this_attr->address, val); 167 break; 168 case AD9834_OPBITEN: 169 if (st->control & AD9834_MODE) { 170 ret = -EINVAL; /* AD9834 reserved mode */ 171 break; 172 } 173 174 if (val) 175 st->control |= AD9834_OPBITEN; 176 else 177 st->control &= ~AD9834_OPBITEN; 178 179 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); 180 ret = spi_sync(st->spi, &st->msg); 181 break; 182 case AD9834_PIN_SW: 183 if (val) 184 st->control |= AD9834_PIN_SW; 185 else 186 st->control &= ~AD9834_PIN_SW; 187 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); 188 ret = spi_sync(st->spi, &st->msg); 189 break; 190 case AD9834_FSEL: 191 case AD9834_PSEL: 192 if (!val) { 193 st->control &= ~(this_attr->address | AD9834_PIN_SW); 194 } else if (val == 1) { 195 st->control |= this_attr->address; 196 st->control &= ~AD9834_PIN_SW; 197 } else { 198 ret = -EINVAL; 199 break; 200 } 201 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); 202 ret = spi_sync(st->spi, &st->msg); 203 break; 204 case AD9834_RESET: 205 if (val) 206 st->control &= ~AD9834_RESET; 207 else 208 st->control |= AD9834_RESET; 209 210 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); 211 ret = spi_sync(st->spi, &st->msg); 212 break; 213 default: 214 ret = -ENODEV; 215 } 216 mutex_unlock(&st->lock); 217 218 return ret ? ret : len; 219 } 220 221 static ssize_t ad9834_store_wavetype(struct device *dev, 222 struct device_attribute *attr, 223 const char *buf, 224 size_t len) 225 { 226 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 227 struct ad9834_state *st = iio_priv(indio_dev); 228 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 229 int ret = 0; 230 bool is_ad9833_7 = (st->devid == ID_AD9833) || (st->devid == ID_AD9837); 231 232 mutex_lock(&st->lock); 233 234 switch ((u32)this_attr->address) { 235 case 0: 236 if (sysfs_streq(buf, "sine")) { 237 st->control &= ~AD9834_MODE; 238 if (is_ad9833_7) 239 st->control &= ~AD9834_OPBITEN; 240 } else if (sysfs_streq(buf, "triangle")) { 241 if (is_ad9833_7) { 242 st->control &= ~AD9834_OPBITEN; 243 st->control |= AD9834_MODE; 244 } else if (st->control & AD9834_OPBITEN) { 245 ret = -EINVAL; /* AD9834 reserved mode */ 246 } else { 247 st->control |= AD9834_MODE; 248 } 249 } else if (is_ad9833_7 && sysfs_streq(buf, "square")) { 250 st->control &= ~AD9834_MODE; 251 st->control |= AD9834_OPBITEN; 252 } else { 253 ret = -EINVAL; 254 } 255 256 break; 257 case 1: 258 if (sysfs_streq(buf, "square") && 259 !(st->control & AD9834_MODE)) { 260 st->control &= ~AD9834_MODE; 261 st->control |= AD9834_OPBITEN; 262 } else { 263 ret = -EINVAL; 264 } 265 break; 266 default: 267 ret = -EINVAL; 268 break; 269 } 270 271 if (!ret) { 272 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); 273 ret = spi_sync(st->spi, &st->msg); 274 } 275 mutex_unlock(&st->lock); 276 277 return ret ? ret : len; 278 } 279 280 static 281 ssize_t ad9834_show_out0_wavetype_available(struct device *dev, 282 struct device_attribute *attr, 283 char *buf) 284 { 285 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 286 struct ad9834_state *st = iio_priv(indio_dev); 287 288 if (st->devid == ID_AD9833 || st->devid == ID_AD9837) 289 return sysfs_emit(buf, "sine triangle square\n"); 290 if (st->control & AD9834_OPBITEN) 291 return sysfs_emit(buf, "sine\n"); 292 return sysfs_emit(buf, "sine triangle\n"); 293 } 294 295 static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, 0444, 296 ad9834_show_out0_wavetype_available, NULL, 0); 297 298 static 299 ssize_t ad9834_show_out1_wavetype_available(struct device *dev, 300 struct device_attribute *attr, 301 char *buf) 302 { 303 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 304 struct ad9834_state *st = iio_priv(indio_dev); 305 306 if (st->control & AD9834_MODE) 307 return sysfs_emit(buf, "\n"); 308 return sysfs_emit(buf, "square\n"); 309 } 310 311 static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, 0444, 312 ad9834_show_out1_wavetype_available, NULL, 0); 313 314 /* 315 * see dds.h for further information 316 */ 317 318 static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9834_write, AD9834_REG_FREQ0); 319 static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9834_write, AD9834_REG_FREQ1); 320 static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9834_write, AD9834_FSEL); 321 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */ 322 323 static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9834_write, AD9834_REG_PHASE0); 324 static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9834_write, AD9834_REG_PHASE1); 325 static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL, ad9834_write, AD9834_PSEL); 326 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/ 327 328 static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL, ad9834_write, AD9834_PIN_SW); 329 static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL, ad9834_write, AD9834_RESET); 330 static IIO_DEV_ATTR_OUTY_ENABLE(0, 1, 0200, NULL, ad9834_write, AD9834_OPBITEN); 331 static IIO_DEV_ATTR_OUT_WAVETYPE(0, 0, ad9834_store_wavetype, 0); 332 static IIO_DEV_ATTR_OUT_WAVETYPE(0, 1, ad9834_store_wavetype, 1); 333 334 static struct attribute *ad9834_attributes[] = { 335 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr, 336 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr, 337 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr, 338 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr, 339 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr, 340 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr, 341 &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr, 342 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr, 343 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr, 344 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr, 345 &iio_dev_attr_out_altvoltage0_out1_enable.dev_attr.attr, 346 &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr, 347 &iio_dev_attr_out_altvoltage0_out1_wavetype.dev_attr.attr, 348 &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr, 349 &iio_dev_attr_out_altvoltage0_out1_wavetype_available.dev_attr.attr, 350 NULL, 351 }; 352 353 static struct attribute *ad9833_attributes[] = { 354 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr, 355 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr, 356 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr, 357 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr, 358 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr, 359 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr, 360 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr, 361 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr, 362 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr, 363 &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr, 364 &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr, 365 NULL, 366 }; 367 368 static const struct attribute_group ad9834_attribute_group = { 369 .attrs = ad9834_attributes, 370 }; 371 372 static const struct attribute_group ad9833_attribute_group = { 373 .attrs = ad9833_attributes, 374 }; 375 376 static const struct iio_info ad9834_info = { 377 .attrs = &ad9834_attribute_group, 378 }; 379 380 static const struct iio_info ad9833_info = { 381 .attrs = &ad9833_attribute_group, 382 }; 383 384 static int ad9834_probe(struct spi_device *spi) 385 { 386 struct ad9834_state *st; 387 struct iio_dev *indio_dev; 388 int ret; 389 390 ret = devm_regulator_get_enable(&spi->dev, "avdd"); 391 if (ret) 392 return dev_err_probe(&spi->dev, ret, "Failed to enable specified AVDD supply\n"); 393 394 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 395 if (!indio_dev) 396 return -ENOMEM; 397 st = iio_priv(indio_dev); 398 mutex_init(&st->lock); 399 st->mclk = devm_clk_get_enabled(&spi->dev, NULL); 400 if (IS_ERR(st->mclk)) 401 return dev_err_probe(&spi->dev, PTR_ERR(st->mclk), 402 "Failed to enable master clock\n"); 403 404 st->spi = spi; 405 st->devid = spi_get_device_id(spi)->driver_data; 406 indio_dev->name = spi_get_device_id(spi)->name; 407 switch (st->devid) { 408 case ID_AD9833: 409 case ID_AD9837: 410 indio_dev->info = &ad9833_info; 411 break; 412 default: 413 indio_dev->info = &ad9834_info; 414 break; 415 } 416 indio_dev->modes = INDIO_DIRECT_MODE; 417 418 /* Setup default messages */ 419 420 st->xfer.tx_buf = &st->data; 421 st->xfer.len = 2; 422 423 spi_message_init(&st->msg); 424 spi_message_add_tail(&st->xfer, &st->msg); 425 426 st->freq_xfer[0].tx_buf = &st->freq_data[0]; 427 st->freq_xfer[0].len = 2; 428 st->freq_xfer[0].cs_change = 1; 429 st->freq_xfer[1].tx_buf = &st->freq_data[1]; 430 st->freq_xfer[1].len = 2; 431 432 spi_message_init(&st->freq_msg); 433 spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg); 434 spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg); 435 436 st->control = AD9834_B28 | AD9834_RESET; 437 st->control |= AD9834_DIV2; 438 439 if (st->devid == ID_AD9834) 440 st->control |= AD9834_SIGN_PIB; 441 442 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); 443 ret = spi_sync(st->spi, &st->msg); 444 if (ret) 445 return dev_err_probe(&spi->dev, ret, 446 "device init failed\n"); 447 448 ret = ad9834_write_frequency(st, AD9834_REG_FREQ0, 1000000); 449 if (ret) 450 return ret; 451 452 ret = ad9834_write_frequency(st, AD9834_REG_FREQ1, 5000000); 453 if (ret) 454 return ret; 455 456 ret = ad9834_write_phase(st, AD9834_REG_PHASE0, 512); 457 if (ret) 458 return ret; 459 460 ret = ad9834_write_phase(st, AD9834_REG_PHASE1, 1024); 461 if (ret) 462 return ret; 463 464 return devm_iio_device_register(&spi->dev, indio_dev); 465 } 466 467 static const struct spi_device_id ad9834_id[] = { 468 {"ad9833", ID_AD9833}, 469 {"ad9834", ID_AD9834}, 470 {"ad9837", ID_AD9837}, 471 {"ad9838", ID_AD9838}, 472 { } 473 }; 474 MODULE_DEVICE_TABLE(spi, ad9834_id); 475 476 static const struct of_device_id ad9834_of_match[] = { 477 {.compatible = "adi,ad9833"}, 478 {.compatible = "adi,ad9834"}, 479 {.compatible = "adi,ad9837"}, 480 {.compatible = "adi,ad9838"}, 481 { } 482 }; 483 484 MODULE_DEVICE_TABLE(of, ad9834_of_match); 485 486 static struct spi_driver ad9834_driver = { 487 .driver = { 488 .name = "ad9834", 489 .of_match_table = ad9834_of_match 490 }, 491 .probe = ad9834_probe, 492 .id_table = ad9834_id, 493 }; 494 module_spi_driver(ad9834_driver); 495 496 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 497 MODULE_DESCRIPTION("Analog Devices AD9833/AD9834/AD9837/AD9838 DDS"); 498 MODULE_LICENSE("GPL v2"); 499