1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AD7785/AD7792/AD7793/AD7794/AD7795 SPI ADC driver 4 * 5 * Copyright 2011-2012 Analog Devices Inc. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/device.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/sysfs.h> 13 #include <linux/spi/spi.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/err.h> 16 #include <linux/sched.h> 17 #include <linux/delay.h> 18 #include <linux/module.h> 19 20 #include <linux/iio/iio.h> 21 #include <linux/iio/sysfs.h> 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/trigger.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 #include <linux/iio/adc/ad_sigma_delta.h> 27 #include <linux/platform_data/ad7793.h> 28 29 /* Registers */ 30 #define AD7793_REG_COMM 0 /* Communications Register (WO, 8-bit) */ 31 #define AD7793_REG_STAT 0 /* Status Register (RO, 8-bit) */ 32 #define AD7793_REG_MODE 1 /* Mode Register (RW, 16-bit */ 33 #define AD7793_REG_CONF 2 /* Configuration Register (RW, 16-bit) */ 34 #define AD7793_REG_DATA 3 /* Data Register (RO, 16-/24-bit) */ 35 #define AD7793_REG_ID 4 /* ID Register (RO, 8-bit) */ 36 #define AD7793_REG_IO 5 /* IO Register (RO, 8-bit) */ 37 #define AD7793_REG_OFFSET 6 /* Offset Register (RW, 16-bit 38 * (AD7792)/24-bit (AD7793)) */ 39 #define AD7793_REG_FULLSALE 7 /* Full-Scale Register 40 * (RW, 16-bit (AD7792)/24-bit (AD7793)) */ 41 42 /* Communications Register Bit Designations (AD7793_REG_COMM) */ 43 #define AD7793_COMM_WEN (1 << 7) /* Write Enable */ 44 #define AD7793_COMM_WRITE (0 << 6) /* Write Operation */ 45 #define AD7793_COMM_READ (1 << 6) /* Read Operation */ 46 #define AD7793_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ 47 #define AD7793_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */ 48 49 /* Status Register Bit Designations (AD7793_REG_STAT) */ 50 #define AD7793_STAT_RDY (1 << 7) /* Ready */ 51 #define AD7793_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */ 52 #define AD7793_STAT_CH3 (1 << 2) /* Channel 3 */ 53 #define AD7793_STAT_CH2 (1 << 1) /* Channel 2 */ 54 #define AD7793_STAT_CH1 (1 << 0) /* Channel 1 */ 55 56 /* Mode Register Bit Designations (AD7793_REG_MODE) */ 57 #define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */ 58 #define AD7793_MODE_SEL_MASK (0x7 << 13) /* Operation Mode Select mask */ 59 #define AD7793_MODE_CLKSRC(x) (((x) & 0x3) << 6) /* ADC Clock Source Select */ 60 #define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */ 61 62 #define AD7793_MODE_CONT 0 /* Continuous Conversion Mode */ 63 #define AD7793_MODE_SINGLE 1 /* Single Conversion Mode */ 64 #define AD7793_MODE_IDLE 2 /* Idle Mode */ 65 #define AD7793_MODE_PWRDN 3 /* Power-Down Mode */ 66 #define AD7793_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ 67 #define AD7793_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ 68 #define AD7793_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ 69 #define AD7793_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ 70 71 #define AD7793_CLK_INT 0 /* Internal 64 kHz Clock not 72 * available at the CLK pin */ 73 #define AD7793_CLK_INT_CO 1 /* Internal 64 kHz Clock available 74 * at the CLK pin */ 75 #define AD7793_CLK_EXT 2 /* External 64 kHz Clock */ 76 #define AD7793_CLK_EXT_DIV2 3 /* External Clock divided by 2 */ 77 78 /* Configuration Register Bit Designations (AD7793_REG_CONF) */ 79 #define AD7793_CONF_VBIAS(x) (((x) & 0x3) << 14) /* Bias Voltage 80 * Generator Enable */ 81 #define AD7793_CONF_BO_EN (1 << 13) /* Burnout Current Enable */ 82 #define AD7793_CONF_UNIPOLAR (1 << 12) /* Unipolar/Bipolar Enable */ 83 #define AD7793_CONF_BOOST (1 << 11) /* Boost Enable */ 84 #define AD7793_CONF_GAIN(x) (((x) & 0x7) << 8) /* Gain Select */ 85 #define AD7793_CONF_REFSEL(x) ((x) << 6) /* INT/EXT Reference Select */ 86 #define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */ 87 #define AD7793_CONF_CHAN(x) ((x) & 0xf) /* Channel select */ 88 #define AD7793_CONF_CHAN_MASK 0xf /* Channel select mask */ 89 90 #define AD7793_CH_AIN1P_AIN1M 0 /* AIN1(+) - AIN1(-) */ 91 #define AD7793_CH_AIN2P_AIN2M 1 /* AIN2(+) - AIN2(-) */ 92 #define AD7793_CH_AIN3P_AIN3M 2 /* AIN3(+) - AIN3(-) */ 93 #define AD7793_CH_AIN1M_AIN1M 3 /* AIN1(-) - AIN1(-) */ 94 #define AD7793_CH_TEMP 6 /* Temp Sensor */ 95 #define AD7793_CH_AVDD_MONITOR 7 /* AVDD Monitor */ 96 97 #define AD7795_CH_AIN4P_AIN4M 4 /* AIN4(+) - AIN4(-) */ 98 #define AD7795_CH_AIN5P_AIN5M 5 /* AIN5(+) - AIN5(-) */ 99 #define AD7795_CH_AIN6P_AIN6M 6 /* AIN6(+) - AIN6(-) */ 100 #define AD7795_CH_AIN1M_AIN1M 8 /* AIN1(-) - AIN1(-) */ 101 102 /* ID Register Bit Designations (AD7793_REG_ID) */ 103 #define AD7785_ID 0x3 104 #define AD7792_ID 0xA 105 #define AD7793_ID 0xB 106 #define AD7794_ID 0xF 107 #define AD7795_ID 0xF 108 #define AD7796_ID 0xA 109 #define AD7797_ID 0xB 110 #define AD7798_ID 0x8 111 #define AD7799_ID 0x9 112 #define AD7793_ID_MASK 0xF 113 114 /* IO (Excitation Current Sources) Register Bit Designations (AD7793_REG_IO) */ 115 #define AD7793_IO_IEXC1_IOUT1_IEXC2_IOUT2 0 /* IEXC1 connect to IOUT1, 116 * IEXC2 connect to IOUT2 */ 117 #define AD7793_IO_IEXC1_IOUT2_IEXC2_IOUT1 1 /* IEXC1 connect to IOUT2, 118 * IEXC2 connect to IOUT1 */ 119 #define AD7793_IO_IEXC1_IEXC2_IOUT1 2 /* Both current sources 120 * IEXC1,2 connect to IOUT1 */ 121 #define AD7793_IO_IEXC1_IEXC2_IOUT2 3 /* Both current sources 122 * IEXC1,2 connect to IOUT2 */ 123 124 #define AD7793_IO_IXCEN_10uA (1 << 0) /* Excitation Current 10uA */ 125 #define AD7793_IO_IXCEN_210uA (2 << 0) /* Excitation Current 210uA */ 126 #define AD7793_IO_IXCEN_1mA (3 << 0) /* Excitation Current 1mA */ 127 128 /* NOTE: 129 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output. 130 * In order to avoid contentions on the SPI bus, it's therefore necessary 131 * to use spi bus locking. 132 * 133 * The DOUT/RDY output must also be wired to an interrupt capable GPIO. 134 */ 135 136 #define AD7793_FLAG_HAS_CLKSEL BIT(0) 137 #define AD7793_FLAG_HAS_REFSEL BIT(1) 138 #define AD7793_FLAG_HAS_VBIAS BIT(2) 139 #define AD7793_HAS_EXITATION_CURRENT BIT(3) 140 #define AD7793_FLAG_HAS_GAIN BIT(4) 141 #define AD7793_FLAG_HAS_BUFFER BIT(5) 142 143 struct ad7793_chip_info { 144 unsigned int id; 145 const struct iio_chan_spec *channels; 146 unsigned int num_channels; 147 unsigned int flags; 148 149 const struct iio_info *iio_info; 150 const u16 *sample_freq_avail; 151 }; 152 153 struct ad7793_state { 154 const struct ad7793_chip_info *chip_info; 155 u16 mode; 156 u16 conf; 157 u32 scale_avail[8][2]; 158 159 struct ad_sigma_delta sd; 160 161 }; 162 163 enum ad7793_supported_device_ids { 164 ID_AD7785, 165 ID_AD7792, 166 ID_AD7793, 167 ID_AD7794, 168 ID_AD7795, 169 ID_AD7796, 170 ID_AD7797, 171 ID_AD7798, 172 ID_AD7799, 173 }; 174 175 static struct ad7793_state *ad_sigma_delta_to_ad7793(struct ad_sigma_delta *sd) 176 { 177 return container_of(sd, struct ad7793_state, sd); 178 } 179 180 static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 181 { 182 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd); 183 184 st->conf &= ~AD7793_CONF_CHAN_MASK; 185 st->conf |= AD7793_CONF_CHAN(channel); 186 187 return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf); 188 } 189 190 static int ad7793_set_mode(struct ad_sigma_delta *sd, 191 enum ad_sigma_delta_mode mode) 192 { 193 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd); 194 195 st->mode &= ~AD7793_MODE_SEL_MASK; 196 st->mode |= AD7793_MODE_SEL(mode); 197 198 return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode); 199 } 200 201 static const struct ad_sigma_delta_info ad7793_sigma_delta_info = { 202 .set_channel = ad7793_set_channel, 203 .set_mode = ad7793_set_mode, 204 .has_registers = true, 205 .addr_shift = 3, 206 .read_mask = BIT(6), 207 .irq_flags = IRQF_TRIGGER_FALLING, 208 .num_resetclks = 32, 209 }; 210 211 static const struct ad_sd_calib_data ad7793_calib_arr[6] = { 212 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M}, 213 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M}, 214 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M}, 215 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M}, 216 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M}, 217 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M} 218 }; 219 220 static int ad7793_calibrate_all(struct ad7793_state *st) 221 { 222 return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr, 223 ARRAY_SIZE(ad7793_calib_arr)); 224 } 225 226 static int ad7793_check_platform_data(struct ad7793_state *st, 227 const struct ad7793_platform_data *pdata) 228 { 229 if ((pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT1 || 230 pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT2) && 231 ((pdata->exitation_current != AD7793_IX_10uA) && 232 (pdata->exitation_current != AD7793_IX_210uA))) 233 return -EINVAL; 234 235 if (!(st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL) && 236 pdata->clock_src != AD7793_CLK_SRC_INT) 237 return -EINVAL; 238 239 if (!(st->chip_info->flags & AD7793_FLAG_HAS_REFSEL) && 240 pdata->refsel != AD7793_REFSEL_REFIN1) 241 return -EINVAL; 242 243 if (!(st->chip_info->flags & AD7793_FLAG_HAS_VBIAS) && 244 pdata->bias_voltage != AD7793_BIAS_VOLTAGE_DISABLED) 245 return -EINVAL; 246 247 if (!(st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) && 248 pdata->exitation_current != AD7793_IX_DISABLED) 249 return -EINVAL; 250 251 return 0; 252 } 253 254 static int ad7793_setup(struct iio_dev *indio_dev, 255 const struct ad7793_platform_data *pdata, 256 unsigned int vref_mv) 257 { 258 struct ad7793_state *st = iio_priv(indio_dev); 259 int i, ret; 260 unsigned long long scale_uv; 261 u32 id; 262 263 ret = ad7793_check_platform_data(st, pdata); 264 if (ret) 265 return ret; 266 267 /* reset the serial interface */ 268 ret = ad_sd_reset(&st->sd); 269 if (ret < 0) 270 goto out; 271 272 /* 273 * Per AD7792/AD7793 datasheet (Rev. B, page 25, RESET section), 274 * allow 500 us after a reset before accessing on-chip registers. 275 */ 276 fsleep(500); 277 278 /* write/read test for device presence */ 279 ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id); 280 if (ret) 281 goto out; 282 283 id &= AD7793_ID_MASK; 284 285 if (id != st->chip_info->id) { 286 ret = dev_err_probe(&st->sd.spi->dev, -ENODEV, 287 "device ID query failed\n"); 288 goto out; 289 } 290 291 st->mode = AD7793_MODE_RATE(1); 292 st->conf = 0; 293 294 if (st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL) 295 st->mode |= AD7793_MODE_CLKSRC(pdata->clock_src); 296 if (st->chip_info->flags & AD7793_FLAG_HAS_REFSEL) 297 st->conf |= AD7793_CONF_REFSEL(pdata->refsel); 298 if (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS) 299 st->conf |= AD7793_CONF_VBIAS(pdata->bias_voltage); 300 if (pdata->buffered || !(st->chip_info->flags & AD7793_FLAG_HAS_BUFFER)) 301 st->conf |= AD7793_CONF_BUF; 302 if (pdata->boost_enable && 303 (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS)) 304 st->conf |= AD7793_CONF_BOOST; 305 if (pdata->burnout_current) 306 st->conf |= AD7793_CONF_BO_EN; 307 if (pdata->unipolar) 308 st->conf |= AD7793_CONF_UNIPOLAR; 309 310 if (!(st->chip_info->flags & AD7793_FLAG_HAS_GAIN)) 311 st->conf |= AD7793_CONF_GAIN(7); 312 313 ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE); 314 if (ret) 315 goto out; 316 317 ret = ad7793_set_channel(&st->sd, 0); 318 if (ret) 319 goto out; 320 321 if (st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) { 322 ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO, 1, 323 pdata->exitation_current | 324 (pdata->current_source_direction << 2)); 325 if (ret) 326 goto out; 327 } 328 329 ret = ad7793_calibrate_all(st); 330 if (ret) 331 goto out; 332 333 /* Populate available ADC input ranges */ 334 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 335 scale_uv = ((u64)vref_mv * 100000000) 336 >> (st->chip_info->channels[0].scan_type.realbits - 337 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1)); 338 scale_uv >>= i; 339 340 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 341 st->scale_avail[i][0] = scale_uv; 342 } 343 344 return 0; 345 out: 346 return dev_err_probe(&st->sd.spi->dev, ret, "setup failed\n"); 347 } 348 349 static const u16 ad7793_sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 350 33, 19, 17, 16, 12, 10, 8, 6, 4}; 351 352 static const u16 ad7797_sample_freq_avail[16] = {0, 0, 0, 123, 62, 50, 0, 353 33, 0, 17, 16, 12, 10, 8, 6, 4}; 354 355 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 356 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4"); 357 358 static IIO_CONST_ATTR_NAMED(sampling_frequency_available_ad7797, 359 sampling_frequency_available, "123 62 50 33 17 16 12 10 8 6 4"); 360 361 static int ad7793_read_avail(struct iio_dev *indio_dev, 362 struct iio_chan_spec const *chan, 363 const int **vals, int *type, int *length, 364 long mask) 365 { 366 struct ad7793_state *st = iio_priv(indio_dev); 367 368 switch (mask) { 369 case IIO_CHAN_INFO_SCALE: 370 *vals = (int *)st->scale_avail; 371 *type = IIO_VAL_INT_PLUS_NANO; 372 /* Values are stored in a 2D matrix */ 373 *length = ARRAY_SIZE(st->scale_avail) * 2; 374 375 return IIO_AVAIL_LIST; 376 default: 377 return -EINVAL; 378 } 379 } 380 381 static struct attribute *ad7793_attributes[] = { 382 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 383 NULL 384 }; 385 386 static const struct attribute_group ad7793_attribute_group = { 387 .attrs = ad7793_attributes, 388 }; 389 390 static struct attribute *ad7797_attributes[] = { 391 &iio_const_attr_sampling_frequency_available_ad7797.dev_attr.attr, 392 NULL 393 }; 394 395 static const struct attribute_group ad7797_attribute_group = { 396 .attrs = ad7797_attributes, 397 }; 398 399 static int ad7793_read_raw(struct iio_dev *indio_dev, 400 struct iio_chan_spec const *chan, 401 int *val, 402 int *val2, 403 long m) 404 { 405 struct ad7793_state *st = iio_priv(indio_dev); 406 int ret; 407 unsigned long long scale_uv; 408 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR); 409 410 switch (m) { 411 case IIO_CHAN_INFO_RAW: 412 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 413 if (ret < 0) 414 return ret; 415 416 return IIO_VAL_INT; 417 418 case IIO_CHAN_INFO_SCALE: 419 switch (chan->type) { 420 case IIO_VOLTAGE: 421 if (chan->differential) { 422 *val = st-> 423 scale_avail[(st->conf >> 8) & 0x7][0]; 424 *val2 = st-> 425 scale_avail[(st->conf >> 8) & 0x7][1]; 426 return IIO_VAL_INT_PLUS_NANO; 427 } 428 /* 1170mV / 2^23 * 6 */ 429 scale_uv = (1170ULL * 1000000000ULL * 6ULL); 430 break; 431 case IIO_TEMP: 432 /* 1170mV / 0.81 mV/C / 2^23 */ 433 scale_uv = 1444444444444444ULL; 434 break; 435 default: 436 return -EINVAL; 437 } 438 439 scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1)); 440 *val = 0; 441 *val2 = scale_uv; 442 return IIO_VAL_INT_PLUS_NANO; 443 case IIO_CHAN_INFO_OFFSET: 444 if (!unipolar) 445 *val = -(1 << (chan->scan_type.realbits - 1)); 446 else 447 *val = 0; 448 449 /* Kelvin to Celsius */ 450 if (chan->type == IIO_TEMP) { 451 unsigned long long offset; 452 unsigned int shift; 453 454 shift = chan->scan_type.realbits - (unipolar ? 0 : 1); 455 offset = 273ULL << shift; 456 do_div(offset, 1444); 457 *val -= offset; 458 } 459 return IIO_VAL_INT; 460 case IIO_CHAN_INFO_SAMP_FREQ: 461 *val = st->chip_info 462 ->sample_freq_avail[AD7793_MODE_RATE(st->mode)]; 463 return IIO_VAL_INT; 464 } 465 return -EINVAL; 466 } 467 468 static int __ad7793_write_raw(struct iio_dev *indio_dev, 469 struct iio_chan_spec const *chan, 470 int val, int val2, long mask) 471 { 472 struct ad7793_state *st = iio_priv(indio_dev); 473 int i; 474 unsigned int tmp; 475 476 switch (mask) { 477 case IIO_CHAN_INFO_SCALE: 478 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 479 if (val2 != st->scale_avail[i][1]) 480 continue; 481 482 tmp = st->conf; 483 st->conf &= ~AD7793_CONF_GAIN(-1); 484 st->conf |= AD7793_CONF_GAIN(i); 485 486 if (tmp == st->conf) 487 return 0; 488 489 ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 490 sizeof(st->conf), st->conf); 491 ad7793_calibrate_all(st); 492 493 return 0; 494 } 495 return -EINVAL; 496 case IIO_CHAN_INFO_SAMP_FREQ: 497 if (!val) 498 return -EINVAL; 499 500 for (i = 0; i < 16; i++) 501 if (val == st->chip_info->sample_freq_avail[i]) 502 break; 503 504 if (i == 16) 505 return -EINVAL; 506 507 st->mode &= ~AD7793_MODE_RATE(-1); 508 st->mode |= AD7793_MODE_RATE(i); 509 ad_sd_write_reg(&st->sd, AD7793_REG_MODE, sizeof(st->mode), 510 st->mode); 511 return 0; 512 default: 513 return -EINVAL; 514 } 515 } 516 517 static int ad7793_write_raw(struct iio_dev *indio_dev, 518 struct iio_chan_spec const *chan, 519 int val, int val2, long mask) 520 { 521 int ret; 522 523 if (!iio_device_claim_direct(indio_dev)) 524 return -EBUSY; 525 526 ret = __ad7793_write_raw(indio_dev, chan, val, val2, mask); 527 528 iio_device_release_direct(indio_dev); 529 530 return ret; 531 } 532 533 static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev, 534 struct iio_chan_spec const *chan, 535 long mask) 536 { 537 return IIO_VAL_INT_PLUS_NANO; 538 } 539 540 static const struct iio_info ad7793_info = { 541 .read_raw = &ad7793_read_raw, 542 .write_raw = &ad7793_write_raw, 543 .write_raw_get_fmt = &ad7793_write_raw_get_fmt, 544 .read_avail = ad7793_read_avail, 545 .attrs = &ad7793_attribute_group, 546 .validate_trigger = ad_sd_validate_trigger, 547 }; 548 549 static const struct iio_info ad7797_info = { 550 .read_raw = &ad7793_read_raw, 551 .write_raw = &ad7793_write_raw, 552 .write_raw_get_fmt = &ad7793_write_raw_get_fmt, 553 .attrs = &ad7797_attribute_group, 554 .validate_trigger = ad_sd_validate_trigger, 555 }; 556 557 #define __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ 558 _storagebits, _shift, _extend_name, _type, _mask_type_av, _mask_all) \ 559 { \ 560 .type = (_type), \ 561 .differential = (_channel2 == -1 ? 0 : 1), \ 562 .indexed = 1, \ 563 .channel = (_channel1), \ 564 .channel2 = (_channel2), \ 565 .address = (_address), \ 566 .extend_name = (_extend_name), \ 567 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 568 BIT(IIO_CHAN_INFO_OFFSET), \ 569 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 570 .info_mask_shared_by_type_available = (_mask_type_av), \ 571 .info_mask_shared_by_all = _mask_all, \ 572 .scan_index = (_si), \ 573 .scan_type = { \ 574 .sign = 'u', \ 575 .realbits = (_bits), \ 576 .storagebits = (_storagebits), \ 577 .shift = (_shift), \ 578 .endianness = IIO_BE, \ 579 }, \ 580 } 581 582 #define AD7793_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ 583 _storagebits, _shift) \ 584 __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ 585 _storagebits, _shift, NULL, IIO_VOLTAGE, \ 586 BIT(IIO_CHAN_INFO_SCALE), \ 587 BIT(IIO_CHAN_INFO_SAMP_FREQ)) 588 589 #define AD7793_SHORTED_CHANNEL(_si, _channel, _address, _bits, \ 590 _storagebits, _shift) \ 591 __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \ 592 _storagebits, _shift, "shorted", IIO_VOLTAGE, \ 593 BIT(IIO_CHAN_INFO_SCALE), \ 594 BIT(IIO_CHAN_INFO_SAMP_FREQ)) 595 596 #define AD7793_TEMP_CHANNEL(_si, _address, _bits, _storagebits, _shift) \ 597 __AD7793_CHANNEL(_si, 0, -1, _address, _bits, \ 598 _storagebits, _shift, NULL, IIO_TEMP, \ 599 0, \ 600 BIT(IIO_CHAN_INFO_SAMP_FREQ)) 601 602 #define AD7793_SUPPLY_CHANNEL(_si, _channel, _address, _bits, _storagebits, \ 603 _shift) \ 604 __AD7793_CHANNEL(_si, _channel, -1, _address, _bits, \ 605 _storagebits, _shift, "supply", IIO_VOLTAGE, \ 606 0, \ 607 BIT(IIO_CHAN_INFO_SAMP_FREQ)) 608 609 #define AD7797_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ 610 _storagebits, _shift) \ 611 __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \ 612 _storagebits, _shift, NULL, IIO_VOLTAGE, \ 613 0, \ 614 BIT(IIO_CHAN_INFO_SAMP_FREQ)) 615 616 #define AD7797_SHORTED_CHANNEL(_si, _channel, _address, _bits, \ 617 _storagebits, _shift) \ 618 __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \ 619 _storagebits, _shift, "shorted", IIO_VOLTAGE, \ 620 0, \ 621 BIT(IIO_CHAN_INFO_SAMP_FREQ)) 622 623 #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \ 624 const struct iio_chan_spec _name##_channels[] = { \ 625 AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \ 626 AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \ 627 AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \ 628 AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \ 629 AD7793_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \ 630 AD7793_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \ 631 IIO_CHAN_SOFT_TIMESTAMP(6), \ 632 } 633 634 #define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \ 635 const struct iio_chan_spec _name##_channels[] = { \ 636 AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ 637 AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \ 638 AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \ 639 AD7793_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \ 640 AD7793_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \ 641 AD7793_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \ 642 AD7793_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ 643 AD7793_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \ 644 AD7793_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ 645 IIO_CHAN_SOFT_TIMESTAMP(9), \ 646 } 647 648 #define DECLARE_AD7797_CHANNELS(_name, _b, _sb) \ 649 const struct iio_chan_spec _name##_channels[] = { \ 650 AD7797_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ 651 AD7797_SHORTED_CHANNEL(1, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ 652 AD7793_TEMP_CHANNEL(2, AD7793_CH_TEMP, (_b), (_sb), 0), \ 653 AD7793_SUPPLY_CHANNEL(3, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ 654 IIO_CHAN_SOFT_TIMESTAMP(4), \ 655 } 656 657 #define DECLARE_AD7799_CHANNELS(_name, _b, _sb) \ 658 const struct iio_chan_spec _name##_channels[] = { \ 659 AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ 660 AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \ 661 AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \ 662 AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ 663 AD7793_SUPPLY_CHANNEL(4, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ 664 IIO_CHAN_SOFT_TIMESTAMP(5), \ 665 } 666 667 static DECLARE_AD7793_CHANNELS(ad7785, 20, 32, 4); 668 static DECLARE_AD7793_CHANNELS(ad7792, 16, 32, 0); 669 static DECLARE_AD7793_CHANNELS(ad7793, 24, 32, 0); 670 static DECLARE_AD7795_CHANNELS(ad7794, 16, 32); 671 static DECLARE_AD7795_CHANNELS(ad7795, 24, 32); 672 static DECLARE_AD7797_CHANNELS(ad7796, 16, 16); 673 static DECLARE_AD7797_CHANNELS(ad7797, 24, 32); 674 static DECLARE_AD7799_CHANNELS(ad7798, 16, 16); 675 static DECLARE_AD7799_CHANNELS(ad7799, 24, 32); 676 677 static const struct ad7793_chip_info ad7793_chip_info_tbl[] = { 678 [ID_AD7785] = { 679 .id = AD7785_ID, 680 .channels = ad7785_channels, 681 .num_channels = ARRAY_SIZE(ad7785_channels), 682 .iio_info = &ad7793_info, 683 .sample_freq_avail = ad7793_sample_freq_avail, 684 .flags = AD7793_FLAG_HAS_CLKSEL | 685 AD7793_FLAG_HAS_REFSEL | 686 AD7793_FLAG_HAS_VBIAS | 687 AD7793_HAS_EXITATION_CURRENT | 688 AD7793_FLAG_HAS_GAIN | 689 AD7793_FLAG_HAS_BUFFER, 690 }, 691 [ID_AD7792] = { 692 .id = AD7792_ID, 693 .channels = ad7792_channels, 694 .num_channels = ARRAY_SIZE(ad7792_channels), 695 .iio_info = &ad7793_info, 696 .sample_freq_avail = ad7793_sample_freq_avail, 697 .flags = AD7793_FLAG_HAS_CLKSEL | 698 AD7793_FLAG_HAS_REFSEL | 699 AD7793_FLAG_HAS_VBIAS | 700 AD7793_HAS_EXITATION_CURRENT | 701 AD7793_FLAG_HAS_GAIN | 702 AD7793_FLAG_HAS_BUFFER, 703 }, 704 [ID_AD7793] = { 705 .id = AD7793_ID, 706 .channels = ad7793_channels, 707 .num_channels = ARRAY_SIZE(ad7793_channels), 708 .iio_info = &ad7793_info, 709 .sample_freq_avail = ad7793_sample_freq_avail, 710 .flags = AD7793_FLAG_HAS_CLKSEL | 711 AD7793_FLAG_HAS_REFSEL | 712 AD7793_FLAG_HAS_VBIAS | 713 AD7793_HAS_EXITATION_CURRENT | 714 AD7793_FLAG_HAS_GAIN | 715 AD7793_FLAG_HAS_BUFFER, 716 }, 717 [ID_AD7794] = { 718 .id = AD7794_ID, 719 .channels = ad7794_channels, 720 .num_channels = ARRAY_SIZE(ad7794_channels), 721 .iio_info = &ad7793_info, 722 .sample_freq_avail = ad7793_sample_freq_avail, 723 .flags = AD7793_FLAG_HAS_CLKSEL | 724 AD7793_FLAG_HAS_REFSEL | 725 AD7793_FLAG_HAS_VBIAS | 726 AD7793_HAS_EXITATION_CURRENT | 727 AD7793_FLAG_HAS_GAIN | 728 AD7793_FLAG_HAS_BUFFER, 729 }, 730 [ID_AD7795] = { 731 .id = AD7795_ID, 732 .channels = ad7795_channels, 733 .num_channels = ARRAY_SIZE(ad7795_channels), 734 .iio_info = &ad7793_info, 735 .sample_freq_avail = ad7793_sample_freq_avail, 736 .flags = AD7793_FLAG_HAS_CLKSEL | 737 AD7793_FLAG_HAS_REFSEL | 738 AD7793_FLAG_HAS_VBIAS | 739 AD7793_HAS_EXITATION_CURRENT | 740 AD7793_FLAG_HAS_GAIN | 741 AD7793_FLAG_HAS_BUFFER, 742 }, 743 [ID_AD7796] = { 744 .id = AD7796_ID, 745 .channels = ad7796_channels, 746 .num_channels = ARRAY_SIZE(ad7796_channels), 747 .iio_info = &ad7797_info, 748 .sample_freq_avail = ad7797_sample_freq_avail, 749 .flags = AD7793_FLAG_HAS_CLKSEL, 750 }, 751 [ID_AD7797] = { 752 .id = AD7797_ID, 753 .channels = ad7797_channels, 754 .num_channels = ARRAY_SIZE(ad7797_channels), 755 .iio_info = &ad7797_info, 756 .sample_freq_avail = ad7797_sample_freq_avail, 757 .flags = AD7793_FLAG_HAS_CLKSEL, 758 }, 759 [ID_AD7798] = { 760 .id = AD7798_ID, 761 .channels = ad7798_channels, 762 .num_channels = ARRAY_SIZE(ad7798_channels), 763 .iio_info = &ad7793_info, 764 .sample_freq_avail = ad7793_sample_freq_avail, 765 .flags = AD7793_FLAG_HAS_GAIN | 766 AD7793_FLAG_HAS_BUFFER, 767 }, 768 [ID_AD7799] = { 769 .id = AD7799_ID, 770 .channels = ad7799_channels, 771 .num_channels = ARRAY_SIZE(ad7799_channels), 772 .iio_info = &ad7793_info, 773 .sample_freq_avail = ad7793_sample_freq_avail, 774 .flags = AD7793_FLAG_HAS_GAIN | 775 AD7793_FLAG_HAS_BUFFER, 776 }, 777 }; 778 779 static int ad7793_probe(struct spi_device *spi) 780 { 781 struct device *dev = &spi->dev; 782 const struct ad7793_platform_data *pdata = dev_get_platdata(dev); 783 struct ad7793_state *st; 784 struct iio_dev *indio_dev; 785 int ret, vref_mv = 0; 786 787 if (!pdata) 788 return dev_err_probe(dev, -ENODEV, "no platform data?\n"); 789 790 if (!spi->irq) 791 return dev_err_probe(dev, -ENODEV, "no IRQ?\n"); 792 793 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 794 if (indio_dev == NULL) 795 return -ENOMEM; 796 797 st = iio_priv(indio_dev); 798 799 ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info); 800 801 if (pdata->refsel != AD7793_REFSEL_INTERNAL) { 802 ret = devm_regulator_get_enable_read_voltage(dev, "refin"); 803 if (ret < 0) 804 return ret; 805 806 vref_mv = ret / 1000; 807 } else { 808 vref_mv = 1170; /* Built-in ref */ 809 } 810 811 st->chip_info = 812 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data]; 813 814 indio_dev->name = spi_get_device_id(spi)->name; 815 indio_dev->modes = INDIO_DIRECT_MODE; 816 indio_dev->channels = st->chip_info->channels; 817 indio_dev->num_channels = st->chip_info->num_channels; 818 indio_dev->info = st->chip_info->iio_info; 819 820 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 821 if (ret) 822 return ret; 823 824 ret = ad7793_setup(indio_dev, pdata, vref_mv); 825 if (ret) 826 return ret; 827 828 return devm_iio_device_register(dev, indio_dev); 829 } 830 831 static const struct spi_device_id ad7793_id[] = { 832 { "ad7785", ID_AD7785 }, 833 { "ad7792", ID_AD7792 }, 834 { "ad7793", ID_AD7793 }, 835 { "ad7794", ID_AD7794 }, 836 { "ad7795", ID_AD7795 }, 837 { "ad7796", ID_AD7796 }, 838 { "ad7797", ID_AD7797 }, 839 { "ad7798", ID_AD7798 }, 840 { "ad7799", ID_AD7799 }, 841 { } 842 }; 843 MODULE_DEVICE_TABLE(spi, ad7793_id); 844 845 static struct spi_driver ad7793_driver = { 846 .driver = { 847 .name = "ad7793", 848 }, 849 .probe = ad7793_probe, 850 .id_table = ad7793_id, 851 }; 852 module_spi_driver(ad7793_driver); 853 854 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 855 MODULE_DESCRIPTION("Analog Devices AD7793 and similar ADCs"); 856 MODULE_LICENSE("GPL v2"); 857 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 858