1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7124 SPI ADC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/kfifo.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/property.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/adc/ad_sigma_delta.h>
24 #include <linux/iio/sysfs.h>
25
26 /* AD7124 registers */
27 #define AD7124_COMMS 0x00
28 #define AD7124_STATUS 0x00
29 #define AD7124_ADC_CONTROL 0x01
30 #define AD7124_DATA 0x02
31 #define AD7124_IO_CONTROL_1 0x03
32 #define AD7124_IO_CONTROL_2 0x04
33 #define AD7124_ID 0x05
34 #define AD7124_ERROR 0x06
35 #define AD7124_ERROR_EN 0x07
36 #define AD7124_MCLK_COUNT 0x08
37 #define AD7124_CHANNEL(x) (0x09 + (x))
38 #define AD7124_CONFIG(x) (0x19 + (x))
39 #define AD7124_FILTER(x) (0x21 + (x))
40 #define AD7124_OFFSET(x) (0x29 + (x))
41 #define AD7124_GAIN(x) (0x31 + (x))
42
43 /* AD7124_STATUS */
44 #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
45
46 /* AD7124_ADC_CONTROL */
47 #define AD7124_ADC_STATUS_EN_MSK BIT(10)
48 #define AD7124_ADC_STATUS_EN(x) FIELD_PREP(AD7124_ADC_STATUS_EN_MSK, x)
49 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
50 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
51 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
52 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
53 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
54 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
55
56 /* AD7124 ID */
57 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
58 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
59 #define AD7124_SILICON_REV_MSK GENMASK(3, 0)
60 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
61
62 #define CHIPID_AD7124_4 0x0
63 #define CHIPID_AD7124_8 0x1
64
65 /* AD7124_CHANNEL_X */
66 #define AD7124_CHANNEL_EN_MSK BIT(15)
67 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
68 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
69 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
70 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
71 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
72 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
73 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
74
75 /* AD7124_CONFIG_X */
76 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
77 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
78 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
79 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
80 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
81 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
82 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5)
83 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
84
85 /* AD7124_FILTER_X */
86 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
87 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
88 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
89 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
90
91 #define AD7124_SINC3_FILTER 2
92 #define AD7124_SINC4_FILTER 0
93
94 #define AD7124_CONF_ADDR_OFFSET 20
95 #define AD7124_MAX_CONFIGS 8
96 #define AD7124_MAX_CHANNELS 16
97
98 /* AD7124 input sources */
99 #define AD7124_INPUT_TEMPSENSOR 16
100 #define AD7124_INPUT_AVSS 17
101
102 enum ad7124_ids {
103 ID_AD7124_4,
104 ID_AD7124_8,
105 };
106
107 enum ad7124_ref_sel {
108 AD7124_REFIN1,
109 AD7124_REFIN2,
110 AD7124_INT_REF,
111 AD7124_AVDD_REF,
112 };
113
114 enum ad7124_power_mode {
115 AD7124_LOW_POWER,
116 AD7124_MID_POWER,
117 AD7124_FULL_POWER,
118 };
119
120 static const unsigned int ad7124_gain[8] = {
121 1, 2, 4, 8, 16, 32, 64, 128
122 };
123
124 static const unsigned int ad7124_reg_size[] = {
125 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
126 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
127 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
128 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
129 3, 3, 3, 3, 3
130 };
131
132 static const int ad7124_master_clk_freq_hz[3] = {
133 [AD7124_LOW_POWER] = 76800,
134 [AD7124_MID_POWER] = 153600,
135 [AD7124_FULL_POWER] = 614400,
136 };
137
138 static const char * const ad7124_ref_names[] = {
139 [AD7124_REFIN1] = "refin1",
140 [AD7124_REFIN2] = "refin2",
141 [AD7124_INT_REF] = "int",
142 [AD7124_AVDD_REF] = "avdd",
143 };
144
145 struct ad7124_chip_info {
146 const char *name;
147 unsigned int chip_id;
148 unsigned int num_inputs;
149 };
150
151 struct ad7124_channel_config {
152 bool live;
153 unsigned int cfg_slot;
154 /* Following fields are used to compare equality. */
155 struct_group(config_props,
156 enum ad7124_ref_sel refsel;
157 bool bipolar;
158 bool buf_positive;
159 bool buf_negative;
160 unsigned int vref_mv;
161 unsigned int pga_bits;
162 unsigned int odr;
163 unsigned int odr_sel_bits;
164 unsigned int filter_type;
165 );
166 };
167
168 struct ad7124_channel {
169 unsigned int nr;
170 struct ad7124_channel_config cfg;
171 unsigned int ain;
172 unsigned int slot;
173 };
174
175 struct ad7124_state {
176 const struct ad7124_chip_info *chip_info;
177 struct ad_sigma_delta sd;
178 struct ad7124_channel *channels;
179 struct regulator *vref[4];
180 struct clk *mclk;
181 unsigned int adc_control;
182 unsigned int num_channels;
183 struct mutex cfgs_lock; /* lock for configs access */
184 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
185 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
186 };
187
188 static const struct iio_chan_spec ad7124_channel_template = {
189 .type = IIO_VOLTAGE,
190 .indexed = 1,
191 .differential = 1,
192 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
193 BIT(IIO_CHAN_INFO_SCALE) |
194 BIT(IIO_CHAN_INFO_OFFSET) |
195 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
196 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
197 .scan_type = {
198 .sign = 'u',
199 .realbits = 24,
200 .storagebits = 32,
201 .endianness = IIO_BE,
202 },
203 };
204
205 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
206 [ID_AD7124_4] = {
207 .name = "ad7124-4",
208 .chip_id = CHIPID_AD7124_4,
209 .num_inputs = 8,
210 },
211 [ID_AD7124_8] = {
212 .name = "ad7124-8",
213 .chip_id = CHIPID_AD7124_8,
214 .num_inputs = 16,
215 },
216 };
217
ad7124_find_closest_match(const int * array,unsigned int size,int val)218 static int ad7124_find_closest_match(const int *array,
219 unsigned int size, int val)
220 {
221 int i, idx;
222 unsigned int diff_new, diff_old;
223
224 diff_old = U32_MAX;
225 idx = 0;
226
227 for (i = 0; i < size; i++) {
228 diff_new = abs(val - array[i]);
229 if (diff_new < diff_old) {
230 diff_old = diff_new;
231 idx = i;
232 }
233 }
234
235 return idx;
236 }
237
ad7124_spi_write_mask(struct ad7124_state * st,unsigned int addr,unsigned long mask,unsigned int val,unsigned int bytes)238 static int ad7124_spi_write_mask(struct ad7124_state *st,
239 unsigned int addr,
240 unsigned long mask,
241 unsigned int val,
242 unsigned int bytes)
243 {
244 unsigned int readval;
245 int ret;
246
247 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
248 if (ret < 0)
249 return ret;
250
251 readval &= ~mask;
252 readval |= val;
253
254 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
255 }
256
ad7124_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)257 static int ad7124_set_mode(struct ad_sigma_delta *sd,
258 enum ad_sigma_delta_mode mode)
259 {
260 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
261
262 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
263 st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
264
265 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
266 }
267
ad7124_set_channel_odr(struct ad7124_state * st,unsigned int channel,unsigned int odr)268 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
269 {
270 unsigned int fclk, odr_sel_bits;
271
272 fclk = clk_get_rate(st->mclk);
273 /*
274 * FS[10:0] = fCLK / (fADC x 32) where:
275 * fADC is the output data rate
276 * fCLK is the master clock frequency
277 * FS[10:0] are the bits in the filter register
278 * FS[10:0] can have a value from 1 to 2047
279 */
280 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
281 if (odr_sel_bits < 1)
282 odr_sel_bits = 1;
283 else if (odr_sel_bits > 2047)
284 odr_sel_bits = 2047;
285
286 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
287 st->channels[channel].cfg.live = false;
288
289 /* fADC = fCLK / (FS[10:0] x 32) */
290 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
291 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
292 }
293
ad7124_get_3db_filter_freq(struct ad7124_state * st,unsigned int channel)294 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
295 unsigned int channel)
296 {
297 unsigned int fadc;
298
299 fadc = st->channels[channel].cfg.odr;
300
301 switch (st->channels[channel].cfg.filter_type) {
302 case AD7124_SINC3_FILTER:
303 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
304 case AD7124_SINC4_FILTER:
305 return DIV_ROUND_CLOSEST(fadc * 262, 1000);
306 default:
307 return -EINVAL;
308 }
309 }
310
ad7124_set_3db_filter_freq(struct ad7124_state * st,unsigned int channel,unsigned int freq)311 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel,
312 unsigned int freq)
313 {
314 unsigned int sinc4_3db_odr;
315 unsigned int sinc3_3db_odr;
316 unsigned int new_filter;
317 unsigned int new_odr;
318
319 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
320 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
321
322 if (sinc4_3db_odr > sinc3_3db_odr) {
323 new_filter = AD7124_SINC3_FILTER;
324 new_odr = sinc4_3db_odr;
325 } else {
326 new_filter = AD7124_SINC4_FILTER;
327 new_odr = sinc3_3db_odr;
328 }
329
330 if (new_odr != st->channels[channel].cfg.odr)
331 st->channels[channel].cfg.live = false;
332
333 st->channels[channel].cfg.filter_type = new_filter;
334 st->channels[channel].cfg.odr = new_odr;
335 }
336
ad7124_find_similar_live_cfg(struct ad7124_state * st,struct ad7124_channel_config * cfg)337 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
338 struct ad7124_channel_config *cfg)
339 {
340 struct ad7124_channel_config *cfg_aux;
341 ptrdiff_t cmp_size;
342 int i;
343
344 cmp_size = sizeof_field(struct ad7124_channel_config, config_props);
345 for (i = 0; i < st->num_channels; i++) {
346 cfg_aux = &st->channels[i].cfg;
347
348 if (cfg_aux->live &&
349 !memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size))
350 return cfg_aux;
351 }
352
353 return NULL;
354 }
355
ad7124_find_free_config_slot(struct ad7124_state * st)356 static int ad7124_find_free_config_slot(struct ad7124_state *st)
357 {
358 unsigned int free_cfg_slot;
359
360 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS);
361 if (free_cfg_slot == AD7124_MAX_CONFIGS)
362 return -1;
363
364 return free_cfg_slot;
365 }
366
367 /* Only called during probe, so dev_err_probe() can be used */
ad7124_init_config_vref(struct ad7124_state * st,struct ad7124_channel_config * cfg)368 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
369 {
370 struct device *dev = &st->sd.spi->dev;
371 unsigned int refsel = cfg->refsel;
372
373 switch (refsel) {
374 case AD7124_REFIN1:
375 case AD7124_REFIN2:
376 case AD7124_AVDD_REF:
377 if (IS_ERR(st->vref[refsel]))
378 return dev_err_probe(dev, PTR_ERR(st->vref[refsel]),
379 "Error, trying to use external voltage reference without a %s regulator.\n",
380 ad7124_ref_names[refsel]);
381
382 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
383 /* Conversion from uV to mV */
384 cfg->vref_mv /= 1000;
385 return 0;
386 case AD7124_INT_REF:
387 cfg->vref_mv = 2500;
388 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
389 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
390 return 0;
391 default:
392 return dev_err_probe(dev, -EINVAL, "Invalid reference %d\n", refsel);
393 }
394 }
395
ad7124_write_config(struct ad7124_state * st,struct ad7124_channel_config * cfg,unsigned int cfg_slot)396 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
397 unsigned int cfg_slot)
398 {
399 unsigned int tmp;
400 unsigned int val;
401 int ret;
402
403 cfg->cfg_slot = cfg_slot;
404
405 tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
406 val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
407 AD7124_CONFIG_IN_BUFF(tmp) | AD7124_CONFIG_PGA(cfg->pga_bits);
408
409 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
410 if (ret < 0)
411 return ret;
412
413 tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type) |
414 AD7124_FILTER_FS(cfg->odr_sel_bits);
415 return ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot),
416 AD7124_FILTER_TYPE_MSK | AD7124_FILTER_FS_MSK,
417 tmp, 3);
418 }
419
ad7124_pop_config(struct ad7124_state * st)420 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
421 {
422 struct ad7124_channel_config *lru_cfg;
423 struct ad7124_channel_config *cfg;
424 int ret;
425 int i;
426
427 /*
428 * Pop least recently used config from the fifo
429 * in order to make room for the new one
430 */
431 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
432 if (ret <= 0)
433 return NULL;
434
435 lru_cfg->live = false;
436
437 /* mark slot as free */
438 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
439
440 /* invalidate all other configs that pointed to this one */
441 for (i = 0; i < st->num_channels; i++) {
442 cfg = &st->channels[i].cfg;
443
444 if (cfg->cfg_slot == lru_cfg->cfg_slot)
445 cfg->live = false;
446 }
447
448 return lru_cfg;
449 }
450
ad7124_push_config(struct ad7124_state * st,struct ad7124_channel_config * cfg)451 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
452 {
453 struct ad7124_channel_config *lru_cfg;
454 int free_cfg_slot;
455
456 free_cfg_slot = ad7124_find_free_config_slot(st);
457 if (free_cfg_slot >= 0) {
458 /* push the new config in configs queue */
459 kfifo_put(&st->live_cfgs_fifo, cfg);
460 } else {
461 /* pop one config to make room for the new one */
462 lru_cfg = ad7124_pop_config(st);
463 if (!lru_cfg)
464 return -EINVAL;
465
466 /* push the new config in configs queue */
467 free_cfg_slot = lru_cfg->cfg_slot;
468 kfifo_put(&st->live_cfgs_fifo, cfg);
469 }
470
471 /* mark slot as used */
472 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
473
474 return ad7124_write_config(st, cfg, free_cfg_slot);
475 }
476
ad7124_enable_channel(struct ad7124_state * st,struct ad7124_channel * ch)477 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
478 {
479 ch->cfg.live = true;
480 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
481 AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
482 }
483
ad7124_prepare_read(struct ad7124_state * st,int address)484 static int ad7124_prepare_read(struct ad7124_state *st, int address)
485 {
486 struct ad7124_channel_config *cfg = &st->channels[address].cfg;
487 struct ad7124_channel_config *live_cfg;
488
489 /*
490 * Before doing any reads assign the channel a configuration.
491 * Check if channel's config is on the device
492 */
493 if (!cfg->live) {
494 /* check if config matches another one */
495 live_cfg = ad7124_find_similar_live_cfg(st, cfg);
496 if (!live_cfg)
497 ad7124_push_config(st, cfg);
498 else
499 cfg->cfg_slot = live_cfg->cfg_slot;
500 }
501
502 /* point channel to the config slot and enable */
503 return ad7124_enable_channel(st, &st->channels[address]);
504 }
505
__ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)506 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
507 {
508 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
509
510 return ad7124_prepare_read(st, channel);
511 }
512
ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)513 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
514 {
515 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
516 int ret;
517
518 mutex_lock(&st->cfgs_lock);
519 ret = __ad7124_set_channel(sd, channel);
520 mutex_unlock(&st->cfgs_lock);
521
522 return ret;
523 }
524
ad7124_append_status(struct ad_sigma_delta * sd,bool append)525 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append)
526 {
527 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
528 unsigned int adc_control = st->adc_control;
529 int ret;
530
531 adc_control &= ~AD7124_ADC_STATUS_EN_MSK;
532 adc_control |= AD7124_ADC_STATUS_EN(append);
533
534 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control);
535 if (ret < 0)
536 return ret;
537
538 st->adc_control = adc_control;
539
540 return 0;
541 }
542
ad7124_disable_all(struct ad_sigma_delta * sd)543 static int ad7124_disable_all(struct ad_sigma_delta *sd)
544 {
545 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
546 int ret;
547 int i;
548
549 for (i = 0; i < st->num_channels; i++) {
550 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK, 0, 2);
551 if (ret < 0)
552 return ret;
553 }
554
555 return 0;
556 }
557
ad7124_disable_one(struct ad_sigma_delta * sd,unsigned int chan)558 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
559 {
560 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
561
562 return ad7124_spi_write_mask(st, AD7124_CHANNEL(chan), AD7124_CHANNEL_EN_MSK, 0, 2);
563 }
564
565 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
566 .set_channel = ad7124_set_channel,
567 .append_status = ad7124_append_status,
568 .disable_all = ad7124_disable_all,
569 .disable_one = ad7124_disable_one,
570 .set_mode = ad7124_set_mode,
571 .has_registers = true,
572 .addr_shift = 0,
573 .read_mask = BIT(6),
574 .status_ch_mask = GENMASK(3, 0),
575 .data_reg = AD7124_DATA,
576 .num_slots = 8,
577 .irq_flags = IRQF_TRIGGER_FALLING,
578 .num_resetclks = 64,
579 };
580
ad7124_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)581 static int ad7124_read_raw(struct iio_dev *indio_dev,
582 struct iio_chan_spec const *chan,
583 int *val, int *val2, long info)
584 {
585 struct ad7124_state *st = iio_priv(indio_dev);
586 int idx, ret;
587
588 switch (info) {
589 case IIO_CHAN_INFO_RAW:
590 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
591 if (ret < 0)
592 return ret;
593
594 return IIO_VAL_INT;
595 case IIO_CHAN_INFO_SCALE:
596 switch (chan->type) {
597 case IIO_VOLTAGE:
598 mutex_lock(&st->cfgs_lock);
599
600 idx = st->channels[chan->address].cfg.pga_bits;
601 *val = st->channels[chan->address].cfg.vref_mv;
602 if (st->channels[chan->address].cfg.bipolar)
603 *val2 = chan->scan_type.realbits - 1 + idx;
604 else
605 *val2 = chan->scan_type.realbits + idx;
606
607 mutex_unlock(&st->cfgs_lock);
608 return IIO_VAL_FRACTIONAL_LOG2;
609
610 case IIO_TEMP:
611 /*
612 * According to the data sheet
613 * Temperature (°C)
614 * = ((Conversion − 0x800000)/13584) − 272.5
615 * = (Conversion − 0x800000 - 13584 * 272.5) / 13584
616 * = (Conversion − 12090248) / 13584
617 * So scale with 1000/13584 to yield °mC. Reduce by 8 to
618 * 125/1698.
619 */
620 *val = 125;
621 *val2 = 1698;
622 return IIO_VAL_FRACTIONAL;
623
624 default:
625 return -EINVAL;
626 }
627
628 case IIO_CHAN_INFO_OFFSET:
629 switch (chan->type) {
630 case IIO_VOLTAGE:
631 mutex_lock(&st->cfgs_lock);
632 if (st->channels[chan->address].cfg.bipolar)
633 *val = -(1 << (chan->scan_type.realbits - 1));
634 else
635 *val = 0;
636
637 mutex_unlock(&st->cfgs_lock);
638 return IIO_VAL_INT;
639
640 case IIO_TEMP:
641 /* see calculation above */
642 *val = -12090248;
643 return IIO_VAL_INT;
644
645 default:
646 return -EINVAL;
647 }
648
649 case IIO_CHAN_INFO_SAMP_FREQ:
650 mutex_lock(&st->cfgs_lock);
651 *val = st->channels[chan->address].cfg.odr;
652 mutex_unlock(&st->cfgs_lock);
653
654 return IIO_VAL_INT;
655 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
656 mutex_lock(&st->cfgs_lock);
657 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
658 mutex_unlock(&st->cfgs_lock);
659
660 return IIO_VAL_INT;
661 default:
662 return -EINVAL;
663 }
664 }
665
ad7124_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)666 static int ad7124_write_raw(struct iio_dev *indio_dev,
667 struct iio_chan_spec const *chan,
668 int val, int val2, long info)
669 {
670 struct ad7124_state *st = iio_priv(indio_dev);
671 unsigned int res, gain, full_scale, vref;
672 int ret = 0;
673
674 mutex_lock(&st->cfgs_lock);
675
676 switch (info) {
677 case IIO_CHAN_INFO_SAMP_FREQ:
678 if (val2 != 0 || val == 0) {
679 ret = -EINVAL;
680 break;
681 }
682
683 ad7124_set_channel_odr(st, chan->address, val);
684 break;
685 case IIO_CHAN_INFO_SCALE:
686 if (val != 0) {
687 ret = -EINVAL;
688 break;
689 }
690
691 if (st->channels[chan->address].cfg.bipolar)
692 full_scale = 1 << (chan->scan_type.realbits - 1);
693 else
694 full_scale = 1 << chan->scan_type.realbits;
695
696 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
697 res = DIV_ROUND_CLOSEST(vref, full_scale);
698 gain = DIV_ROUND_CLOSEST(res, val2);
699 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
700
701 if (st->channels[chan->address].cfg.pga_bits != res)
702 st->channels[chan->address].cfg.live = false;
703
704 st->channels[chan->address].cfg.pga_bits = res;
705 break;
706 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
707 if (val2 != 0) {
708 ret = -EINVAL;
709 break;
710 }
711
712 ad7124_set_3db_filter_freq(st, chan->address, val);
713 break;
714 default:
715 ret = -EINVAL;
716 }
717
718 mutex_unlock(&st->cfgs_lock);
719 return ret;
720 }
721
ad7124_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)722 static int ad7124_reg_access(struct iio_dev *indio_dev,
723 unsigned int reg,
724 unsigned int writeval,
725 unsigned int *readval)
726 {
727 struct ad7124_state *st = iio_priv(indio_dev);
728 int ret;
729
730 if (reg >= ARRAY_SIZE(ad7124_reg_size))
731 return -EINVAL;
732
733 if (readval)
734 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
735 readval);
736 else
737 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
738 writeval);
739
740 return ret;
741 }
742
743 static IIO_CONST_ATTR(in_voltage_scale_available,
744 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
745
746 static struct attribute *ad7124_attributes[] = {
747 &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
748 NULL,
749 };
750
751 static const struct attribute_group ad7124_attrs_group = {
752 .attrs = ad7124_attributes,
753 };
754
ad7124_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)755 static int ad7124_update_scan_mode(struct iio_dev *indio_dev,
756 const unsigned long *scan_mask)
757 {
758 struct ad7124_state *st = iio_priv(indio_dev);
759 bool bit_set;
760 int ret;
761 int i;
762
763 mutex_lock(&st->cfgs_lock);
764 for (i = 0; i < st->num_channels; i++) {
765 bit_set = test_bit(i, scan_mask);
766 if (bit_set)
767 ret = __ad7124_set_channel(&st->sd, i);
768 else
769 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK,
770 0, 2);
771 if (ret < 0) {
772 mutex_unlock(&st->cfgs_lock);
773
774 return ret;
775 }
776 }
777
778 mutex_unlock(&st->cfgs_lock);
779
780 return 0;
781 }
782
783 static const struct iio_info ad7124_info = {
784 .read_raw = ad7124_read_raw,
785 .write_raw = ad7124_write_raw,
786 .debugfs_reg_access = &ad7124_reg_access,
787 .validate_trigger = ad_sd_validate_trigger,
788 .update_scan_mode = ad7124_update_scan_mode,
789 .attrs = &ad7124_attrs_group,
790 };
791
792 /* Only called during probe, so dev_err_probe() can be used */
ad7124_soft_reset(struct ad7124_state * st)793 static int ad7124_soft_reset(struct ad7124_state *st)
794 {
795 struct device *dev = &st->sd.spi->dev;
796 unsigned int readval, timeout;
797 int ret;
798
799 ret = ad_sd_reset(&st->sd);
800 if (ret < 0)
801 return ret;
802
803 fsleep(200);
804 timeout = 100;
805 do {
806 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
807 if (ret < 0)
808 return dev_err_probe(dev, ret, "Error reading status register\n");
809
810 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
811 return 0;
812
813 /* The AD7124 requires typically 2ms to power up and settle */
814 usleep_range(100, 2000);
815 } while (--timeout);
816
817 return dev_err_probe(dev, -EIO, "Soft reset failed\n");
818 }
819
ad7124_check_chip_id(struct ad7124_state * st)820 static int ad7124_check_chip_id(struct ad7124_state *st)
821 {
822 struct device *dev = &st->sd.spi->dev;
823 unsigned int readval, chip_id, silicon_rev;
824 int ret;
825
826 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
827 if (ret < 0)
828 return dev_err_probe(dev, ret, "Failure to read ID register\n");
829
830 chip_id = AD7124_DEVICE_ID_GET(readval);
831 silicon_rev = AD7124_SILICON_REV_GET(readval);
832
833 if (chip_id != st->chip_info->chip_id)
834 return dev_err_probe(dev, -ENODEV,
835 "Chip ID mismatch: expected %u, got %u\n",
836 st->chip_info->chip_id, chip_id);
837
838 if (silicon_rev == 0)
839 return dev_err_probe(dev, -ENODEV,
840 "Silicon revision empty. Chip may not be present\n");
841
842 return 0;
843 }
844
845 /*
846 * Input specifiers 8 - 15 are explicitly reserved for ad7124-4
847 * while they are fine for ad7124-8. Values above 31 don't fit
848 * into the register field and so are invalid for sure.
849 */
ad7124_valid_input_select(unsigned int ain,const struct ad7124_chip_info * info)850 static bool ad7124_valid_input_select(unsigned int ain, const struct ad7124_chip_info *info)
851 {
852 if (ain >= info->num_inputs && ain < 16)
853 return false;
854
855 return ain <= FIELD_MAX(AD7124_CHANNEL_AINM_MSK);
856 }
857
ad7124_parse_channel_config(struct iio_dev * indio_dev,struct device * dev)858 static int ad7124_parse_channel_config(struct iio_dev *indio_dev,
859 struct device *dev)
860 {
861 struct ad7124_state *st = iio_priv(indio_dev);
862 struct ad7124_channel_config *cfg;
863 struct ad7124_channel *channels;
864 struct iio_chan_spec *chan;
865 unsigned int ain[2], channel = 0, tmp;
866 unsigned int num_channels;
867 int ret;
868
869 num_channels = device_get_child_node_count(dev);
870
871 /*
872 * The driver assigns each logical channel defined in the device tree
873 * statically one channel register. So only accept 16 such logical
874 * channels to not treat CONFIG_0 (i.e. the register following
875 * CHANNEL_15) as an additional channel register. The driver could be
876 * improved to lift this limitation.
877 */
878 if (num_channels > AD7124_MAX_CHANNELS)
879 return dev_err_probe(dev, -EINVAL, "Too many channels defined\n");
880
881 /* Add one for temperature */
882 st->num_channels = min(num_channels + 1, AD7124_MAX_CHANNELS);
883
884 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
885 sizeof(*chan), GFP_KERNEL);
886 if (!chan)
887 return -ENOMEM;
888
889 channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
890 GFP_KERNEL);
891 if (!channels)
892 return -ENOMEM;
893
894 indio_dev->channels = chan;
895 indio_dev->num_channels = st->num_channels;
896 st->channels = channels;
897
898 device_for_each_child_node_scoped(dev, child) {
899 ret = fwnode_property_read_u32(child, "reg", &channel);
900 if (ret)
901 return dev_err_probe(dev, ret,
902 "Failed to parse reg property of %pfwP\n", child);
903
904 if (channel >= num_channels)
905 return dev_err_probe(dev, -EINVAL,
906 "Channel index >= number of channels in %pfwP\n", child);
907
908 ret = fwnode_property_read_u32_array(child, "diff-channels",
909 ain, 2);
910 if (ret)
911 return dev_err_probe(dev, ret,
912 "Failed to parse diff-channels property of %pfwP\n", child);
913
914 if (!ad7124_valid_input_select(ain[0], st->chip_info) ||
915 !ad7124_valid_input_select(ain[1], st->chip_info))
916 return dev_err_probe(dev, -EINVAL,
917 "diff-channels property of %pfwP contains invalid data\n", child);
918
919 st->channels[channel].nr = channel;
920 st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
921 AD7124_CHANNEL_AINM(ain[1]);
922
923 cfg = &st->channels[channel].cfg;
924 cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
925
926 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp);
927 if (ret)
928 cfg->refsel = AD7124_INT_REF;
929 else
930 cfg->refsel = tmp;
931
932 cfg->buf_positive =
933 fwnode_property_read_bool(child, "adi,buffered-positive");
934 cfg->buf_negative =
935 fwnode_property_read_bool(child, "adi,buffered-negative");
936
937 chan[channel] = ad7124_channel_template;
938 chan[channel].address = channel;
939 chan[channel].scan_index = channel;
940 chan[channel].channel = ain[0];
941 chan[channel].channel2 = ain[1];
942 }
943
944 if (num_channels < AD7124_MAX_CHANNELS) {
945 st->channels[num_channels] = (struct ad7124_channel) {
946 .nr = num_channels,
947 .ain = AD7124_CHANNEL_AINP(AD7124_INPUT_TEMPSENSOR) |
948 AD7124_CHANNEL_AINM(AD7124_INPUT_AVSS),
949 .cfg = {
950 .bipolar = true,
951 },
952 };
953
954 chan[num_channels] = (struct iio_chan_spec) {
955 .type = IIO_TEMP,
956 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
957 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) |
958 BIT(IIO_CHAN_INFO_SAMP_FREQ),
959 .scan_type = {
960 /*
961 * You might find it strange that a bipolar
962 * measurement yields an unsigned value, but
963 * this matches the device's manual.
964 */
965 .sign = 'u',
966 .realbits = 24,
967 .storagebits = 32,
968 .endianness = IIO_BE,
969 },
970 .address = num_channels,
971 .scan_index = num_channels,
972 };
973 }
974
975 return 0;
976 }
977
ad7124_setup(struct ad7124_state * st)978 static int ad7124_setup(struct ad7124_state *st)
979 {
980 struct device *dev = &st->sd.spi->dev;
981 unsigned int fclk, power_mode;
982 int i, ret;
983
984 fclk = clk_get_rate(st->mclk);
985 if (!fclk)
986 return dev_err_probe(dev, -EINVAL, "Failed to get mclk rate\n");
987
988 /* The power mode changes the master clock frequency */
989 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
990 ARRAY_SIZE(ad7124_master_clk_freq_hz),
991 fclk);
992 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
993 ret = clk_set_rate(st->mclk, fclk);
994 if (ret)
995 return dev_err_probe(dev, ret, "Failed to set mclk rate\n");
996 }
997
998 /* Set the power mode */
999 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
1000 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
1001
1002 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
1003 st->adc_control |= AD7124_ADC_CTRL_MODE(AD_SD_MODE_IDLE);
1004
1005 mutex_init(&st->cfgs_lock);
1006 INIT_KFIFO(st->live_cfgs_fifo);
1007 for (i = 0; i < st->num_channels; i++) {
1008
1009 ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
1010 if (ret < 0)
1011 return ret;
1012
1013 /*
1014 * 9.38 SPS is the minimum output data rate supported
1015 * regardless of the selected power mode. Round it up to 10 and
1016 * set all channels to this default value.
1017 */
1018 ad7124_set_channel_odr(st, i, 10);
1019
1020 /* Disable all channels to prevent unintended conversions. */
1021 ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, 0);
1022 }
1023
1024 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
1025 if (ret < 0)
1026 return dev_err_probe(dev, ret, "Failed to setup CONTROL register\n");
1027
1028 return ret;
1029 }
1030
ad7124_reg_disable(void * r)1031 static void ad7124_reg_disable(void *r)
1032 {
1033 regulator_disable(r);
1034 }
1035
ad7124_probe(struct spi_device * spi)1036 static int ad7124_probe(struct spi_device *spi)
1037 {
1038 const struct ad7124_chip_info *info;
1039 struct device *dev = &spi->dev;
1040 struct ad7124_state *st;
1041 struct iio_dev *indio_dev;
1042 int i, ret;
1043
1044 info = spi_get_device_match_data(spi);
1045 if (!info)
1046 return dev_err_probe(dev, -ENODEV, "Failed to get match data\n");
1047
1048 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1049 if (!indio_dev)
1050 return -ENOMEM;
1051
1052 st = iio_priv(indio_dev);
1053
1054 st->chip_info = info;
1055
1056 indio_dev->name = st->chip_info->name;
1057 indio_dev->modes = INDIO_DIRECT_MODE;
1058 indio_dev->info = &ad7124_info;
1059
1060 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
1061 if (ret < 0)
1062 return ret;
1063
1064 ret = ad7124_parse_channel_config(indio_dev, &spi->dev);
1065 if (ret < 0)
1066 return ret;
1067
1068 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
1069 if (i == AD7124_INT_REF)
1070 continue;
1071
1072 st->vref[i] = devm_regulator_get_optional(&spi->dev,
1073 ad7124_ref_names[i]);
1074 if (PTR_ERR(st->vref[i]) == -ENODEV)
1075 continue;
1076 else if (IS_ERR(st->vref[i]))
1077 return PTR_ERR(st->vref[i]);
1078
1079 ret = regulator_enable(st->vref[i]);
1080 if (ret)
1081 return dev_err_probe(dev, ret, "Failed to enable regulator #%d\n", i);
1082
1083 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
1084 st->vref[i]);
1085 if (ret)
1086 return dev_err_probe(dev, ret, "Failed to register disable handler for regulator #%d\n", i);
1087 }
1088
1089 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
1090 if (IS_ERR(st->mclk))
1091 return dev_err_probe(dev, PTR_ERR(st->mclk), "Failed to get mclk\n");
1092
1093 ret = ad7124_soft_reset(st);
1094 if (ret < 0)
1095 return ret;
1096
1097 ret = ad7124_check_chip_id(st);
1098 if (ret)
1099 return ret;
1100
1101 ret = ad7124_setup(st);
1102 if (ret < 0)
1103 return ret;
1104
1105 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1106 if (ret < 0)
1107 return dev_err_probe(dev, ret, "Failed to setup triggers\n");
1108
1109 ret = devm_iio_device_register(&spi->dev, indio_dev);
1110 if (ret < 0)
1111 return dev_err_probe(dev, ret, "Failed to register iio device\n");
1112
1113 return 0;
1114 }
1115
1116 static const struct of_device_id ad7124_of_match[] = {
1117 { .compatible = "adi,ad7124-4",
1118 .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
1119 { .compatible = "adi,ad7124-8",
1120 .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
1121 { }
1122 };
1123 MODULE_DEVICE_TABLE(of, ad7124_of_match);
1124
1125 static const struct spi_device_id ad71124_ids[] = {
1126 { "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] },
1127 { "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] },
1128 { }
1129 };
1130 MODULE_DEVICE_TABLE(spi, ad71124_ids);
1131
1132 static struct spi_driver ad71124_driver = {
1133 .driver = {
1134 .name = "ad7124",
1135 .of_match_table = ad7124_of_match,
1136 },
1137 .probe = ad7124_probe,
1138 .id_table = ad71124_ids,
1139 };
1140 module_spi_driver(ad71124_driver);
1141
1142 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1143 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
1144 MODULE_LICENSE("GPL");
1145 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
1146