1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7124 SPI ADC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 * Copyright 2025 BayLibre, SAS
7 */
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/cleanup.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/kfifo.h>
20 #include <linux/minmax.h>
21 #include <linux/module.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/property.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/spi/spi.h>
26 #include <linux/sprintf.h>
27 #include <linux/units.h>
28
29 #include <linux/iio/iio.h>
30 #include <linux/iio/adc/ad_sigma_delta.h>
31 #include <linux/iio/sysfs.h>
32
33 /* AD7124 registers */
34 #define AD7124_COMMS 0x00
35 #define AD7124_STATUS 0x00
36 #define AD7124_ADC_CONTROL 0x01
37 #define AD7124_DATA 0x02
38 #define AD7124_IO_CONTROL_1 0x03
39 #define AD7124_IO_CONTROL_2 0x04
40 #define AD7124_ID 0x05
41 #define AD7124_ERROR 0x06
42 #define AD7124_ERROR_EN 0x07
43 #define AD7124_MCLK_COUNT 0x08
44 #define AD7124_CHANNEL(x) (0x09 + (x))
45 #define AD7124_CONFIG(x) (0x19 + (x))
46 #define AD7124_FILTER(x) (0x21 + (x))
47 #define AD7124_OFFSET(x) (0x29 + (x))
48 #define AD7124_GAIN(x) (0x31 + (x))
49
50 /* AD7124_STATUS */
51 #define AD7124_STATUS_POR_FLAG BIT(4)
52
53 /* AD7124_ADC_CONTROL */
54 #define AD7124_ADC_CONTROL_CLK_SEL GENMASK(1, 0)
55 #define AD7124_ADC_CONTROL_CLK_SEL_INT 0
56 #define AD7124_ADC_CONTROL_CLK_SEL_INT_OUT 1
57 #define AD7124_ADC_CONTROL_CLK_SEL_EXT 2
58 #define AD7124_ADC_CONTROL_CLK_SEL_EXT_DIV4 3
59 #define AD7124_ADC_CONTROL_MODE GENMASK(5, 2)
60 #define AD7124_ADC_CONTROL_MODE_CONTINUOUS 0
61 #define AD7124_ADC_CONTROL_MODE_SINGLE 1
62 #define AD7124_ADC_CONTROL_MODE_STANDBY 2
63 #define AD7124_ADC_CONTROL_MODE_POWERDOWN 3
64 #define AD7124_ADC_CONTROL_MODE_IDLE 4
65 #define AD7124_ADC_CONTROL_MODE_INT_OFFSET_CALIB 5 /* Internal Zero-Scale Calibration */
66 #define AD7124_ADC_CONTROL_MODE_INT_GAIN_CALIB 6 /* Internal Full-Scale Calibration */
67 #define AD7124_ADC_CONTROL_MODE_SYS_OFFSET_CALIB 7 /* System Zero-Scale Calibration */
68 #define AD7124_ADC_CONTROL_MODE_SYS_GAIN_CALIB 8 /* System Full-Scale Calibration */
69 #define AD7124_ADC_CONTROL_POWER_MODE GENMASK(7, 6)
70 #define AD7124_ADC_CONTROL_POWER_MODE_LOW 0
71 #define AD7124_ADC_CONTROL_POWER_MODE_MID 1
72 #define AD7124_ADC_CONTROL_POWER_MODE_FULL 2
73 #define AD7124_ADC_CONTROL_REF_EN BIT(8)
74 #define AD7124_ADC_CONTROL_DATA_STATUS BIT(10)
75
76 /* AD7124_ID */
77 #define AD7124_ID_SILICON_REVISION GENMASK(3, 0)
78 #define AD7124_ID_DEVICE_ID GENMASK(7, 4)
79 #define AD7124_ID_DEVICE_ID_AD7124_4 0x0
80 #define AD7124_ID_DEVICE_ID_AD7124_8 0x1
81
82 /* AD7124_CHANNEL_X */
83 #define AD7124_CHANNEL_ENABLE BIT(15)
84 #define AD7124_CHANNEL_SETUP GENMASK(14, 12)
85 #define AD7124_CHANNEL_AINP GENMASK(9, 5)
86 #define AD7124_CHANNEL_AINM GENMASK(4, 0)
87 #define AD7124_CHANNEL_AINx_TEMPSENSOR 16
88 #define AD7124_CHANNEL_AINx_AVSS 17
89
90 /* AD7124_CONFIG_X */
91 #define AD7124_CONFIG_BIPOLAR BIT(11)
92 #define AD7124_CONFIG_IN_BUFF GENMASK(6, 5)
93 #define AD7124_CONFIG_AIN_BUFP BIT(6)
94 #define AD7124_CONFIG_AIN_BUFM BIT(5)
95 #define AD7124_CONFIG_REF_SEL GENMASK(4, 3)
96 #define AD7124_CONFIG_PGA GENMASK(2, 0)
97
98 /* AD7124_FILTER_X */
99 #define AD7124_FILTER_FILTER GENMASK(23, 21)
100 #define AD7124_FILTER_FILTER_SINC4 0
101 #define AD7124_FILTER_FILTER_SINC3 2
102 #define AD7124_FILTER_FILTER_SINC4_SINC1 4
103 #define AD7124_FILTER_FILTER_SINC3_SINC1 5
104 #define AD7124_FILTER_FILTER_SINC3_PF 7
105 #define AD7124_FILTER_REJ60 BIT(20)
106 #define AD7124_FILTER_POST_FILTER GENMASK(19, 17)
107 #define AD7124_FILTER_POST_FILTER_47dB 2
108 #define AD7124_FILTER_POST_FILTER_62dB 3
109 #define AD7124_FILTER_POST_FILTER_86dB 5
110 #define AD7124_FILTER_POST_FILTER_92dB 6
111 #define AD7124_FILTER_SINGLE_CYCLE BIT(16)
112 #define AD7124_FILTER_FS GENMASK(10, 0)
113
114 #define AD7124_CFG_SLOT_UNASSIGNED ~0U
115
116 #define AD7124_MAX_CONFIGS 8
117 #define AD7124_MAX_CHANNELS 16
118
119 #define AD7124_INT_CLK_HZ 614400
120
121 /* AD7124 input sources */
122
123 enum ad7124_ref_sel {
124 AD7124_REFIN1,
125 AD7124_REFIN2,
126 AD7124_INT_REF,
127 AD7124_AVDD_REF,
128 };
129
130 enum ad7124_power_mode {
131 AD7124_LOW_POWER,
132 AD7124_MID_POWER,
133 AD7124_FULL_POWER,
134 };
135
136 static const unsigned int ad7124_gain[8] = {
137 1, 2, 4, 8, 16, 32, 64, 128
138 };
139
140 static const unsigned int ad7124_reg_size[] = {
141 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
142 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
143 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
144 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
145 3, 3, 3, 3, 3
146 };
147
148 static const int ad7124_master_clk_freq_hz[3] = {
149 [AD7124_LOW_POWER] = AD7124_INT_CLK_HZ / 8,
150 [AD7124_MID_POWER] = AD7124_INT_CLK_HZ / 4,
151 [AD7124_FULL_POWER] = AD7124_INT_CLK_HZ,
152 };
153
154 static const char * const ad7124_ref_names[] = {
155 [AD7124_REFIN1] = "refin1",
156 [AD7124_REFIN2] = "refin2",
157 [AD7124_INT_REF] = "int",
158 [AD7124_AVDD_REF] = "avdd",
159 };
160
161 struct ad7124_chip_info {
162 const char *name;
163 unsigned int chip_id;
164 unsigned int num_inputs;
165 };
166
167 enum ad7124_filter_type {
168 AD7124_FILTER_TYPE_SINC3,
169 AD7124_FILTER_TYPE_SINC3_PF1,
170 AD7124_FILTER_TYPE_SINC3_PF2,
171 AD7124_FILTER_TYPE_SINC3_PF3,
172 AD7124_FILTER_TYPE_SINC3_PF4,
173 AD7124_FILTER_TYPE_SINC3_REJ60,
174 AD7124_FILTER_TYPE_SINC3_SINC1,
175 AD7124_FILTER_TYPE_SINC4,
176 AD7124_FILTER_TYPE_SINC4_REJ60,
177 AD7124_FILTER_TYPE_SINC4_SINC1,
178 };
179
180 struct ad7124_channel_config {
181 unsigned int cfg_slot;
182 unsigned int requested_odr;
183 unsigned int requested_odr_micro;
184 /*
185 * Following fields are used to compare for equality. If you
186 * make adaptations in it, you most likely also have to adapt
187 * ad7124_config_equal(), too.
188 */
189 struct_group(config_props,
190 enum ad7124_ref_sel refsel;
191 bool bipolar;
192 bool buf_positive;
193 bool buf_negative;
194 unsigned int vref_mv;
195 unsigned int pga_bits;
196 unsigned int odr_sel_bits;
197 enum ad7124_filter_type filter_type;
198 unsigned int calibration_offset;
199 unsigned int calibration_gain;
200 );
201 };
202
203 struct ad7124_channel {
204 struct ad7124_channel_config cfg;
205 unsigned int ain;
206 unsigned int slot;
207 u8 syscalib_mode;
208 };
209
210 struct ad7124_state {
211 const struct ad7124_chip_info *chip_info;
212 struct ad_sigma_delta sd;
213 struct ad7124_channel *channels;
214 struct regulator *vref[4];
215 u32 clk_hz;
216 unsigned int adc_control;
217 unsigned int num_channels;
218 struct mutex cfgs_lock; /* lock for configs access */
219 u8 cfg_slot_use_count[AD7124_MAX_CONFIGS];
220
221 /*
222 * Stores the power-on reset value for the GAIN(x) registers which are
223 * needed for measurements at gain 1 (i.e. CONFIG(x).PGA == 0)
224 */
225 unsigned int gain_default;
226 bool enable_single_cycle;
227 };
228
229 static const struct ad7124_chip_info ad7124_4_chip_info = {
230 .name = "ad7124-4",
231 .chip_id = AD7124_ID_DEVICE_ID_AD7124_4,
232 .num_inputs = 8,
233 };
234
235 static const struct ad7124_chip_info ad7124_8_chip_info = {
236 .name = "ad7124-8",
237 .chip_id = AD7124_ID_DEVICE_ID_AD7124_8,
238 .num_inputs = 16,
239 };
240
ad7124_find_closest_match(const int * array,unsigned int size,int val)241 static int ad7124_find_closest_match(const int *array,
242 unsigned int size, int val)
243 {
244 int i, idx;
245 unsigned int diff_new, diff_old;
246
247 diff_old = U32_MAX;
248 idx = 0;
249
250 for (i = 0; i < size; i++) {
251 diff_new = abs(val - array[i]);
252 if (diff_new < diff_old) {
253 diff_old = diff_new;
254 idx = i;
255 }
256 }
257
258 return idx;
259 }
260
ad7124_spi_write_mask(struct ad7124_state * st,unsigned int addr,unsigned long mask,unsigned int val,unsigned int bytes)261 static int ad7124_spi_write_mask(struct ad7124_state *st,
262 unsigned int addr,
263 unsigned long mask,
264 unsigned int val,
265 unsigned int bytes)
266 {
267 unsigned int readval;
268 int ret;
269
270 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
271 if (ret < 0)
272 return ret;
273
274 readval &= ~mask;
275 readval |= val;
276
277 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
278 }
279
ad7124_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)280 static int ad7124_set_mode(struct ad_sigma_delta *sd,
281 enum ad_sigma_delta_mode mode)
282 {
283 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
284
285 st->adc_control &= ~AD7124_ADC_CONTROL_MODE;
286 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_MODE, mode);
287
288 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
289 }
290
ad7124_get_fclk_hz(struct ad7124_state * st)291 static u32 ad7124_get_fclk_hz(struct ad7124_state *st)
292 {
293 enum ad7124_power_mode power_mode;
294 u32 fclk_hz;
295
296 power_mode = FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, st->adc_control);
297 fclk_hz = st->clk_hz;
298
299 switch (power_mode) {
300 case AD7124_LOW_POWER:
301 fclk_hz /= 8;
302 break;
303 case AD7124_MID_POWER:
304 fclk_hz /= 4;
305 break;
306 default:
307 break;
308 }
309
310 return fclk_hz;
311 }
312
ad7124_get_fs_factor(struct ad7124_state * st,unsigned int channel)313 static u32 ad7124_get_fs_factor(struct ad7124_state *st, unsigned int channel)
314 {
315 enum ad7124_power_mode power_mode =
316 FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, st->adc_control);
317 u32 avg = power_mode == AD7124_LOW_POWER ? 8 : 16;
318
319 /*
320 * These are the "zero-latency" factors from the data sheet. For the
321 * sinc1 filters, these aren't documented, but derived by taking the
322 * single-channel formula from the sinc1 section of the data sheet and
323 * multiplying that by the sinc3/4 factor from the corresponding zero-
324 * latency sections.
325 */
326 switch (st->channels[channel].cfg.filter_type) {
327 case AD7124_FILTER_TYPE_SINC4:
328 case AD7124_FILTER_TYPE_SINC4_REJ60:
329 return 4 * 32;
330 case AD7124_FILTER_TYPE_SINC4_SINC1:
331 return 4 * avg * 32;
332 case AD7124_FILTER_TYPE_SINC3_SINC1:
333 return 3 * avg * 32;
334 default:
335 return 3 * 32;
336 }
337 }
338
ad7124_get_fadc_divisor(struct ad7124_state * st,unsigned int channel)339 static u32 ad7124_get_fadc_divisor(struct ad7124_state *st, unsigned int channel)
340 {
341 u32 factor = ad7124_get_fs_factor(st, channel);
342
343 /*
344 * The output data rate (f_ADC) is f_CLK / divisor. We are returning
345 * the divisor.
346 */
347 return st->channels[channel].cfg.odr_sel_bits * factor;
348 }
349
ad7124_set_channel_odr(struct ad7124_state * st,unsigned int channel)350 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel)
351 {
352 struct ad7124_channel_config *cfg = &st->channels[channel].cfg;
353 unsigned int fclk, factor, divisor, odr_sel_bits;
354
355 fclk = ad7124_get_fclk_hz(st);
356 factor = ad7124_get_fs_factor(st, channel);
357
358 /*
359 * FS[10:0] = fCLK / (fADC x 32 * N) where:
360 * fADC is the output data rate
361 * fCLK is the master clock frequency
362 * N is number of conversions per sample (depends on filter type)
363 * FS[10:0] are the bits in the filter register
364 * FS[10:0] can have a value from 1 to 2047
365 */
366 divisor = cfg->requested_odr * factor +
367 cfg->requested_odr_micro * factor / MICRO;
368 odr_sel_bits = clamp(DIV_ROUND_CLOSEST(fclk, divisor), 1, 2047);
369
370 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
371 }
372
ad7124_get_3db_filter_factor(struct ad7124_state * st,unsigned int channel)373 static int ad7124_get_3db_filter_factor(struct ad7124_state *st,
374 unsigned int channel)
375 {
376 struct ad7124_channel_config *cfg = &st->channels[channel].cfg;
377
378 /*
379 * 3dB point is the f_CLK rate times some factor. This functions returns
380 * the factor times 1000.
381 */
382 switch (cfg->filter_type) {
383 case AD7124_FILTER_TYPE_SINC3:
384 case AD7124_FILTER_TYPE_SINC3_REJ60:
385 case AD7124_FILTER_TYPE_SINC3_SINC1:
386 return 272;
387 case AD7124_FILTER_TYPE_SINC4:
388 case AD7124_FILTER_TYPE_SINC4_REJ60:
389 case AD7124_FILTER_TYPE_SINC4_SINC1:
390 return 230;
391 case AD7124_FILTER_TYPE_SINC3_PF1:
392 return 633;
393 case AD7124_FILTER_TYPE_SINC3_PF2:
394 return 605;
395 case AD7124_FILTER_TYPE_SINC3_PF3:
396 return 669;
397 case AD7124_FILTER_TYPE_SINC3_PF4:
398 return 759;
399 default:
400 return -EINVAL;
401 }
402 }
403
404 /* Only called during probe, so dev_err_probe() can be used */
ad7124_init_config_vref(struct ad7124_state * st,struct ad7124_channel_config * cfg)405 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
406 {
407 struct device *dev = &st->sd.spi->dev;
408 unsigned int refsel = cfg->refsel;
409
410 switch (refsel) {
411 case AD7124_REFIN1:
412 case AD7124_REFIN2:
413 case AD7124_AVDD_REF:
414 if (IS_ERR(st->vref[refsel]))
415 return dev_err_probe(dev, PTR_ERR(st->vref[refsel]),
416 "Error, trying to use external voltage reference without a %s regulator.\n",
417 ad7124_ref_names[refsel]);
418
419 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
420 /* Conversion from uV to mV */
421 cfg->vref_mv /= 1000;
422 return 0;
423 case AD7124_INT_REF:
424 cfg->vref_mv = 2500;
425 st->adc_control |= AD7124_ADC_CONTROL_REF_EN;
426 return 0;
427 default:
428 return dev_err_probe(dev, -EINVAL, "Invalid reference %d\n", refsel);
429 }
430 }
431
ad7124_config_equal(struct ad7124_channel_config * a,struct ad7124_channel_config * b)432 static bool ad7124_config_equal(struct ad7124_channel_config *a,
433 struct ad7124_channel_config *b)
434 {
435 return a->refsel == b->refsel &&
436 a->bipolar == b->bipolar &&
437 a->buf_positive == b->buf_positive &&
438 a->buf_negative == b->buf_negative &&
439 a->vref_mv == b->vref_mv &&
440 a->pga_bits == b->pga_bits &&
441 a->odr_sel_bits == b->odr_sel_bits &&
442 a->filter_type == b->filter_type &&
443 a->calibration_offset == b->calibration_offset &&
444 a->calibration_gain == b->calibration_gain;
445 }
446
ad7124_write_config(struct ad7124_state * st,struct ad7124_channel_config * cfg,unsigned int cfg_slot)447 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
448 unsigned int cfg_slot)
449 {
450 unsigned int val, filter;
451 unsigned int rej60 = 0;
452 unsigned int post = 0;
453 int ret;
454
455 ret = ad_sd_write_reg(&st->sd, AD7124_OFFSET(cfg_slot), 3,
456 cfg->calibration_offset);
457 if (ret)
458 return ret;
459
460 ret = ad_sd_write_reg(&st->sd, AD7124_GAIN(cfg_slot), 3,
461 cfg->calibration_gain);
462 if (ret)
463 return ret;
464
465 val = FIELD_PREP(AD7124_CONFIG_BIPOLAR, cfg->bipolar) |
466 FIELD_PREP(AD7124_CONFIG_REF_SEL, cfg->refsel) |
467 (cfg->buf_positive ? AD7124_CONFIG_AIN_BUFP : 0) |
468 (cfg->buf_negative ? AD7124_CONFIG_AIN_BUFM : 0) |
469 FIELD_PREP(AD7124_CONFIG_PGA, cfg->pga_bits);
470
471 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg_slot), 2, val);
472 if (ret < 0)
473 return ret;
474
475 switch (cfg->filter_type) {
476 case AD7124_FILTER_TYPE_SINC3:
477 filter = AD7124_FILTER_FILTER_SINC3;
478 break;
479 case AD7124_FILTER_TYPE_SINC3_PF1:
480 filter = AD7124_FILTER_FILTER_SINC3_PF;
481 post = AD7124_FILTER_POST_FILTER_47dB;
482 break;
483 case AD7124_FILTER_TYPE_SINC3_PF2:
484 filter = AD7124_FILTER_FILTER_SINC3_PF;
485 post = AD7124_FILTER_POST_FILTER_62dB;
486 break;
487 case AD7124_FILTER_TYPE_SINC3_PF3:
488 filter = AD7124_FILTER_FILTER_SINC3_PF;
489 post = AD7124_FILTER_POST_FILTER_86dB;
490 break;
491 case AD7124_FILTER_TYPE_SINC3_PF4:
492 filter = AD7124_FILTER_FILTER_SINC3_PF;
493 post = AD7124_FILTER_POST_FILTER_92dB;
494 break;
495 case AD7124_FILTER_TYPE_SINC3_REJ60:
496 filter = AD7124_FILTER_FILTER_SINC3;
497 rej60 = 1;
498 break;
499 case AD7124_FILTER_TYPE_SINC3_SINC1:
500 filter = AD7124_FILTER_FILTER_SINC3_SINC1;
501 break;
502 case AD7124_FILTER_TYPE_SINC4:
503 filter = AD7124_FILTER_FILTER_SINC4;
504 break;
505 case AD7124_FILTER_TYPE_SINC4_REJ60:
506 filter = AD7124_FILTER_FILTER_SINC4;
507 rej60 = 1;
508 break;
509 case AD7124_FILTER_TYPE_SINC4_SINC1:
510 filter = AD7124_FILTER_FILTER_SINC4_SINC1;
511 break;
512 default:
513 return -EINVAL;
514 }
515
516 /*
517 * NB: AD7124_FILTER_SINGLE_CYCLE is always set so that we get the same
518 * sampling frequency even when only one channel is enabled in a
519 * buffered read. If it was not set, the N in ad7124_set_channel_odr()
520 * would be 1 and we would get a faster sampling frequency than what
521 * was requested. It may only be disabled through debugfs for testing
522 * purposes.
523 */
524 return ad_sd_write_reg(&st->sd, AD7124_FILTER(cfg_slot), 3,
525 FIELD_PREP(AD7124_FILTER_FILTER, filter) |
526 FIELD_PREP(AD7124_FILTER_REJ60, rej60) |
527 FIELD_PREP(AD7124_FILTER_POST_FILTER, post) |
528 FIELD_PREP(AD7124_FILTER_SINGLE_CYCLE,
529 st->enable_single_cycle) |
530 FIELD_PREP(AD7124_FILTER_FS, cfg->odr_sel_bits));
531 }
532
533 /**
534 * ad7124_request_config_slot() - Request a config slot for a given config
535 * @st: Driver instance
536 * @channel: Channel to request a slot for
537 *
538 * Tries to find a matching config already in use, otherwise finds a free
539 * slot. If this function returns successfully, the use count for the slot is
540 * increased and the slot number is stored in cfg->cfg_slot.
541 *
542 * The slot must be released again with ad7124_release_config_slot() when no
543 * longer needed.
544 *
545 * Returns: 0 if a slot was successfully assigned, -EUSERS if no slot is
546 * available or other error if SPI communication fails.
547 */
ad7124_request_config_slot(struct ad7124_state * st,u8 channel)548 static int ad7124_request_config_slot(struct ad7124_state *st, u8 channel)
549 {
550 unsigned int other, slot;
551 int last_used_slot = -1;
552
553 /* Find another channel with a matching config, if any. */
554 for (other = 0; other < st->num_channels; other++) {
555 if (other == channel)
556 continue;
557
558 if (st->channels[other].cfg.cfg_slot == AD7124_CFG_SLOT_UNASSIGNED)
559 continue;
560
561 last_used_slot = max_t(int, last_used_slot,
562 st->channels[other].cfg.cfg_slot);
563
564 if (!ad7124_config_equal(&st->channels[other].cfg,
565 &st->channels[channel].cfg))
566 continue;
567
568 /* Found a match, re-use that slot. */
569 slot = st->channels[other].cfg.cfg_slot;
570 st->cfg_slot_use_count[slot]++;
571 st->channels[channel].cfg.cfg_slot = slot;
572
573 return 0;
574 }
575
576 /* No match, use next free slot. */
577 slot = last_used_slot + 1;
578 if (slot >= AD7124_MAX_CONFIGS)
579 return -EUSERS;
580
581 st->cfg_slot_use_count[slot]++;
582 st->channels[channel].cfg.cfg_slot = slot;
583
584 return ad7124_write_config(st, &st->channels[channel].cfg, slot);
585 }
586
ad7124_release_config_slot(struct ad7124_state * st,u8 channel)587 static void ad7124_release_config_slot(struct ad7124_state *st, u8 channel)
588 {
589 unsigned int slot;
590
591 /*
592 * All of these early return conditions can happen at probe when all
593 * channels are disabled. Otherwise, they should not happen normally.
594 */
595 if (channel >= st->num_channels)
596 return;
597
598 slot = st->channels[channel].cfg.cfg_slot;
599
600 if (slot == AD7124_CFG_SLOT_UNASSIGNED ||
601 st->cfg_slot_use_count[slot] == 0)
602 return;
603
604 st->cfg_slot_use_count[slot]--;
605 st->channels[channel].cfg.cfg_slot = AD7124_CFG_SLOT_UNASSIGNED;
606 }
607
ad7124_prepare_read(struct ad7124_state * st,int address)608 static int ad7124_prepare_read(struct ad7124_state *st, int address)
609 {
610 struct ad7124_channel_config *cfg = &st->channels[address].cfg;
611 int ret;
612
613 ret = ad7124_request_config_slot(st, address);
614 if (ret)
615 return ret;
616
617 /* point channel to the config slot and enable */
618 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(address), 2,
619 st->channels[address].ain |
620 FIELD_PREP(AD7124_CHANNEL_SETUP, cfg->cfg_slot) |
621 AD7124_CHANNEL_ENABLE);
622 }
623
ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)624 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
625 {
626 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
627 int ret;
628
629 mutex_lock(&st->cfgs_lock);
630 ret = ad7124_prepare_read(st, channel);
631 mutex_unlock(&st->cfgs_lock);
632
633 return ret;
634 }
635
ad7124_append_status(struct ad_sigma_delta * sd,bool append)636 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append)
637 {
638 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
639 unsigned int adc_control = st->adc_control;
640 int ret;
641
642 if (append)
643 adc_control |= AD7124_ADC_CONTROL_DATA_STATUS;
644 else
645 adc_control &= ~AD7124_ADC_CONTROL_DATA_STATUS;
646
647 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control);
648 if (ret < 0)
649 return ret;
650
651 st->adc_control = adc_control;
652
653 return 0;
654 }
655
ad7124_disable_one(struct ad_sigma_delta * sd,unsigned int chan)656 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
657 {
658 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
659
660 ad7124_release_config_slot(st, chan);
661
662 /* The relevant thing here is that AD7124_CHANNEL_ENABLE is cleared. */
663 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan), 2, 0);
664 }
665
ad7124_disable_all(struct ad_sigma_delta * sd)666 static int ad7124_disable_all(struct ad_sigma_delta *sd)
667 {
668 int ret;
669 int i;
670
671 for (i = 0; i < AD7124_MAX_CHANNELS; i++) {
672 ret = ad7124_disable_one(sd, i);
673 if (ret < 0)
674 return ret;
675 }
676
677 return 0;
678 }
679
680 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
681 .set_channel = ad7124_set_channel,
682 .append_status = ad7124_append_status,
683 .disable_all = ad7124_disable_all,
684 .disable_one = ad7124_disable_one,
685 .set_mode = ad7124_set_mode,
686 .has_registers = true,
687 .addr_shift = 0,
688 .read_mask = BIT(6),
689 .status_ch_mask = GENMASK(3, 0),
690 .data_reg = AD7124_DATA,
691 .num_slots = 8,
692 .irq_flags = IRQF_TRIGGER_FALLING,
693 .num_resetclks = 64,
694 };
695
696 static const int ad7124_voltage_scales[][2] = {
697 { 0, 1164 },
698 { 0, 2328 },
699 { 0, 4656 },
700 { 0, 9313 },
701 { 0, 18626 },
702 { 0, 37252 },
703 { 0, 74505 },
704 { 0, 149011 },
705 { 0, 298023 },
706 };
707
ad7124_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)708 static int ad7124_read_avail(struct iio_dev *indio_dev,
709 struct iio_chan_spec const *chan,
710 const int **vals, int *type, int *length, long info)
711 {
712 switch (info) {
713 case IIO_CHAN_INFO_SCALE:
714 *vals = (const int *)ad7124_voltage_scales;
715 *type = IIO_VAL_INT_PLUS_NANO;
716 *length = ARRAY_SIZE(ad7124_voltage_scales) * 2;
717 return IIO_AVAIL_LIST;
718 default:
719 return -EINVAL;
720 }
721 }
722
ad7124_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)723 static int ad7124_read_raw(struct iio_dev *indio_dev,
724 struct iio_chan_spec const *chan,
725 int *val, int *val2, long info)
726 {
727 struct ad7124_state *st = iio_priv(indio_dev);
728 int idx, ret;
729
730 switch (info) {
731 case IIO_CHAN_INFO_RAW:
732 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
733 if (ret < 0)
734 return ret;
735
736 return IIO_VAL_INT;
737 case IIO_CHAN_INFO_SCALE:
738 switch (chan->type) {
739 case IIO_VOLTAGE:
740 mutex_lock(&st->cfgs_lock);
741
742 idx = st->channels[chan->address].cfg.pga_bits;
743 *val = st->channels[chan->address].cfg.vref_mv;
744 if (st->channels[chan->address].cfg.bipolar)
745 *val2 = chan->scan_type.realbits - 1 + idx;
746 else
747 *val2 = chan->scan_type.realbits + idx;
748
749 mutex_unlock(&st->cfgs_lock);
750 return IIO_VAL_FRACTIONAL_LOG2;
751
752 case IIO_TEMP:
753 /*
754 * According to the data sheet
755 * Temperature (°C)
756 * = ((Conversion − 0x800000)/13584) − 272.5
757 * = (Conversion − 0x800000 - 13584 * 272.5) / 13584
758 * = (Conversion − 12090248) / 13584
759 * So scale with 1000/13584 to yield °mC. Reduce by 8 to
760 * 125/1698.
761 */
762 *val = 125;
763 *val2 = 1698;
764 return IIO_VAL_FRACTIONAL;
765
766 default:
767 return -EINVAL;
768 }
769
770 case IIO_CHAN_INFO_OFFSET:
771 switch (chan->type) {
772 case IIO_VOLTAGE:
773 mutex_lock(&st->cfgs_lock);
774 if (st->channels[chan->address].cfg.bipolar)
775 *val = -(1 << (chan->scan_type.realbits - 1));
776 else
777 *val = 0;
778
779 mutex_unlock(&st->cfgs_lock);
780 return IIO_VAL_INT;
781
782 case IIO_TEMP:
783 /* see calculation above */
784 *val = -12090248;
785 return IIO_VAL_INT;
786
787 default:
788 return -EINVAL;
789 }
790
791 case IIO_CHAN_INFO_SAMP_FREQ: {
792 struct ad7124_channel_config *cfg = &st->channels[chan->address].cfg;
793
794 guard(mutex)(&st->cfgs_lock);
795
796 switch (cfg->filter_type) {
797 case AD7124_FILTER_TYPE_SINC3:
798 case AD7124_FILTER_TYPE_SINC3_REJ60:
799 case AD7124_FILTER_TYPE_SINC3_SINC1:
800 case AD7124_FILTER_TYPE_SINC4:
801 case AD7124_FILTER_TYPE_SINC4_REJ60:
802 case AD7124_FILTER_TYPE_SINC4_SINC1:
803 *val = ad7124_get_fclk_hz(st);
804 *val2 = ad7124_get_fadc_divisor(st, chan->address);
805 return IIO_VAL_FRACTIONAL;
806 /*
807 * Post filters force the chip to a fixed rate. These are the
808 * single-channel rates from the data sheet divided by 3 for
809 * the multi-channel case (data sheet doesn't explicitly state
810 * this but confirmed through testing).
811 */
812 case AD7124_FILTER_TYPE_SINC3_PF1:
813 *val = 300;
814 *val2 = 33;
815 return IIO_VAL_FRACTIONAL;
816 case AD7124_FILTER_TYPE_SINC3_PF2:
817 *val = 25;
818 *val2 = 3;
819 return IIO_VAL_FRACTIONAL;
820 case AD7124_FILTER_TYPE_SINC3_PF3:
821 *val = 20;
822 *val2 = 3;
823 return IIO_VAL_FRACTIONAL;
824 case AD7124_FILTER_TYPE_SINC3_PF4:
825 *val = 50;
826 *val2 = 9;
827 return IIO_VAL_FRACTIONAL;
828 default:
829 return -EINVAL;
830 }
831 }
832 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: {
833 guard(mutex)(&st->cfgs_lock);
834
835 ret = ad7124_get_3db_filter_factor(st, chan->address);
836 if (ret < 0)
837 return ret;
838
839 /* 3dB point is the f_CLK rate times a fractional value */
840 *val = ret * ad7124_get_fclk_hz(st);
841 *val2 = MILLI * ad7124_get_fadc_divisor(st, chan->address);
842 return IIO_VAL_FRACTIONAL;
843 }
844 default:
845 return -EINVAL;
846 }
847 }
848
ad7124_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)849 static int ad7124_write_raw(struct iio_dev *indio_dev,
850 struct iio_chan_spec const *chan,
851 int val, int val2, long info)
852 {
853 struct ad7124_state *st = iio_priv(indio_dev);
854 struct ad7124_channel_config *cfg = &st->channels[chan->address].cfg;
855 unsigned int res, gain, full_scale, vref;
856
857 guard(mutex)(&st->cfgs_lock);
858
859 switch (info) {
860 case IIO_CHAN_INFO_SAMP_FREQ:
861 if (val2 < 0 || val < 0 || (val2 == 0 && val == 0))
862 return -EINVAL;
863
864 cfg->requested_odr = val;
865 cfg->requested_odr_micro = val2;
866 ad7124_set_channel_odr(st, chan->address);
867
868 return 0;
869 case IIO_CHAN_INFO_SCALE:
870 if (val != 0)
871 return -EINVAL;
872
873 if (st->channels[chan->address].cfg.bipolar)
874 full_scale = 1 << (chan->scan_type.realbits - 1);
875 else
876 full_scale = 1 << chan->scan_type.realbits;
877
878 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
879 res = DIV_ROUND_CLOSEST(vref, full_scale);
880 gain = DIV_ROUND_CLOSEST(res, val2);
881 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
882
883 st->channels[chan->address].cfg.pga_bits = res;
884 return 0;
885 default:
886 return -EINVAL;
887 }
888 }
889
ad7124_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)890 static int ad7124_reg_access(struct iio_dev *indio_dev,
891 unsigned int reg,
892 unsigned int writeval,
893 unsigned int *readval)
894 {
895 struct ad7124_state *st = iio_priv(indio_dev);
896 int ret;
897
898 if (reg >= ARRAY_SIZE(ad7124_reg_size))
899 return -EINVAL;
900
901 if (readval)
902 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
903 readval);
904 else
905 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
906 writeval);
907
908 return ret;
909 }
910
ad7124_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)911 static int ad7124_update_scan_mode(struct iio_dev *indio_dev,
912 const unsigned long *scan_mask)
913 {
914 struct ad7124_state *st = iio_priv(indio_dev);
915 bool bit_set;
916 int ret;
917 int i;
918
919 guard(mutex)(&st->cfgs_lock);
920
921 for (i = 0; i < st->num_channels; i++) {
922 bit_set = test_bit(i, scan_mask);
923 if (bit_set)
924 ret = ad7124_prepare_read(st, i);
925 else
926 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_ENABLE,
927 0, 2);
928 if (ret < 0)
929 return ret;
930 }
931
932 return 0;
933 }
934
935 static const struct iio_info ad7124_info = {
936 .read_avail = ad7124_read_avail,
937 .read_raw = ad7124_read_raw,
938 .write_raw = ad7124_write_raw,
939 .debugfs_reg_access = &ad7124_reg_access,
940 .validate_trigger = ad_sd_validate_trigger,
941 .update_scan_mode = ad7124_update_scan_mode,
942 };
943
944 /* Only called during probe, so dev_err_probe() can be used */
ad7124_soft_reset(struct ad7124_state * st)945 static int ad7124_soft_reset(struct ad7124_state *st)
946 {
947 struct device *dev = &st->sd.spi->dev;
948 unsigned int readval, timeout;
949 int ret;
950
951 ret = ad_sd_reset(&st->sd);
952 if (ret < 0)
953 return ret;
954
955 fsleep(200);
956 timeout = 100;
957 do {
958 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
959 if (ret < 0)
960 return dev_err_probe(dev, ret, "Error reading status register\n");
961
962 if (!(readval & AD7124_STATUS_POR_FLAG))
963 break;
964
965 /* The AD7124 requires typically 2ms to power up and settle */
966 usleep_range(100, 2000);
967 } while (--timeout);
968
969 if (readval & AD7124_STATUS_POR_FLAG)
970 return dev_err_probe(dev, -EIO, "Soft reset failed\n");
971
972 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3, &st->gain_default);
973 if (ret < 0)
974 return dev_err_probe(dev, ret, "Error reading gain register\n");
975
976 dev_dbg(dev, "Reset value of GAIN register is 0x%x\n", st->gain_default);
977
978 return 0;
979 }
980
ad7124_check_chip_id(struct ad7124_state * st)981 static int ad7124_check_chip_id(struct ad7124_state *st)
982 {
983 struct device *dev = &st->sd.spi->dev;
984 unsigned int readval, chip_id, silicon_rev;
985 int ret;
986
987 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
988 if (ret < 0)
989 return dev_err_probe(dev, ret, "Failure to read ID register\n");
990
991 chip_id = FIELD_GET(AD7124_ID_DEVICE_ID, readval);
992 silicon_rev = FIELD_GET(AD7124_ID_SILICON_REVISION, readval);
993
994 if (chip_id != st->chip_info->chip_id)
995 return dev_err_probe(dev, -ENODEV,
996 "Chip ID mismatch: expected %u, got %u\n",
997 st->chip_info->chip_id, chip_id);
998
999 if (silicon_rev == 0)
1000 return dev_err_probe(dev, -ENODEV,
1001 "Silicon revision empty. Chip may not be present\n");
1002
1003 return 0;
1004 }
1005
1006 enum {
1007 AD7124_SYSCALIB_ZERO_SCALE,
1008 AD7124_SYSCALIB_FULL_SCALE,
1009 };
1010
ad7124_syscalib_locked(struct ad7124_state * st,const struct iio_chan_spec * chan)1011 static int ad7124_syscalib_locked(struct ad7124_state *st, const struct iio_chan_spec *chan)
1012 {
1013 struct device *dev = &st->sd.spi->dev;
1014 struct ad7124_channel *ch = &st->channels[chan->address];
1015 int ret;
1016
1017 if (ch->syscalib_mode == AD7124_SYSCALIB_ZERO_SCALE) {
1018 ch->cfg.calibration_offset = 0x800000;
1019
1020 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_SYS_OFFSET_CALIB,
1021 chan->address);
1022 if (ret < 0)
1023 return ret;
1024
1025 /*
1026 * Making the assumption that a single conversion will always
1027 * use configuration slot 0 for the OFFSET/GAIN registers.
1028 */
1029 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(0), 3,
1030 &ch->cfg.calibration_offset);
1031 if (ret < 0)
1032 return ret;
1033
1034 dev_dbg(dev, "offset for channel %lu after zero-scale calibration: 0x%x\n",
1035 chan->address, ch->cfg.calibration_offset);
1036 } else {
1037 ch->cfg.calibration_gain = st->gain_default;
1038
1039 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_SYS_GAIN_CALIB,
1040 chan->address);
1041 if (ret < 0)
1042 return ret;
1043
1044 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3,
1045 &ch->cfg.calibration_gain);
1046 if (ret < 0)
1047 return ret;
1048
1049 dev_dbg(dev, "gain for channel %lu after full-scale calibration: 0x%x\n",
1050 chan->address, ch->cfg.calibration_gain);
1051 }
1052
1053 return 0;
1054 }
1055
ad7124_write_syscalib(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)1056 static ssize_t ad7124_write_syscalib(struct iio_dev *indio_dev,
1057 uintptr_t private,
1058 const struct iio_chan_spec *chan,
1059 const char *buf, size_t len)
1060 {
1061 struct ad7124_state *st = iio_priv(indio_dev);
1062 bool sys_calib;
1063 int ret;
1064
1065 ret = kstrtobool(buf, &sys_calib);
1066 if (ret)
1067 return ret;
1068
1069 if (!sys_calib)
1070 return len;
1071
1072 if (!iio_device_claim_direct(indio_dev))
1073 return -EBUSY;
1074
1075 ret = ad7124_syscalib_locked(st, chan);
1076
1077 iio_device_release_direct(indio_dev);
1078
1079 return ret ?: len;
1080 }
1081
1082 static const char * const ad7124_syscalib_modes[] = {
1083 [AD7124_SYSCALIB_ZERO_SCALE] = "zero_scale",
1084 [AD7124_SYSCALIB_FULL_SCALE] = "full_scale",
1085 };
1086
ad7124_set_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)1087 static int ad7124_set_syscalib_mode(struct iio_dev *indio_dev,
1088 const struct iio_chan_spec *chan,
1089 unsigned int mode)
1090 {
1091 struct ad7124_state *st = iio_priv(indio_dev);
1092
1093 st->channels[chan->address].syscalib_mode = mode;
1094
1095 return 0;
1096 }
1097
ad7124_get_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)1098 static int ad7124_get_syscalib_mode(struct iio_dev *indio_dev,
1099 const struct iio_chan_spec *chan)
1100 {
1101 struct ad7124_state *st = iio_priv(indio_dev);
1102
1103 return st->channels[chan->address].syscalib_mode;
1104 }
1105
1106 static const struct iio_enum ad7124_syscalib_mode_enum = {
1107 .items = ad7124_syscalib_modes,
1108 .num_items = ARRAY_SIZE(ad7124_syscalib_modes),
1109 .set = ad7124_set_syscalib_mode,
1110 .get = ad7124_get_syscalib_mode
1111 };
1112
1113 static const char * const ad7124_filter_types[] = {
1114 [AD7124_FILTER_TYPE_SINC3] = "sinc3",
1115 [AD7124_FILTER_TYPE_SINC3_PF1] = "sinc3+pf1",
1116 [AD7124_FILTER_TYPE_SINC3_PF2] = "sinc3+pf2",
1117 [AD7124_FILTER_TYPE_SINC3_PF3] = "sinc3+pf3",
1118 [AD7124_FILTER_TYPE_SINC3_PF4] = "sinc3+pf4",
1119 [AD7124_FILTER_TYPE_SINC3_REJ60] = "sinc3+rej60",
1120 [AD7124_FILTER_TYPE_SINC3_SINC1] = "sinc3+sinc1",
1121 [AD7124_FILTER_TYPE_SINC4] = "sinc4",
1122 [AD7124_FILTER_TYPE_SINC4_REJ60] = "sinc4+rej60",
1123 [AD7124_FILTER_TYPE_SINC4_SINC1] = "sinc4+sinc1",
1124 };
1125
ad7124_set_filter_type_attr(struct iio_dev * dev,const struct iio_chan_spec * chan,unsigned int value)1126 static int ad7124_set_filter_type_attr(struct iio_dev *dev,
1127 const struct iio_chan_spec *chan,
1128 unsigned int value)
1129 {
1130 struct ad7124_state *st = iio_priv(dev);
1131 struct ad7124_channel_config *cfg = &st->channels[chan->address].cfg;
1132
1133 guard(mutex)(&st->cfgs_lock);
1134
1135 cfg->filter_type = value;
1136 ad7124_set_channel_odr(st, chan->address);
1137
1138 return 0;
1139 }
1140
ad7124_get_filter_type_attr(struct iio_dev * dev,const struct iio_chan_spec * chan)1141 static int ad7124_get_filter_type_attr(struct iio_dev *dev,
1142 const struct iio_chan_spec *chan)
1143 {
1144 struct ad7124_state *st = iio_priv(dev);
1145
1146 guard(mutex)(&st->cfgs_lock);
1147
1148 return st->channels[chan->address].cfg.filter_type;
1149 }
1150
1151 static const struct iio_enum ad7124_filter_type_enum = {
1152 .items = ad7124_filter_types,
1153 .num_items = ARRAY_SIZE(ad7124_filter_types),
1154 .set = ad7124_set_filter_type_attr,
1155 .get = ad7124_get_filter_type_attr,
1156 };
1157
1158 static const struct iio_chan_spec_ext_info ad7124_calibsys_ext_info[] = {
1159 {
1160 .name = "sys_calibration",
1161 .write = ad7124_write_syscalib,
1162 .shared = IIO_SEPARATE,
1163 },
1164 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
1165 &ad7124_syscalib_mode_enum),
1166 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
1167 &ad7124_syscalib_mode_enum),
1168 IIO_ENUM("filter_type", IIO_SEPARATE, &ad7124_filter_type_enum),
1169 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE,
1170 &ad7124_filter_type_enum),
1171 { }
1172 };
1173
1174 static const struct iio_chan_spec ad7124_channel_template = {
1175 .type = IIO_VOLTAGE,
1176 .indexed = 1,
1177 .differential = 1,
1178 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1179 BIT(IIO_CHAN_INFO_SCALE) |
1180 BIT(IIO_CHAN_INFO_OFFSET) |
1181 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
1182 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
1183 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE),
1184 .scan_type = {
1185 .sign = 'u',
1186 .realbits = 24,
1187 .storagebits = 32,
1188 .endianness = IIO_BE,
1189 },
1190 .ext_info = ad7124_calibsys_ext_info,
1191 };
1192
1193 /*
1194 * Input specifiers 8 - 15 are explicitly reserved for ad7124-4
1195 * while they are fine for ad7124-8. Values above 31 don't fit
1196 * into the register field and so are invalid for sure.
1197 */
ad7124_valid_input_select(unsigned int ain,const struct ad7124_chip_info * info)1198 static bool ad7124_valid_input_select(unsigned int ain, const struct ad7124_chip_info *info)
1199 {
1200 if (ain >= info->num_inputs && ain < 16)
1201 return false;
1202
1203 return ain <= FIELD_MAX(AD7124_CHANNEL_AINM);
1204 }
1205
ad7124_parse_channel_config(struct iio_dev * indio_dev,struct device * dev)1206 static int ad7124_parse_channel_config(struct iio_dev *indio_dev,
1207 struct device *dev)
1208 {
1209 struct ad7124_state *st = iio_priv(indio_dev);
1210 struct ad7124_channel_config *cfg;
1211 struct ad7124_channel *channels;
1212 struct iio_chan_spec *chan;
1213 unsigned int ain[2], channel = 0, tmp;
1214 unsigned int num_channels;
1215 int ret;
1216
1217 num_channels = device_get_child_node_count(dev);
1218
1219 /*
1220 * The driver assigns each logical channel defined in the device tree
1221 * statically one channel register. So only accept 16 such logical
1222 * channels to not treat CONFIG_0 (i.e. the register following
1223 * CHANNEL_15) as an additional channel register. The driver could be
1224 * improved to lift this limitation.
1225 */
1226 if (num_channels > AD7124_MAX_CHANNELS)
1227 return dev_err_probe(dev, -EINVAL, "Too many channels defined\n");
1228
1229 /* Add one for temperature */
1230 st->num_channels = min(num_channels + 1, AD7124_MAX_CHANNELS);
1231
1232 chan = devm_kcalloc(dev, st->num_channels,
1233 sizeof(*chan), GFP_KERNEL);
1234 if (!chan)
1235 return -ENOMEM;
1236
1237 channels = devm_kcalloc(dev, st->num_channels, sizeof(*channels),
1238 GFP_KERNEL);
1239 if (!channels)
1240 return -ENOMEM;
1241
1242 indio_dev->channels = chan;
1243 indio_dev->num_channels = st->num_channels;
1244 st->channels = channels;
1245
1246 device_for_each_child_node_scoped(dev, child) {
1247 ret = fwnode_property_read_u32(child, "reg", &channel);
1248 if (ret)
1249 return dev_err_probe(dev, ret,
1250 "Failed to parse reg property of %pfwP\n", child);
1251
1252 if (channel >= num_channels)
1253 return dev_err_probe(dev, -EINVAL,
1254 "Channel index >= number of channels in %pfwP\n", child);
1255
1256 ret = fwnode_property_read_u32_array(child, "diff-channels",
1257 ain, 2);
1258 if (ret)
1259 return dev_err_probe(dev, ret,
1260 "Failed to parse diff-channels property of %pfwP\n", child);
1261
1262 if (!ad7124_valid_input_select(ain[0], st->chip_info) ||
1263 !ad7124_valid_input_select(ain[1], st->chip_info))
1264 return dev_err_probe(dev, -EINVAL,
1265 "diff-channels property of %pfwP contains invalid data\n", child);
1266
1267 st->channels[channel].ain = FIELD_PREP(AD7124_CHANNEL_AINP, ain[0]) |
1268 FIELD_PREP(AD7124_CHANNEL_AINM, ain[1]);
1269
1270 cfg = &st->channels[channel].cfg;
1271 cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
1272
1273 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp);
1274 if (ret)
1275 cfg->refsel = AD7124_INT_REF;
1276 else
1277 cfg->refsel = tmp;
1278
1279 cfg->buf_positive =
1280 fwnode_property_read_bool(child, "adi,buffered-positive");
1281 cfg->buf_negative =
1282 fwnode_property_read_bool(child, "adi,buffered-negative");
1283
1284 chan[channel] = ad7124_channel_template;
1285 chan[channel].address = channel;
1286 chan[channel].scan_index = channel;
1287 chan[channel].channel = ain[0];
1288 chan[channel].channel2 = ain[1];
1289 }
1290
1291 if (num_channels < AD7124_MAX_CHANNELS) {
1292 st->channels[num_channels] = (struct ad7124_channel) {
1293 .ain = FIELD_PREP(AD7124_CHANNEL_AINP, AD7124_CHANNEL_AINx_TEMPSENSOR) |
1294 FIELD_PREP(AD7124_CHANNEL_AINM, AD7124_CHANNEL_AINx_AVSS),
1295 .cfg = {
1296 .bipolar = true,
1297 },
1298 };
1299
1300 chan[num_channels] = (struct iio_chan_spec) {
1301 .type = IIO_TEMP,
1302 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1303 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) |
1304 BIT(IIO_CHAN_INFO_SAMP_FREQ),
1305 .scan_type = {
1306 /*
1307 * You might find it strange that a bipolar
1308 * measurement yields an unsigned value, but
1309 * this matches the device's manual.
1310 */
1311 .sign = 'u',
1312 .realbits = 24,
1313 .storagebits = 32,
1314 .endianness = IIO_BE,
1315 },
1316 .address = num_channels,
1317 .scan_index = num_channels,
1318 .ext_info = ad7124_calibsys_ext_info,
1319 };
1320 }
1321
1322 return 0;
1323 }
1324
ad7124_setup(struct ad7124_state * st)1325 static int ad7124_setup(struct ad7124_state *st)
1326 {
1327 struct device *dev = &st->sd.spi->dev;
1328 unsigned int power_mode, clk_sel;
1329 struct clk *mclk;
1330 int i, ret;
1331
1332 /*
1333 * Always use full power mode for max performance. If needed, the driver
1334 * could be adapted to use a dynamic power mode based on the requested
1335 * output data rate.
1336 */
1337 power_mode = AD7124_ADC_CONTROL_POWER_MODE_FULL;
1338
1339 /*
1340 * This "mclk" business is needed for backwards compatibility with old
1341 * devicetrees that specified a fake clock named "mclk" to select the
1342 * power mode.
1343 */
1344 mclk = devm_clk_get_optional_enabled(dev, "mclk");
1345 if (IS_ERR(mclk))
1346 return dev_err_probe(dev, PTR_ERR(mclk), "Failed to get mclk\n");
1347
1348 if (mclk) {
1349 unsigned long mclk_hz;
1350
1351 mclk_hz = clk_get_rate(mclk);
1352 if (!mclk_hz)
1353 return dev_err_probe(dev, -EINVAL,
1354 "Failed to get mclk rate\n");
1355
1356 /*
1357 * This logic is a bit backwards, which is why it is only here
1358 * for backwards compatibility. The driver should be able to set
1359 * the power mode as it sees fit and the f_clk/mclk rate should
1360 * be dynamic accordingly. But here, we are selecting a fixed
1361 * power mode based on the given "mclk" rate.
1362 */
1363 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
1364 ARRAY_SIZE(ad7124_master_clk_freq_hz), mclk_hz);
1365
1366 if (mclk_hz != ad7124_master_clk_freq_hz[power_mode]) {
1367 ret = clk_set_rate(mclk, mclk_hz);
1368 if (ret)
1369 return dev_err_probe(dev, ret,
1370 "Failed to set mclk rate\n");
1371 }
1372
1373 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT;
1374 st->clk_hz = AD7124_INT_CLK_HZ;
1375 } else if (!device_property_present(dev, "clocks") &&
1376 device_property_present(dev, "#clock-cells")) {
1377 #ifdef CONFIG_COMMON_CLK
1378 struct clk_hw *clk_hw;
1379
1380 const char *name __free(kfree) = kasprintf(GFP_KERNEL, "%pfwP-clk",
1381 dev_fwnode(dev));
1382 if (!name)
1383 return -ENOMEM;
1384
1385 clk_hw = devm_clk_hw_register_fixed_rate(dev, name, NULL, 0,
1386 AD7124_INT_CLK_HZ);
1387 if (IS_ERR(clk_hw))
1388 return dev_err_probe(dev, PTR_ERR(clk_hw),
1389 "Failed to register clock provider\n");
1390
1391 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1392 clk_hw);
1393 if (ret)
1394 return dev_err_probe(dev, ret,
1395 "Failed to add clock provider\n");
1396 #endif
1397
1398 /*
1399 * Treat the clock as always on. This way we don't have to deal
1400 * with someone trying to enable/disable the clock while we are
1401 * reading samples.
1402 */
1403 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT_OUT;
1404 st->clk_hz = AD7124_INT_CLK_HZ;
1405 } else {
1406 struct clk *clk;
1407
1408 clk = devm_clk_get_optional_enabled(dev, NULL);
1409 if (IS_ERR(clk))
1410 return dev_err_probe(dev, PTR_ERR(clk),
1411 "Failed to get external clock\n");
1412
1413 if (clk) {
1414 unsigned long clk_hz;
1415
1416 clk_hz = clk_get_rate(clk);
1417 if (!clk_hz)
1418 return dev_err_probe(dev, -EINVAL,
1419 "Failed to get external clock rate\n");
1420
1421 /*
1422 * The external clock may be 4x the nominal clock rate,
1423 * in which case the ADC needs to be configured to
1424 * divide it by 4. Using MEGA is a bit arbitrary, but
1425 * the expected clock rates are either 614.4 kHz or
1426 * 2.4576 MHz, so this should work.
1427 */
1428 if (clk_hz > (1 * HZ_PER_MHZ)) {
1429 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_EXT_DIV4;
1430 st->clk_hz = clk_hz / 4;
1431 } else {
1432 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_EXT;
1433 st->clk_hz = clk_hz;
1434 }
1435 } else {
1436 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT;
1437 st->clk_hz = AD7124_INT_CLK_HZ;
1438 }
1439 }
1440
1441 st->adc_control &= ~AD7124_ADC_CONTROL_CLK_SEL;
1442 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_CLK_SEL, clk_sel);
1443
1444 st->adc_control &= ~AD7124_ADC_CONTROL_POWER_MODE;
1445 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_POWER_MODE, power_mode);
1446
1447 st->adc_control &= ~AD7124_ADC_CONTROL_MODE;
1448 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_MODE, AD_SD_MODE_IDLE);
1449
1450 ret = devm_mutex_init(dev, &st->cfgs_lock);
1451 if (ret)
1452 return ret;
1453
1454 for (i = 0; i < st->num_channels; i++) {
1455 struct ad7124_channel_config *cfg = &st->channels[i].cfg;
1456
1457 ret = ad7124_init_config_vref(st, cfg);
1458 if (ret < 0)
1459 return ret;
1460
1461 cfg->cfg_slot = AD7124_CFG_SLOT_UNASSIGNED;
1462
1463 /* Default filter type on the ADC after reset. */
1464 cfg->filter_type = AD7124_FILTER_TYPE_SINC4;
1465
1466 /*
1467 * 9.38 SPS is the minimum output data rate supported
1468 * regardless of the selected power mode. Round it up to 10 and
1469 * set all channels to this default value.
1470 */
1471 cfg->requested_odr = 10;
1472 ad7124_set_channel_odr(st, i);
1473 }
1474
1475 ad7124_disable_all(&st->sd);
1476
1477 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
1478 if (ret < 0)
1479 return dev_err_probe(dev, ret, "Failed to setup CONTROL register\n");
1480
1481 return ret;
1482 }
1483
__ad7124_calibrate_all(struct ad7124_state * st,struct iio_dev * indio_dev)1484 static int __ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev)
1485 {
1486 struct device *dev = &st->sd.spi->dev;
1487 int ret, i;
1488
1489 for (i = 0; i < st->num_channels; i++) {
1490 /*
1491 * For calibration the OFFSET register should hold its reset default
1492 * value. For the GAIN register there is no such requirement but
1493 * for gain 1 it should hold the reset default value, too. So to
1494 * simplify matters use the reset default value for both.
1495 */
1496 st->channels[i].cfg.calibration_offset = 0x800000;
1497 st->channels[i].cfg.calibration_gain = st->gain_default;
1498
1499 /*
1500 * Only the main voltage input channels are important enough
1501 * to be automatically calibrated here. For everything else,
1502 * just use the default values set above.
1503 */
1504 if (indio_dev->channels[i].type != IIO_VOLTAGE)
1505 continue;
1506
1507 /*
1508 * Full-scale calibration isn't supported at gain 1, so skip in
1509 * that case. Note that untypically full-scale calibration has
1510 * to happen before zero-scale calibration. This only applies to
1511 * the internal calibration. For system calibration it's as
1512 * usual: first zero-scale then full-scale calibration.
1513 */
1514 if (st->channels[i].cfg.pga_bits > 0) {
1515 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_INT_GAIN_CALIB, i);
1516 if (ret < 0)
1517 return ret;
1518
1519 /*
1520 * read out the resulting value of GAIN
1521 * after full-scale calibration because the next
1522 * ad_sd_calibrate() call overwrites this via
1523 * ad_sigma_delta_set_channel() -> ad7124_set_channel()
1524 * -> ad7124_prepare_read().
1525 */
1526 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3,
1527 &st->channels[i].cfg.calibration_gain);
1528 if (ret < 0)
1529 return ret;
1530 }
1531
1532 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_INT_OFFSET_CALIB, i);
1533 if (ret < 0)
1534 return ret;
1535
1536 /*
1537 * Making the assumption that a single conversion will always
1538 * use configuration slot 0 for the OFFSET/GAIN registers.
1539 */
1540 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(0), 3,
1541 &st->channels[i].cfg.calibration_offset);
1542 if (ret < 0)
1543 return ret;
1544
1545 dev_dbg(dev, "offset and gain for channel %d = 0x%x + 0x%x\n", i,
1546 st->channels[i].cfg.calibration_offset,
1547 st->channels[i].cfg.calibration_gain);
1548 }
1549
1550 return 0;
1551 }
1552
ad7124_calibrate_all(struct ad7124_state * st,struct iio_dev * indio_dev)1553 static int ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev)
1554 {
1555 int ret;
1556 unsigned int adc_control = st->adc_control;
1557
1558 /*
1559 * Calibration isn't supported at full power, so speed down a bit.
1560 * Setting .adc_control is enough here because the control register is
1561 * written as part of ad_sd_calibrate() -> ad_sigma_delta_set_mode().
1562 * The resulting calibration is then also valid for high-speed, so just
1563 * restore adc_control afterwards.
1564 */
1565 if (FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, adc_control) >= AD7124_FULL_POWER) {
1566 st->adc_control &= ~AD7124_ADC_CONTROL_POWER_MODE;
1567 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_POWER_MODE, AD7124_MID_POWER);
1568 }
1569
1570 ret = __ad7124_calibrate_all(st, indio_dev);
1571
1572 st->adc_control = adc_control;
1573
1574 return ret;
1575 }
1576
ad7124_reg_disable(void * r)1577 static void ad7124_reg_disable(void *r)
1578 {
1579 regulator_disable(r);
1580 }
1581
ad7124_debugfs_init(struct iio_dev * indio_dev)1582 static void ad7124_debugfs_init(struct iio_dev *indio_dev)
1583 {
1584 struct dentry *dentry = iio_get_debugfs_dentry(indio_dev);
1585 struct ad7124_state *st = iio_priv(indio_dev);
1586
1587 if (!IS_ENABLED(CONFIG_DEBUG_FS))
1588 return;
1589
1590 debugfs_create_bool("enable_single_cycle", 0644, dentry,
1591 &st->enable_single_cycle);
1592 }
1593
ad7124_probe(struct spi_device * spi)1594 static int ad7124_probe(struct spi_device *spi)
1595 {
1596 const struct ad7124_chip_info *info;
1597 struct device *dev = &spi->dev;
1598 struct ad7124_state *st;
1599 struct iio_dev *indio_dev;
1600 int i, ret;
1601
1602 info = spi_get_device_match_data(spi);
1603 if (!info)
1604 return dev_err_probe(dev, -ENODEV, "Failed to get match data\n");
1605
1606 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1607 if (!indio_dev)
1608 return -ENOMEM;
1609
1610 st = iio_priv(indio_dev);
1611
1612 st->chip_info = info;
1613
1614 /* Only disabled for debug/testing purposes. */
1615 st->enable_single_cycle = true;
1616
1617 indio_dev->name = st->chip_info->name;
1618 indio_dev->modes = INDIO_DIRECT_MODE;
1619 indio_dev->info = &ad7124_info;
1620
1621 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
1622 if (ret < 0)
1623 return ret;
1624
1625 ret = ad7124_parse_channel_config(indio_dev, &spi->dev);
1626 if (ret < 0)
1627 return ret;
1628
1629 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
1630 if (i == AD7124_INT_REF)
1631 continue;
1632
1633 st->vref[i] = devm_regulator_get_optional(&spi->dev,
1634 ad7124_ref_names[i]);
1635 if (PTR_ERR(st->vref[i]) == -ENODEV)
1636 continue;
1637 else if (IS_ERR(st->vref[i]))
1638 return PTR_ERR(st->vref[i]);
1639
1640 ret = regulator_enable(st->vref[i]);
1641 if (ret)
1642 return dev_err_probe(dev, ret, "Failed to enable regulator #%d\n", i);
1643
1644 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
1645 st->vref[i]);
1646 if (ret)
1647 return ret;
1648 }
1649
1650 ret = ad7124_soft_reset(st);
1651 if (ret < 0)
1652 return ret;
1653
1654 ret = ad7124_check_chip_id(st);
1655 if (ret)
1656 return ret;
1657
1658 ret = ad7124_setup(st);
1659 if (ret < 0)
1660 return ret;
1661
1662 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1663 if (ret < 0)
1664 return dev_err_probe(dev, ret, "Failed to setup triggers\n");
1665
1666 ret = ad7124_calibrate_all(st, indio_dev);
1667 if (ret)
1668 return ret;
1669
1670 ret = devm_iio_device_register(&spi->dev, indio_dev);
1671 if (ret < 0)
1672 return dev_err_probe(dev, ret, "Failed to register iio device\n");
1673
1674 ad7124_debugfs_init(indio_dev);
1675
1676 return 0;
1677 }
1678
1679 static const struct of_device_id ad7124_of_match[] = {
1680 { .compatible = "adi,ad7124-4", .data = &ad7124_4_chip_info },
1681 { .compatible = "adi,ad7124-8", .data = &ad7124_8_chip_info },
1682 { }
1683 };
1684 MODULE_DEVICE_TABLE(of, ad7124_of_match);
1685
1686 static const struct spi_device_id ad71124_ids[] = {
1687 { "ad7124-4", (kernel_ulong_t)&ad7124_4_chip_info },
1688 { "ad7124-8", (kernel_ulong_t)&ad7124_8_chip_info },
1689 { }
1690 };
1691 MODULE_DEVICE_TABLE(spi, ad71124_ids);
1692
1693 static struct spi_driver ad71124_driver = {
1694 .driver = {
1695 .name = "ad7124",
1696 .of_match_table = ad7124_of_match,
1697 },
1698 .probe = ad7124_probe,
1699 .id_table = ad71124_ids,
1700 };
1701 module_spi_driver(ad71124_driver);
1702
1703 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1704 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
1705 MODULE_LICENSE("GPL");
1706 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
1707