1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Analog Devices AD4170-4 ADC driver 4 * 5 * Copyright (C) 2025 Analog Devices, Inc. 6 * Author: Ana-Maria Cusco <ana-maria.cusco@analog.com> 7 * Author: Marcelo Schmitt <marcelo.schmitt@analog.com> 8 */ 9 10 #include <linux/array_size.h> 11 #include <linux/bitfield.h> 12 #include <linux/bitmap.h> 13 #include <linux/bitops.h> 14 #include <linux/bits.h> 15 #include <linux/cleanup.h> 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/err.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/iio.h> 24 #include <linux/iio/trigger.h> 25 #include <linux/iio/trigger_consumer.h> 26 #include <linux/iio/triggered_buffer.h> 27 #include <linux/interrupt.h> 28 #include <linux/irq.h> 29 #include <linux/math64.h> 30 #include <linux/minmax.h> 31 #include <linux/module.h> 32 #include <linux/property.h> 33 #include <linux/regmap.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/spi/spi.h> 36 #include <linux/time.h> 37 #include <linux/types.h> 38 #include <linux/unaligned.h> 39 #include <linux/units.h> 40 #include <linux/util_macros.h> 41 42 /* 43 * AD4170 registers 44 * Multibyte register addresses point to the most significant byte which is the 45 * address to use to get the most significant byte first (address accessed is 46 * decremented by one for each data byte) 47 * 48 * Each register address define follows the AD4170_<REG_NAME>_REG format. 49 * Each mask follows the AD4170_<REG_NAME>_<FIELD_NAME> format. 50 * E.g. AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK is for accessing DIG_AUX1_CTRL field 51 * of PIN_MUXING_REG. 52 * Each constant follows the AD4170_<REG_NAME>_<FIELD_NAME>_<FUNCTION> format. 53 * E.g. AD4170_PIN_MUXING_DIG_AUX1_DISABLED is the value written to 54 * DIG_AUX1_CTRL field of PIN_MUXING register to disable DIG_AUX1 pin. 55 * Some register names and register field names are shortened versions of 56 * their datasheet counterpart names to provide better code readability. 57 */ 58 #define AD4170_CONFIG_A_REG 0x00 59 #define AD4170_DATA_24B_REG 0x1E 60 #define AD4170_PIN_MUXING_REG 0x69 61 #define AD4170_CLOCK_CTRL_REG 0x6B 62 #define AD4170_ADC_CTRL_REG 0x71 63 #define AD4170_CHAN_EN_REG 0x79 64 #define AD4170_CHAN_SETUP_REG(x) (0x81 + 4 * (x)) 65 #define AD4170_CHAN_MAP_REG(x) (0x83 + 4 * (x)) 66 #define AD4170_MISC_REG(x) (0xC1 + 14 * (x)) 67 #define AD4170_AFE_REG(x) (0xC3 + 14 * (x)) 68 #define AD4170_FILTER_REG(x) (0xC5 + 14 * (x)) 69 #define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x)) 70 #define AD4170_OFFSET_REG(x) (0xCA + 14 * (x)) 71 #define AD4170_GAIN_REG(x) (0xCD + 14 * (x)) 72 #define AD4170_V_BIAS_REG 0x135 73 #define AD4170_CURRENT_SRC_REG(x) (0x139 + 2 * (x)) 74 #define AD4170_GPIO_MODE_REG 0x191 75 #define AD4170_GPIO_OUTPUT_REG 0x193 76 #define AD4170_GPIO_INPUT_REG 0x195 77 #define AD4170_ADC_CTRL_CONT_READ_EXIT_REG 0x200 /* virtual reg */ 78 79 #define AD4170_REG_READ_MASK BIT(14) 80 81 /* AD4170_CONFIG_A_REG - INTERFACE_CONFIG_A REGISTER */ 82 #define AD4170_SW_RESET_MSK (BIT(7) | BIT(0)) 83 84 /* AD4170_PIN_MUXING_REG */ 85 #define AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK GENMASK(5, 4) 86 87 /* AD4170_CLOCK_CTRL_REG */ 88 #define AD4170_CLOCK_CTRL_CLOCKSEL_MSK GENMASK(1, 0) 89 90 /* AD4170_ADC_CTRL_REG */ 91 #define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK BIT(7) 92 #define AD4170_ADC_CTRL_CONT_READ_MSK GENMASK(5, 4) 93 #define AD4170_ADC_CTRL_MODE_MSK GENMASK(3, 0) 94 95 /* AD4170_CHAN_EN_REG */ 96 #define AD4170_CHAN_EN(ch) BIT(ch) 97 98 /* AD4170_CHAN_SETUP_REG */ 99 #define AD4170_CHAN_SETUP_SETUP_MSK GENMASK(2, 0) 100 101 /* AD4170_CHAN_MAP_REG */ 102 #define AD4170_CHAN_MAP_AINP_MSK GENMASK(12, 8) 103 #define AD4170_CHAN_MAP_AINM_MSK GENMASK(4, 0) 104 105 /* AD4170_MISC_REG */ 106 #define AD4170_MISC_CHOP_IEXC_MSK GENMASK(15, 14) 107 #define AD4170_MISC_CHOP_ADC_MSK GENMASK(9, 8) 108 109 /* AD4170_AFE_REG */ 110 #define AD4170_AFE_REF_BUF_M_MSK GENMASK(11, 10) 111 #define AD4170_AFE_REF_BUF_P_MSK GENMASK(9, 8) 112 #define AD4170_AFE_REF_SELECT_MSK GENMASK(6, 5) 113 #define AD4170_AFE_BIPOLAR_MSK BIT(4) 114 #define AD4170_AFE_PGA_GAIN_MSK GENMASK(3, 0) 115 116 /* AD4170_FILTER_REG */ 117 #define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0) 118 119 /* AD4170_CURRENT_SRC_REG */ 120 #define AD4170_CURRENT_SRC_I_OUT_PIN_MSK GENMASK(12, 8) 121 #define AD4170_CURRENT_SRC_I_OUT_VAL_MSK GENMASK(2, 0) 122 123 /* AD4170_GPIO_MODE_REG */ 124 #define AD4170_GPIO_MODE_GPIO0_MSK GENMASK(1, 0) 125 #define AD4170_GPIO_MODE_GPIO1_MSK GENMASK(3, 2) 126 #define AD4170_GPIO_MODE_GPIO2_MSK GENMASK(5, 4) 127 #define AD4170_GPIO_MODE_GPIO3_MSK GENMASK(7, 6) 128 129 /* AD4170_GPIO_OUTPUT_REG */ 130 #define AD4170_GPIO_OUTPUT_GPIO_MSK(x) BIT(x) 131 132 /* AD4170 register constants */ 133 134 /* AD4170_CLOCK_CTRL_REG constants */ 135 #define AD4170_CLOCK_CTRL_CLOCKSEL_INT 0x0 136 #define AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT 0x1 137 #define AD4170_CLOCK_CTRL_CLOCKSEL_EXT 0x2 138 #define AD4170_CLOCK_CTRL_CLOCKSEL_EXT_XTAL 0x3 139 140 /* AD4170_CHAN_MAP_REG constants */ 141 #define AD4170_CHAN_MAP_AIN(x) (x) 142 #define AD4170_CHAN_MAP_TEMP_SENSOR 17 143 #define AD4170_CHAN_MAP_AVDD_AVSS_P 18 144 #define AD4170_CHAN_MAP_AVDD_AVSS_N 18 145 #define AD4170_CHAN_MAP_IOVDD_DGND_P 19 146 #define AD4170_CHAN_MAP_IOVDD_DGND_N 19 147 #define AD4170_CHAN_MAP_AVSS 23 148 #define AD4170_CHAN_MAP_DGND 24 149 #define AD4170_CHAN_MAP_REFIN1_P 25 150 #define AD4170_CHAN_MAP_REFIN1_N 26 151 #define AD4170_CHAN_MAP_REFIN2_P 27 152 #define AD4170_CHAN_MAP_REFIN2_N 28 153 #define AD4170_CHAN_MAP_REFOUT 29 154 155 /* AD4170_MISC_REG constants */ 156 #define AD4170_MISC_CHOP_IEXC_PAIR1 0x1 157 #define AD4170_MISC_CHOP_IEXC_PAIR2 0x2 158 #define AD4170_MISC_CHOP_IEXC_BOTH 0x3 159 160 /* AD4170_PIN_MUXING_REG constants */ 161 #define AD4170_PIN_MUXING_DIG_AUX1_DISABLED 0x0 162 #define AD4170_PIN_MUXING_DIG_AUX1_RDY 0x1 163 164 /* AD4170_ADC_CTRL_REG constants */ 165 #define AD4170_ADC_CTRL_MODE_CONT 0x0 166 #define AD4170_ADC_CTRL_MODE_SINGLE 0x4 167 #define AD4170_ADC_CTRL_MODE_IDLE 0x7 168 169 #define AD4170_ADC_CTRL_CONT_READ_DISABLE 0x0 170 #define AD4170_ADC_CTRL_CONT_READ_ENABLE 0x1 171 172 /* AD4170_FILTER_REG constants */ 173 #define AD4170_FILTER_FILTER_TYPE_SINC5_AVG 0x0 174 #define AD4170_FILTER_FILTER_TYPE_SINC5 0x4 175 #define AD4170_FILTER_FILTER_TYPE_SINC3 0x6 176 177 /* AD4170_CURRENT_SRC_REG constants */ 178 #define AD4170_CURRENT_SRC_I_OUT_PIN_AIN(x) (x) 179 #define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(x) ((x) + 17) 180 181 /* AD4170_GPIO_MODE_REG constants */ 182 #define AD4170_GPIO_MODE_GPIO_INPUT 1 183 #define AD4170_GPIO_MODE_GPIO_OUTPUT 2 184 185 /* Device properties and auxiliary constants */ 186 187 #define AD4170_NUM_ANALOG_PINS 9 188 #define AD4170_NUM_GPIO_PINS 4 189 #define AD4170_MAX_ADC_CHANNELS 16 190 #define AD4170_MAX_IIO_CHANNELS (AD4170_MAX_ADC_CHANNELS + 1) 191 #define AD4170_MAX_ANALOG_PINS 8 192 #define AD4170_MAX_SETUPS 8 193 #define AD4170_INVALID_SETUP 9 194 #define AD4170_SPI_INST_PHASE_LEN 2 195 #define AD4170_SPI_MAX_XFER_LEN 6 196 #define AD4170_NUM_CURRENT_SRC 4 197 #define AD4170_DEFAULT_SAMP_RATE (125 * HZ_PER_KHZ) 198 199 #define AD4170_INT_REF_2_5V 2500000 200 201 /* Internal and external clock properties */ 202 #define AD4170_INT_CLOCK_16MHZ (16 * HZ_PER_MHZ) 203 #define AD4170_EXT_CLOCK_MHZ_MIN (1 * HZ_PER_MHZ) 204 #define AD4170_EXT_CLOCK_MHZ_MAX (17 * HZ_PER_MHZ) 205 206 #define AD4170_NUM_PGA_OPTIONS 10 207 208 /* Digital filter properties */ 209 #define AD4170_SINC3_MIN_FS 4 210 #define AD4170_SINC3_MAX_FS 65532 211 #define AD4170_SINC5_MIN_FS 1 212 #define AD4170_SINC5_MAX_FS 256 213 214 #define AD4170_GAIN_REG_DEFAULT 0x555555 215 216 #define AD4170_ADC_CTRL_CONT_READ_EXIT 0xA5 217 218 /* Analog pin functions */ 219 #define AD4170_PIN_UNASSIGNED 0x00 220 #define AD4170_PIN_ANALOG_IN 0x01 221 #define AD4170_PIN_CURRENT_OUT 0x02 222 #define AD4170_PIN_VBIAS 0x04 223 224 /* GPIO pin functions */ 225 #define AD4170_GPIO_UNASSIGNED 0x00 226 #define AD4170_GPIO_AC_EXCITATION 0x02 227 #define AD4170_GPIO_OUTPUT 0x04 228 229 /* Current source */ 230 #define AD4170_CURRENT_SRC_DISABLED 0xFF 231 232 static const unsigned int ad4170_reg_size[] = { 233 [AD4170_CONFIG_A_REG] = 1, 234 [AD4170_DATA_24B_REG] = 3, 235 [AD4170_PIN_MUXING_REG] = 2, 236 [AD4170_CLOCK_CTRL_REG] = 2, 237 [AD4170_ADC_CTRL_REG] = 2, 238 [AD4170_CHAN_EN_REG] = 2, 239 /* 240 * CHANNEL_SETUP and CHANNEL_MAP register are all 2 byte size each and 241 * their addresses are interleaved such that we have CHANNEL_SETUP0 242 * address followed by CHANNEL_MAP0 address, followed by CHANNEL_SETUP1, 243 * and so on until CHANNEL_MAP15. 244 * Thus, initialize the register size for them only once. 245 */ 246 [AD4170_CHAN_SETUP_REG(0) ... AD4170_CHAN_MAP_REG(AD4170_MAX_ADC_CHANNELS - 1)] = 2, 247 /* 248 * MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN register addresses are 249 * also interleaved but MISC, AFE, FILTER, FILTER_FS, OFFSET are 16-bit 250 * while OFFSET, GAIN are 24-bit registers so we can't init them all to 251 * the same size. 252 */ 253 [AD4170_MISC_REG(0) ... AD4170_FILTER_FS_REG(0)] = 2, 254 [AD4170_MISC_REG(1) ... AD4170_FILTER_FS_REG(1)] = 2, 255 [AD4170_MISC_REG(2) ... AD4170_FILTER_FS_REG(2)] = 2, 256 [AD4170_MISC_REG(3) ... AD4170_FILTER_FS_REG(3)] = 2, 257 [AD4170_MISC_REG(4) ... AD4170_FILTER_FS_REG(4)] = 2, 258 [AD4170_MISC_REG(5) ... AD4170_FILTER_FS_REG(5)] = 2, 259 [AD4170_MISC_REG(6) ... AD4170_FILTER_FS_REG(6)] = 2, 260 [AD4170_MISC_REG(7) ... AD4170_FILTER_FS_REG(7)] = 2, 261 [AD4170_OFFSET_REG(0) ... AD4170_GAIN_REG(0)] = 3, 262 [AD4170_OFFSET_REG(1) ... AD4170_GAIN_REG(1)] = 3, 263 [AD4170_OFFSET_REG(2) ... AD4170_GAIN_REG(2)] = 3, 264 [AD4170_OFFSET_REG(3) ... AD4170_GAIN_REG(3)] = 3, 265 [AD4170_OFFSET_REG(4) ... AD4170_GAIN_REG(4)] = 3, 266 [AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3, 267 [AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3, 268 [AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3, 269 [AD4170_V_BIAS_REG] = 2, 270 [AD4170_CURRENT_SRC_REG(0) ... AD4170_CURRENT_SRC_REG(3)] = 2, 271 [AD4170_GPIO_MODE_REG] = 2, 272 [AD4170_GPIO_OUTPUT_REG] = 2, 273 [AD4170_GPIO_INPUT_REG] = 2, 274 [AD4170_ADC_CTRL_CONT_READ_EXIT_REG] = 0, 275 }; 276 277 enum ad4170_ref_buf { 278 AD4170_REF_BUF_PRE, /* Pre-charge reference buffer */ 279 AD4170_REF_BUF_FULL, /* Full reference buffering */ 280 AD4170_REF_BUF_BYPASS, /* Bypass reference buffering */ 281 }; 282 283 /* maps adi,positive/negative-reference-buffer property values to enum */ 284 static const char * const ad4170_ref_buf_str[] = { 285 [AD4170_REF_BUF_PRE] = "precharge", 286 [AD4170_REF_BUF_FULL] = "full", 287 [AD4170_REF_BUF_BYPASS] = "disabled", 288 }; 289 290 enum ad4170_ref_select { 291 AD4170_REF_REFIN1, 292 AD4170_REF_REFIN2, 293 AD4170_REF_REFOUT, 294 AD4170_REF_AVDD, 295 }; 296 297 enum ad4170_filter_type { 298 AD4170_SINC5_AVG, 299 AD4170_SINC5, 300 AD4170_SINC3, 301 }; 302 303 enum ad4170_regulator { 304 AD4170_AVDD_SUP, 305 AD4170_AVSS_SUP, 306 AD4170_IOVDD_SUP, 307 AD4170_REFIN1P_SUP, 308 AD4170_REFIN1N_SUP, 309 AD4170_REFIN2P_SUP, 310 AD4170_REFIN2N_SUP, 311 AD4170_MAX_SUP, 312 }; 313 314 static const char *const ad4170_clk_sel[] = { 315 "ext-clk", "xtal", 316 }; 317 318 enum ad4170_int_pin_sel { 319 AD4170_INT_PIN_SDO, 320 AD4170_INT_PIN_DIG_AUX1, 321 }; 322 323 static const char * const ad4170_int_pin_names[] = { 324 [AD4170_INT_PIN_SDO] = "sdo", 325 [AD4170_INT_PIN_DIG_AUX1] = "dig_aux1", 326 }; 327 328 static const unsigned int ad4170_sinc3_filt_fs_tbl[] = { 329 4, 8, 12, 16, 20, 40, 48, 80, /* 0 - 7 */ 330 100, 256, 500, 1000, 5000, 8332, 10000, 25000, /* 8 - 15 */ 331 50000, 65532, /* 16 - 17 */ 332 }; 333 334 #define AD4170_MAX_FS_TBL_SIZE ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl) 335 336 static const unsigned int ad4170_sinc5_filt_fs_tbl[] = { 337 1, 2, 4, 8, 12, 16, 20, 40, 48, 80, 100, 256, 338 }; 339 340 static const unsigned int ad4170_iout_pin_tbl[] = { 341 AD4170_CURRENT_SRC_I_OUT_PIN_AIN(0), 342 AD4170_CURRENT_SRC_I_OUT_PIN_AIN(1), 343 AD4170_CURRENT_SRC_I_OUT_PIN_AIN(2), 344 AD4170_CURRENT_SRC_I_OUT_PIN_AIN(3), 345 AD4170_CURRENT_SRC_I_OUT_PIN_AIN(4), 346 AD4170_CURRENT_SRC_I_OUT_PIN_AIN(5), 347 AD4170_CURRENT_SRC_I_OUT_PIN_AIN(6), 348 AD4170_CURRENT_SRC_I_OUT_PIN_AIN(7), 349 AD4170_CURRENT_SRC_I_OUT_PIN_AIN(8), 350 AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(0), 351 AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(1), 352 AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(2), 353 AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(3), 354 }; 355 356 static const unsigned int ad4170_iout_current_ua_tbl[] = { 357 0, 10, 50, 100, 250, 500, 1000, 1500, 358 }; 359 360 enum ad4170_sensor_enum { 361 AD4170_ADC_SENSOR = 0, 362 AD4170_WEIGH_SCALE_SENSOR = 1, 363 AD4170_RTD_SENSOR = 2, 364 AD4170_THERMOCOUPLE_SENSOR = 3, 365 }; 366 367 /* maps adi,sensor-type property value to enum */ 368 static const char * const ad4170_sensor_type[] = { 369 [AD4170_ADC_SENSOR] = "adc", 370 [AD4170_WEIGH_SCALE_SENSOR] = "weighscale", 371 [AD4170_RTD_SENSOR] = "rtd", 372 [AD4170_THERMOCOUPLE_SENSOR] = "thermocouple", 373 }; 374 375 struct ad4170_chip_info { 376 const char *name; 377 }; 378 379 static const struct ad4170_chip_info ad4170_chip_info = { 380 .name = "ad4170-4", 381 }; 382 383 static const struct ad4170_chip_info ad4190_chip_info = { 384 .name = "ad4190-4", 385 }; 386 387 static const struct ad4170_chip_info ad4195_chip_info = { 388 .name = "ad4195-4", 389 }; 390 391 /* 392 * There are 8 of each MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN 393 * configuration registers. That is, there are 8 miscellaneous registers, MISC0 394 * to MISC7. Each MISC register is associated with a setup; MISCN is associated 395 * with setup number N. The other 5 above mentioned types of registers have 396 * analogous structure. A setup is a set of those registers. For example, 397 * setup 1 comprises of MISC1, AFE1, FILTER1, FILTER_FS1, OFFSET1, and GAIN1 398 * registers. Also, there are 16 CHANNEL_SETUP registers (CHANNEL_SETUP0 to 399 * CHANNEL_SETUP15). Each channel setup is associated with one of the 8 possible 400 * setups. Thus, AD4170 can support up to 16 channels but, since there are only 401 * 8 available setups, channels must share settings if more than 8 channels are 402 * configured. 403 * 404 * If this struct is modified, ad4170_setup_eq() will probably need to be 405 * updated too. 406 */ 407 struct ad4170_setup { 408 u16 misc; 409 u16 afe; 410 u16 filter; 411 u16 filter_fs; 412 u32 offset; /* For calibration purposes */ 413 u32 gain; /* For calibration purposes */ 414 }; 415 416 struct ad4170_setup_info { 417 struct ad4170_setup setup; 418 unsigned int enabled_channels; 419 unsigned int channels; 420 }; 421 422 struct ad4170_chan_info { 423 unsigned int input_range_uv; 424 unsigned int setup_num; /* Index to access state setup_infos array */ 425 struct ad4170_setup setup; /* cached setup */ 426 int offset_tbl[10]; 427 u32 scale_tbl[10][2]; 428 bool initialized; 429 bool enabled; 430 }; 431 432 static const char * const ad4170_filt_names[] = { 433 [AD4170_SINC5_AVG] = "sinc5+avg", 434 [AD4170_SINC5] = "sinc5", 435 [AD4170_SINC3] = "sinc3", 436 }; 437 438 struct ad4170_state { 439 struct mutex lock; /* Protect read-modify-write and multi write sequences */ 440 int vrefs_uv[AD4170_MAX_SUP]; 441 u32 mclk_hz; 442 struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS]; 443 struct ad4170_chan_info chan_infos[AD4170_MAX_ADC_CHANNELS]; 444 struct completion completion; 445 struct iio_chan_spec chans[AD4170_MAX_IIO_CHANNELS]; 446 struct spi_device *spi; 447 struct regmap *regmap; 448 int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2]; 449 __be32 bounce_buffer[AD4170_MAX_ADC_CHANNELS]; 450 struct spi_message msg; 451 struct spi_transfer xfer; 452 struct iio_trigger *trig; 453 struct clk_hw int_clk_hw; 454 unsigned int clock_ctrl; 455 unsigned int pins_fn[AD4170_NUM_ANALOG_PINS]; 456 int gpio_fn[AD4170_NUM_GPIO_PINS]; 457 unsigned int cur_src_pins[AD4170_NUM_CURRENT_SRC]; 458 struct gpio_chip gpiochip; 459 /* 460 * DMA (thus cache coherency maintenance) requires the transfer buffers 461 * to live in their own cache lines. 462 */ 463 u8 rx_buf[4] __aligned(IIO_DMA_MINALIGN); 464 }; 465 466 static void ad4170_fill_sps_tbl(struct ad4170_state *st) 467 { 468 unsigned int tmp0, tmp1, i; 469 470 /* 471 * The ODR can be calculated the same way for sinc5+avg, sinc5, and 472 * sinc3 filter types with the exception that sinc5 filter has a 473 * narrowed range of allowed FILTER_FS values. 474 */ 475 for (i = 0; i < ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl); i++) { 476 tmp0 = div_u64_rem(st->mclk_hz, 32 * ad4170_sinc3_filt_fs_tbl[i], 477 &tmp1); 478 tmp1 = mult_frac(tmp1, MICRO, 32 * ad4170_sinc3_filt_fs_tbl[i]); 479 /* Fill sinc5+avg filter SPS table */ 480 st->sps_tbl[AD4170_SINC5_AVG][i][0] = tmp0; /* Integer part */ 481 st->sps_tbl[AD4170_SINC5_AVG][i][1] = tmp1; /* Fractional part */ 482 483 /* Fill sinc3 filter SPS table */ 484 st->sps_tbl[AD4170_SINC3][i][0] = tmp0; /* Integer part */ 485 st->sps_tbl[AD4170_SINC3][i][1] = tmp1; /* Fractional part */ 486 } 487 /* Sinc5 filter ODR doesn't use all FILTER_FS bits */ 488 for (i = 0; i < ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl); i++) { 489 tmp0 = div_u64_rem(st->mclk_hz, 32 * ad4170_sinc5_filt_fs_tbl[i], 490 &tmp1); 491 tmp1 = mult_frac(tmp1, MICRO, 32 * ad4170_sinc5_filt_fs_tbl[i]); 492 /* Fill sinc5 filter SPS table */ 493 st->sps_tbl[AD4170_SINC5][i][0] = tmp0; /* Integer part */ 494 st->sps_tbl[AD4170_SINC5][i][1] = tmp1; /* Fractional part */ 495 } 496 } 497 498 static int ad4170_debugfs_reg_access(struct iio_dev *indio_dev, 499 unsigned int reg, unsigned int writeval, 500 unsigned int *readval) 501 { 502 struct ad4170_state *st = iio_priv(indio_dev); 503 504 if (readval) 505 return regmap_read(st->regmap, reg, readval); 506 507 return regmap_write(st->regmap, reg, writeval); 508 } 509 510 static int ad4170_get_reg_size(struct ad4170_state *st, unsigned int reg, 511 unsigned int *size) 512 { 513 if (reg >= ARRAY_SIZE(ad4170_reg_size)) 514 return -EINVAL; 515 516 *size = ad4170_reg_size[reg]; 517 518 return 0; 519 } 520 521 static int ad4170_reg_write(void *context, unsigned int reg, unsigned int val) 522 { 523 struct ad4170_state *st = context; 524 u8 tx_buf[AD4170_SPI_MAX_XFER_LEN]; 525 unsigned int size; 526 int ret; 527 528 ret = ad4170_get_reg_size(st, reg, &size); 529 if (ret) 530 return ret; 531 532 put_unaligned_be16(reg, tx_buf); 533 switch (size) { 534 case 3: 535 put_unaligned_be24(val, &tx_buf[AD4170_SPI_INST_PHASE_LEN]); 536 break; 537 case 2: 538 put_unaligned_be16(val, &tx_buf[AD4170_SPI_INST_PHASE_LEN]); 539 break; 540 case 1: 541 tx_buf[AD4170_SPI_INST_PHASE_LEN] = val; 542 break; 543 case 0: 544 /* Write continuous read exit code */ 545 tx_buf[0] = AD4170_ADC_CTRL_CONT_READ_EXIT; 546 return spi_write_then_read(st->spi, tx_buf, 1, NULL, 0); 547 default: 548 return -EINVAL; 549 } 550 551 return spi_write_then_read(st->spi, tx_buf, 552 AD4170_SPI_INST_PHASE_LEN + size, NULL, 0); 553 } 554 555 static int ad4170_reg_read(void *context, unsigned int reg, unsigned int *val) 556 { 557 struct ad4170_state *st = context; 558 u8 tx_buf[AD4170_SPI_INST_PHASE_LEN]; 559 unsigned int size; 560 int ret; 561 562 put_unaligned_be16(AD4170_REG_READ_MASK | reg, tx_buf); 563 564 ret = ad4170_get_reg_size(st, reg, &size); 565 if (ret) 566 return ret; 567 568 ret = spi_write_then_read(st->spi, tx_buf, ARRAY_SIZE(tx_buf), 569 st->rx_buf, size); 570 if (ret) 571 return ret; 572 573 switch (size) { 574 case 3: 575 *val = get_unaligned_be24(st->rx_buf); 576 return 0; 577 case 2: 578 *val = get_unaligned_be16(st->rx_buf); 579 return 0; 580 case 1: 581 *val = st->rx_buf[0]; 582 return 0; 583 default: 584 return -EINVAL; 585 } 586 } 587 588 static const struct regmap_config ad4170_regmap_config = { 589 .reg_read = ad4170_reg_read, 590 .reg_write = ad4170_reg_write, 591 }; 592 593 static bool ad4170_setup_eq(struct ad4170_setup *a, struct ad4170_setup *b) 594 { 595 if (a->misc != b->misc || 596 a->afe != b->afe || 597 a->filter != b->filter || 598 a->filter_fs != b->filter_fs || 599 a->offset != b->offset || 600 a->gain != b->gain) 601 return false; 602 603 return true; 604 } 605 606 static int ad4170_find_setup(struct ad4170_state *st, 607 struct ad4170_setup *target_setup, 608 unsigned int *setup_num, bool *overwrite) 609 { 610 unsigned int i; 611 612 *setup_num = AD4170_INVALID_SETUP; 613 *overwrite = false; 614 615 for (i = 0; i < AD4170_MAX_SETUPS; i++) { 616 struct ad4170_setup_info *setup_info = &st->setup_infos[i]; 617 618 /* Immediately accept a matching setup. */ 619 if (ad4170_setup_eq(target_setup, &setup_info->setup)) { 620 *setup_num = i; 621 return 0; 622 } 623 624 /* Ignore all setups which are used by enabled channels. */ 625 if (setup_info->enabled_channels) 626 continue; 627 628 /* Find the least used slot. */ 629 if (*setup_num == AD4170_INVALID_SETUP || 630 setup_info->channels < st->setup_infos[*setup_num].channels) 631 *setup_num = i; 632 } 633 634 if (*setup_num == AD4170_INVALID_SETUP) 635 return -EINVAL; 636 637 *overwrite = true; 638 return 0; 639 } 640 641 static void ad4170_unlink_channel(struct ad4170_state *st, unsigned int channel) 642 { 643 struct ad4170_chan_info *chan_info = &st->chan_infos[channel]; 644 struct ad4170_setup_info *setup_info = &st->setup_infos[chan_info->setup_num]; 645 646 chan_info->setup_num = AD4170_INVALID_SETUP; 647 setup_info->channels--; 648 } 649 650 static int ad4170_unlink_setup(struct ad4170_state *st, unsigned int setup_num) 651 { 652 unsigned int i; 653 654 for (i = 0; i < AD4170_MAX_ADC_CHANNELS; i++) { 655 struct ad4170_chan_info *chan_info = &st->chan_infos[i]; 656 657 if (!chan_info->initialized || chan_info->setup_num != setup_num) 658 continue; 659 660 ad4170_unlink_channel(st, i); 661 } 662 return 0; 663 } 664 665 static int ad4170_link_channel_setup(struct ad4170_state *st, 666 unsigned int chan_addr, 667 unsigned int setup_num) 668 { 669 struct ad4170_setup_info *setup_info = &st->setup_infos[setup_num]; 670 struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr]; 671 int ret; 672 673 ret = regmap_update_bits(st->regmap, AD4170_CHAN_SETUP_REG(chan_addr), 674 AD4170_CHAN_SETUP_SETUP_MSK, 675 FIELD_PREP(AD4170_CHAN_SETUP_SETUP_MSK, setup_num)); 676 if (ret) 677 return ret; 678 679 chan_info->setup_num = setup_num; 680 setup_info->channels++; 681 return 0; 682 } 683 684 static int ad4170_write_setup(struct ad4170_state *st, unsigned int setup_num, 685 struct ad4170_setup *setup) 686 { 687 int ret; 688 689 /* 690 * It is recommended to place the ADC in standby mode or idle mode to 691 * write to OFFSET and GAIN registers. 692 */ 693 ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 694 AD4170_ADC_CTRL_MODE_MSK, 695 FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK, 696 AD4170_ADC_CTRL_MODE_IDLE)); 697 if (ret) 698 return ret; 699 700 ret = regmap_write(st->regmap, AD4170_MISC_REG(setup_num), setup->misc); 701 if (ret) 702 return ret; 703 704 ret = regmap_write(st->regmap, AD4170_AFE_REG(setup_num), setup->afe); 705 if (ret) 706 return ret; 707 708 ret = regmap_write(st->regmap, AD4170_FILTER_REG(setup_num), 709 setup->filter); 710 if (ret) 711 return ret; 712 713 ret = regmap_write(st->regmap, AD4170_FILTER_FS_REG(setup_num), 714 setup->filter_fs); 715 if (ret) 716 return ret; 717 718 ret = regmap_write(st->regmap, AD4170_OFFSET_REG(setup_num), 719 setup->offset); 720 if (ret) 721 return ret; 722 723 ret = regmap_write(st->regmap, AD4170_GAIN_REG(setup_num), setup->gain); 724 if (ret) 725 return ret; 726 727 memcpy(&st->setup_infos[setup_num].setup, setup, sizeof(*setup)); 728 return 0; 729 } 730 731 static int ad4170_write_channel_setup(struct ad4170_state *st, 732 unsigned int chan_addr, bool on_enable) 733 { 734 struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr]; 735 bool overwrite; 736 int setup_num; 737 int ret; 738 739 /* 740 * Similar to AD4130 driver, the following cases need to be handled. 741 * 742 * 1. Enabled and linked channel with setup changes: 743 * - Find a setup. If not possible, return error. 744 * - Unlink channel from current setup. 745 * - If the setup found has only disabled channels linked to it, 746 * unlink all channels, and write the new setup to it. 747 * - Link channel to new setup. 748 * 749 * 2. Soon to be enabled and unlinked channel: 750 * - Find a setup. If not possible, return error. 751 * - If the setup found has only disabled channels linked to it, 752 * unlink all channels, and write the new setup to it. 753 * - Link channel to the setup. 754 * 755 * 3. Disabled and linked channel with setup changes: 756 * - Unlink channel from current setup. 757 * 758 * 4. Soon to be enabled and linked channel: 759 * 5. Disabled and unlinked channel with setup changes: 760 * - Do nothing. 761 */ 762 763 /* Cases 3, 4, and 5 */ 764 if (chan_info->setup_num != AD4170_INVALID_SETUP) { 765 /* Case 4 */ 766 if (on_enable) 767 return 0; 768 769 /* Case 3 */ 770 if (!chan_info->enabled) { 771 ad4170_unlink_channel(st, chan_addr); 772 return 0; 773 } 774 } else if (!on_enable && !chan_info->enabled) { 775 /* Case 5 */ 776 return 0; 777 } 778 779 /* Cases 1 & 2 */ 780 ret = ad4170_find_setup(st, &chan_info->setup, &setup_num, &overwrite); 781 if (ret) 782 return ret; 783 784 if (chan_info->setup_num != AD4170_INVALID_SETUP) 785 /* Case 1 */ 786 ad4170_unlink_channel(st, chan_addr); 787 788 if (overwrite) { 789 ret = ad4170_unlink_setup(st, setup_num); 790 if (ret) 791 return ret; 792 793 ret = ad4170_write_setup(st, setup_num, &chan_info->setup); 794 if (ret) 795 return ret; 796 } 797 798 return ad4170_link_channel_setup(st, chan_addr, setup_num); 799 } 800 801 static int ad4170_set_channel_enable(struct ad4170_state *st, 802 unsigned int chan_addr, bool status) 803 { 804 struct ad4170_chan_info *chan_info = &st->chan_infos[chan_addr]; 805 struct ad4170_setup_info *setup_info; 806 int ret; 807 808 if (chan_info->enabled == status) 809 return 0; 810 811 if (status) { 812 ret = ad4170_write_channel_setup(st, chan_addr, true); 813 if (ret) 814 return ret; 815 } 816 817 setup_info = &st->setup_infos[chan_info->setup_num]; 818 819 ret = regmap_update_bits(st->regmap, AD4170_CHAN_EN_REG, 820 AD4170_CHAN_EN(chan_addr), 821 status ? AD4170_CHAN_EN(chan_addr) : 0); 822 if (ret) 823 return ret; 824 825 setup_info->enabled_channels += status ? 1 : -1; 826 chan_info->enabled = status; 827 return 0; 828 } 829 830 static int __ad4170_get_filter_type(unsigned int filter) 831 { 832 u16 f_conf = FIELD_GET(AD4170_FILTER_FILTER_TYPE_MSK, filter); 833 834 switch (f_conf) { 835 case AD4170_FILTER_FILTER_TYPE_SINC5_AVG: 836 return AD4170_SINC5_AVG; 837 case AD4170_FILTER_FILTER_TYPE_SINC5: 838 return AD4170_SINC5; 839 case AD4170_FILTER_FILTER_TYPE_SINC3: 840 return AD4170_SINC3; 841 default: 842 return -EINVAL; 843 } 844 } 845 846 static int ad4170_set_filter_type(struct iio_dev *indio_dev, 847 struct iio_chan_spec const *chan, 848 unsigned int val) 849 { 850 struct ad4170_state *st = iio_priv(indio_dev); 851 struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 852 struct ad4170_setup *setup = &chan_info->setup; 853 unsigned int filter_type_conf; 854 int ret; 855 856 switch (val) { 857 case AD4170_SINC5_AVG: 858 filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC5_AVG; 859 break; 860 case AD4170_SINC5: 861 filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC5; 862 break; 863 case AD4170_SINC3: 864 filter_type_conf = AD4170_FILTER_FILTER_TYPE_SINC3; 865 break; 866 default: 867 return -EINVAL; 868 } 869 870 /* 871 * The filters provide the same ODR for a given filter_fs value but 872 * there are different minimum and maximum filter_fs limits for each 873 * filter. The filter_fs value will be adjusted if the current filter_fs 874 * is out of the limits of the just requested filter. Since the 875 * filter_fs value affects the ODR (sampling_frequency), changing the 876 * filter may lead to a change in the sampling frequency. 877 */ 878 scoped_guard(mutex, &st->lock) { 879 if (!iio_device_claim_direct(indio_dev)) 880 return -EBUSY; 881 882 if (val == AD4170_SINC5_AVG || val == AD4170_SINC3) 883 setup->filter_fs = clamp(val, AD4170_SINC3_MIN_FS, 884 AD4170_SINC3_MAX_FS); 885 else 886 setup->filter_fs = clamp(val, AD4170_SINC5_MIN_FS, 887 AD4170_SINC5_MAX_FS); 888 889 setup->filter &= ~AD4170_FILTER_FILTER_TYPE_MSK; 890 setup->filter |= FIELD_PREP(AD4170_FILTER_FILTER_TYPE_MSK, 891 filter_type_conf); 892 893 ret = ad4170_write_channel_setup(st, chan->address, false); 894 iio_device_release_direct(indio_dev); 895 } 896 897 return ret; 898 } 899 900 static int ad4170_get_filter_type(struct iio_dev *indio_dev, 901 struct iio_chan_spec const *chan) 902 { 903 struct ad4170_state *st = iio_priv(indio_dev); 904 struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 905 struct ad4170_setup *setup = &chan_info->setup; 906 907 return __ad4170_get_filter_type(setup->filter); 908 } 909 910 static const struct iio_enum ad4170_filter_type_enum = { 911 .items = ad4170_filt_names, 912 .num_items = ARRAY_SIZE(ad4170_filt_names), 913 .get = ad4170_get_filter_type, 914 .set = ad4170_set_filter_type, 915 }; 916 917 static const struct iio_chan_spec_ext_info ad4170_filter_type_ext_info[] = { 918 IIO_ENUM("filter_type", IIO_SEPARATE, &ad4170_filter_type_enum), 919 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE, 920 &ad4170_filter_type_enum), 921 { } 922 }; 923 924 static const struct iio_chan_spec ad4170_channel_template = { 925 .type = IIO_VOLTAGE, 926 .indexed = 1, 927 .differential = 1, 928 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 929 BIT(IIO_CHAN_INFO_SCALE) | 930 BIT(IIO_CHAN_INFO_CALIBBIAS) | 931 BIT(IIO_CHAN_INFO_CALIBSCALE) | 932 BIT(IIO_CHAN_INFO_SAMP_FREQ) | 933 BIT(IIO_CHAN_INFO_OFFSET), 934 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE) | 935 BIT(IIO_CHAN_INFO_SAMP_FREQ), 936 .ext_info = ad4170_filter_type_ext_info, 937 .scan_type = { 938 .realbits = 24, 939 .storagebits = 32, 940 .shift = 8, 941 .endianness = IIO_BE, 942 }, 943 }; 944 945 static const struct iio_chan_spec ad4170_temp_channel_template = { 946 .type = IIO_TEMP, 947 .indexed = 0, 948 .channel = 17, 949 .channel2 = 17, 950 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 951 BIT(IIO_CHAN_INFO_SCALE) | 952 BIT(IIO_CHAN_INFO_OFFSET) | 953 BIT(IIO_CHAN_INFO_CALIBSCALE) | 954 BIT(IIO_CHAN_INFO_CALIBBIAS) | 955 BIT(IIO_CHAN_INFO_SAMP_FREQ), 956 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 957 .scan_type = { 958 .sign = 's', 959 .realbits = 24, 960 .storagebits = 32, 961 .shift = 8, 962 .endianness = IIO_BE, 963 }, 964 }; 965 966 /* 967 * Receives the number of a multiplexed AD4170 input (ain_n), and stores the 968 * voltage (in µV) of the specified input into ain_voltage. If the input number 969 * is a ordinary analog input (AIN0 to AIN8), stores zero into ain_voltage. 970 * If a voltage regulator required by a special input is unavailable, return 971 * error code. Return 0 on success. 972 */ 973 static int ad4170_get_ain_voltage_uv(struct ad4170_state *st, int ain_n, 974 int *ain_voltage) 975 { 976 struct device *dev = &st->spi->dev; 977 int v_diff; 978 979 *ain_voltage = 0; 980 /* 981 * The voltage bias (vbias) sets the common-mode voltage of the channel 982 * to (AVDD + AVSS)/2. If provided, AVSS supply provides the magnitude 983 * (absolute value) of the negative voltage supplied to the AVSS pin. 984 * So, we do AVDD - AVSS to compute the DC voltage generated by the bias 985 * voltage generator. 986 */ 987 if (st->pins_fn[ain_n] & AD4170_PIN_VBIAS) { 988 int v_diff = st->vrefs_uv[AD4170_AVDD_SUP] - st->vrefs_uv[AD4170_AVSS_SUP]; 989 *ain_voltage = v_diff / 2; 990 return 0; 991 } 992 993 if (ain_n <= AD4170_CHAN_MAP_TEMP_SENSOR) 994 return 0; 995 996 switch (ain_n) { 997 case AD4170_CHAN_MAP_AVDD_AVSS_N: 998 v_diff = st->vrefs_uv[AD4170_AVDD_SUP] - st->vrefs_uv[AD4170_AVSS_SUP]; 999 *ain_voltage = v_diff / 5; 1000 return 0; 1001 case AD4170_CHAN_MAP_IOVDD_DGND_N: 1002 *ain_voltage = st->vrefs_uv[AD4170_IOVDD_SUP] / 5; 1003 return 0; 1004 case AD4170_CHAN_MAP_AVSS: 1005 *ain_voltage = st->vrefs_uv[AD4170_AVSS_SUP]; 1006 return 0; 1007 case AD4170_CHAN_MAP_DGND: 1008 *ain_voltage = 0; 1009 return 0; 1010 case AD4170_CHAN_MAP_REFIN1_P: 1011 if (st->vrefs_uv[AD4170_REFIN1P_SUP] == -ENODEV) 1012 return dev_err_probe(dev, -ENODEV, 1013 "input set to REFIN+ but ref not provided\n"); 1014 1015 *ain_voltage = st->vrefs_uv[AD4170_REFIN1P_SUP]; 1016 return 0; 1017 case AD4170_CHAN_MAP_REFIN1_N: 1018 if (st->vrefs_uv[AD4170_REFIN1N_SUP] == -ENODEV) 1019 return dev_err_probe(dev, -ENODEV, 1020 "input set to REFIN- but ref not provided\n"); 1021 1022 *ain_voltage = st->vrefs_uv[AD4170_REFIN1N_SUP]; 1023 return 0; 1024 case AD4170_CHAN_MAP_REFIN2_P: 1025 if (st->vrefs_uv[AD4170_REFIN2P_SUP] == -ENODEV) 1026 return dev_err_probe(dev, -ENODEV, 1027 "input set to REFIN2+ but ref not provided\n"); 1028 1029 *ain_voltage = st->vrefs_uv[AD4170_REFIN2P_SUP]; 1030 return 0; 1031 case AD4170_CHAN_MAP_REFIN2_N: 1032 if (st->vrefs_uv[AD4170_REFIN2N_SUP] == -ENODEV) 1033 return dev_err_probe(dev, -ENODEV, 1034 "input set to REFIN2- but ref not provided\n"); 1035 1036 *ain_voltage = st->vrefs_uv[AD4170_REFIN2N_SUP]; 1037 return 0; 1038 case AD4170_CHAN_MAP_REFOUT: 1039 /* REFOUT is 2.5V relative to AVSS so take that into account */ 1040 *ain_voltage = st->vrefs_uv[AD4170_AVSS_SUP] + AD4170_INT_REF_2_5V; 1041 return 0; 1042 default: 1043 return -EINVAL; 1044 } 1045 } 1046 1047 static int ad4170_validate_analog_input(struct ad4170_state *st, int pin) 1048 { 1049 if (pin <= AD4170_MAX_ANALOG_PINS) { 1050 if (st->pins_fn[pin] & AD4170_PIN_CURRENT_OUT) 1051 return dev_err_probe(&st->spi->dev, -EINVAL, 1052 "Pin %d already used with fn %u.\n", 1053 pin, st->pins_fn[pin]); 1054 1055 st->pins_fn[pin] |= AD4170_PIN_ANALOG_IN; 1056 } 1057 return 0; 1058 } 1059 1060 static int ad4170_validate_channel_input(struct ad4170_state *st, int pin, bool com) 1061 { 1062 /* Check common-mode input pin is mapped to a special input. */ 1063 if (com && (pin < AD4170_CHAN_MAP_AVDD_AVSS_P || pin > AD4170_CHAN_MAP_REFOUT)) 1064 return dev_err_probe(&st->spi->dev, -EINVAL, 1065 "Invalid common-mode input pin number. %d\n", 1066 pin); 1067 1068 /* Check differential input pin is mapped to a analog input pin. */ 1069 if (!com && pin > AD4170_MAX_ANALOG_PINS) 1070 return dev_err_probe(&st->spi->dev, -EINVAL, 1071 "Invalid analog input pin number. %d\n", 1072 pin); 1073 1074 return ad4170_validate_analog_input(st, pin); 1075 } 1076 1077 /* 1078 * Verifies whether the channel input configuration is valid by checking the 1079 * input numbers. 1080 * Returns 0 on valid channel input configuration. -EINVAL otherwise. 1081 */ 1082 static int ad4170_validate_channel(struct ad4170_state *st, 1083 struct iio_chan_spec const *chan) 1084 { 1085 int ret; 1086 1087 ret = ad4170_validate_channel_input(st, chan->channel, false); 1088 if (ret) 1089 return ret; 1090 1091 return ad4170_validate_channel_input(st, chan->channel2, 1092 !chan->differential); 1093 } 1094 1095 /* 1096 * Verifies whether the channel configuration is valid by checking the provided 1097 * input type, polarity, and voltage references result in a sane input range. 1098 * Returns negative error code on failure. 1099 */ 1100 static int ad4170_get_input_range(struct ad4170_state *st, 1101 struct iio_chan_spec const *chan, 1102 unsigned int ch_reg, unsigned int ref_sel) 1103 { 1104 bool bipolar = chan->scan_type.sign == 's'; 1105 struct device *dev = &st->spi->dev; 1106 int refp, refn, ain_voltage, ret; 1107 1108 switch (ref_sel) { 1109 case AD4170_REF_REFIN1: 1110 if (st->vrefs_uv[AD4170_REFIN1P_SUP] == -ENODEV || 1111 st->vrefs_uv[AD4170_REFIN1N_SUP] == -ENODEV) 1112 return dev_err_probe(dev, -ENODEV, 1113 "REFIN± selected but not provided\n"); 1114 1115 refp = st->vrefs_uv[AD4170_REFIN1P_SUP]; 1116 refn = st->vrefs_uv[AD4170_REFIN1N_SUP]; 1117 break; 1118 case AD4170_REF_REFIN2: 1119 if (st->vrefs_uv[AD4170_REFIN2P_SUP] == -ENODEV || 1120 st->vrefs_uv[AD4170_REFIN2N_SUP] == -ENODEV) 1121 return dev_err_probe(dev, -ENODEV, 1122 "REFIN2± selected but not provided\n"); 1123 1124 refp = st->vrefs_uv[AD4170_REFIN2P_SUP]; 1125 refn = st->vrefs_uv[AD4170_REFIN2N_SUP]; 1126 break; 1127 case AD4170_REF_AVDD: 1128 refp = st->vrefs_uv[AD4170_AVDD_SUP]; 1129 refn = st->vrefs_uv[AD4170_AVSS_SUP]; 1130 break; 1131 case AD4170_REF_REFOUT: 1132 /* REFOUT is 2.5 V relative to AVSS */ 1133 refp = st->vrefs_uv[AD4170_AVSS_SUP] + AD4170_INT_REF_2_5V; 1134 refn = st->vrefs_uv[AD4170_AVSS_SUP]; 1135 break; 1136 default: 1137 return -EINVAL; 1138 } 1139 1140 /* 1141 * Find out the analog input range from the channel type, polarity, and 1142 * voltage reference selection. 1143 * AD4170 channels are either differential or pseudo-differential. 1144 * Diff input voltage range: −VREF/gain to +VREF/gain (datasheet page 6) 1145 * Pseudo-diff input voltage range: 0 to VREF/gain (datasheet page 6) 1146 */ 1147 if (chan->differential) { 1148 if (!bipolar) 1149 return dev_err_probe(dev, -EINVAL, 1150 "Channel %u differential unipolar\n", 1151 ch_reg); 1152 1153 /* 1154 * Differential bipolar channel. 1155 * avss-supply is never above 0V. 1156 * Assuming refin1n-supply not above 0V. 1157 * Assuming refin2n-supply not above 0V. 1158 */ 1159 return refp + abs(refn); 1160 } 1161 /* 1162 * Some configurations can lead to invalid setups. 1163 * For example, if AVSS = -2.5V, REF_SELECT set to REFOUT (REFOUT/AVSS), 1164 * and pseudo-diff channel configuration set, then the input range 1165 * should go from 0V to +VREF (single-ended - datasheet pg 10), but 1166 * REFOUT/AVSS range would be -2.5V to 0V. 1167 * Check the positive reference is higher than 0V for pseudo-diff 1168 * channels. 1169 * Note that at this point in the code, refp can only be >= 0 since all 1170 * error codes from reading the regulator voltage have been checked 1171 * either at ad4170_regulator_setup() or above in this function. 1172 */ 1173 if (refp == 0) 1174 return dev_err_probe(dev, -EINVAL, 1175 "REF+ == GND for pseudo-diff chan %u\n", 1176 ch_reg); 1177 1178 if (bipolar) 1179 return refp; 1180 1181 /* 1182 * Pseudo-differential unipolar channel. 1183 * Input expected to swing from IN- to +VREF. 1184 */ 1185 ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ain_voltage); 1186 if (ret) 1187 return ret; 1188 1189 if (refp - ain_voltage <= 0) 1190 return dev_err_probe(dev, -EINVAL, 1191 "Negative input >= REF+ for pseudo-diff chan %u\n", 1192 ch_reg); 1193 1194 return refp - ain_voltage; 1195 } 1196 1197 static int __ad4170_read_sample(struct iio_dev *indio_dev, 1198 struct iio_chan_spec const *chan, int *val) 1199 { 1200 struct ad4170_state *st = iio_priv(indio_dev); 1201 unsigned long settling_time_ms; 1202 int ret; 1203 1204 reinit_completion(&st->completion); 1205 ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 1206 AD4170_ADC_CTRL_MODE_MSK, 1207 FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK, 1208 AD4170_ADC_CTRL_MODE_SINGLE)); 1209 if (ret) 1210 return ret; 1211 1212 /* 1213 * When a channel is manually selected by the user, the ADC needs an 1214 * extra time to provide the first stable conversion. The ADC settling 1215 * time depends on the filter type, filter frequency, and ADC clock 1216 * frequency (see datasheet page 53). The maximum settling time among 1217 * all filter configurations is 6291164 / fCLK. Use that formula to wait 1218 * for sufficient time whatever the filter configuration may be. 1219 */ 1220 settling_time_ms = DIV_ROUND_UP(6291164 * MILLI, st->mclk_hz); 1221 ret = wait_for_completion_timeout(&st->completion, 1222 msecs_to_jiffies(settling_time_ms)); 1223 if (!ret) 1224 dev_dbg(&st->spi->dev, 1225 "No Data Ready signal. Reading after delay.\n"); 1226 1227 ret = regmap_read(st->regmap, AD4170_DATA_24B_REG, val); 1228 if (ret) 1229 return ret; 1230 1231 if (chan->scan_type.sign == 's') 1232 *val = sign_extend32(*val, chan->scan_type.realbits - 1); 1233 1234 return 0; 1235 } 1236 1237 static int ad4170_read_sample(struct iio_dev *indio_dev, 1238 struct iio_chan_spec const *chan, int *val) 1239 { 1240 struct ad4170_state *st = iio_priv(indio_dev); 1241 struct device *dev = &st->spi->dev; 1242 int ret, ret2; 1243 1244 /* 1245 * The ADC sequences through all enabled channels. That can lead to 1246 * incorrect channel being sampled if a previous read would have left a 1247 * different channel enabled. Thus, always enable and disable the 1248 * channel on single-shot read. 1249 */ 1250 ret = ad4170_set_channel_enable(st, chan->address, true); 1251 if (ret) 1252 return ret; 1253 1254 ret = __ad4170_read_sample(indio_dev, chan, val); 1255 if (ret) { 1256 dev_err(dev, "failed to read sample: %d\n", ret); 1257 1258 ret2 = ad4170_set_channel_enable(st, chan->address, false); 1259 if (ret2) 1260 dev_err(dev, "failed to disable channel: %d\n", ret2); 1261 1262 return ret; 1263 } 1264 1265 ret = ad4170_set_channel_enable(st, chan->address, false); 1266 if (ret) 1267 return ret; 1268 1269 return IIO_VAL_INT; 1270 } 1271 1272 static int ad4170_read_raw(struct iio_dev *indio_dev, 1273 struct iio_chan_spec const *chan, 1274 int *val, int *val2, long info) 1275 { 1276 struct ad4170_state *st = iio_priv(indio_dev); 1277 struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1278 struct ad4170_setup *setup = &chan_info->setup; 1279 enum ad4170_filter_type f_type; 1280 unsigned int pga, fs_idx; 1281 int ret; 1282 1283 guard(mutex)(&st->lock); 1284 switch (info) { 1285 case IIO_CHAN_INFO_RAW: 1286 if (!iio_device_claim_direct(indio_dev)) 1287 return -EBUSY; 1288 1289 ret = ad4170_read_sample(indio_dev, chan, val); 1290 iio_device_release_direct(indio_dev); 1291 return ret; 1292 case IIO_CHAN_INFO_SCALE: 1293 pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe); 1294 switch (chan->type) { 1295 case IIO_VOLTAGE: 1296 *val = chan_info->scale_tbl[pga][0]; 1297 *val2 = chan_info->scale_tbl[pga][1]; 1298 return IIO_VAL_INT_PLUS_NANO; 1299 case IIO_TEMP: 1300 /* 1301 * The scale_tbl converts output codes to mV units so 1302 * multiply by MILLI to make the factor convert to µV. 1303 * Then, apply the temperature sensor change sensitivity 1304 * of 477 μV/K. Finally, multiply the result by MILLI 1305 * again to comply with milli degrees Celsius IIO ABI. 1306 */ 1307 *val = 0; 1308 *val2 = DIV_ROUND_CLOSEST(chan_info->scale_tbl[pga][1] * MILLI, 477) * 1309 MILLI; 1310 return IIO_VAL_INT_PLUS_NANO; 1311 default: 1312 return -EINVAL; 1313 } 1314 case IIO_CHAN_INFO_OFFSET: 1315 pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe); 1316 *val = chan_info->offset_tbl[pga]; 1317 return IIO_VAL_INT; 1318 case IIO_CHAN_INFO_SAMP_FREQ: 1319 f_type = __ad4170_get_filter_type(setup->filter); 1320 switch (f_type) { 1321 case AD4170_SINC5_AVG: 1322 case AD4170_SINC3: 1323 fs_idx = find_closest(setup->filter_fs, 1324 ad4170_sinc3_filt_fs_tbl, 1325 ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl)); 1326 *val = st->sps_tbl[f_type][fs_idx][0]; 1327 *val2 = st->sps_tbl[f_type][fs_idx][1]; 1328 return IIO_VAL_INT_PLUS_MICRO; 1329 case AD4170_SINC5: 1330 fs_idx = find_closest(setup->filter_fs, 1331 ad4170_sinc5_filt_fs_tbl, 1332 ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl)); 1333 *val = st->sps_tbl[f_type][fs_idx][0]; 1334 *val2 = st->sps_tbl[f_type][fs_idx][1]; 1335 return IIO_VAL_INT_PLUS_MICRO; 1336 default: 1337 return -EINVAL; 1338 } 1339 case IIO_CHAN_INFO_CALIBBIAS: 1340 *val = setup->offset; 1341 return IIO_VAL_INT; 1342 case IIO_CHAN_INFO_CALIBSCALE: 1343 *val = setup->gain; 1344 return IIO_VAL_INT; 1345 default: 1346 return -EINVAL; 1347 } 1348 } 1349 1350 static int ad4170_fill_scale_tbl(struct iio_dev *indio_dev, 1351 struct iio_chan_spec const *chan) 1352 { 1353 struct ad4170_state *st = iio_priv(indio_dev); 1354 struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1355 struct device *dev = &st->spi->dev; 1356 int bipolar = chan->scan_type.sign == 's' ? 1 : 0; 1357 int precision_bits = chan->scan_type.realbits; 1358 int pga, ainm_voltage, ret; 1359 unsigned long long offset; 1360 1361 ainm_voltage = 0; 1362 ret = ad4170_get_ain_voltage_uv(st, chan->channel2, &ainm_voltage); 1363 if (ret < 0) 1364 return dev_err_probe(dev, ret, "Failed to fill scale table\n"); 1365 1366 for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) { 1367 u64 nv; 1368 unsigned int lshift, rshift; 1369 1370 /* 1371 * The PGA options are numbered from 0 to 9, with option 0 being 1372 * a gain of 2^0 (no actual gain), and 7 meaning a gain of 2^7. 1373 * Option 8, though, sets a gain of 0.5, so the input signal can 1374 * be attenuated by 2 rather than amplified. Option 9, allows 1375 * the signal to bypass the PGA circuitry (no gain). 1376 * 1377 * The scale factor to get ADC output codes to values in mV 1378 * units is given by: 1379 * _scale = (input_range / gain) / 2^precision 1380 * AD4170 gain is a power of 2 so the above can be written as 1381 * _scale = input_range / 2^(precision + gain) 1382 * Keep the input range in µV to avoid truncating the less 1383 * significant bits when right shifting it so to preserve scale 1384 * precision. 1385 */ 1386 nv = (u64)chan_info->input_range_uv * NANO; 1387 lshift = !!(pga & BIT(3)); /* handle PGA options 8 and 9 */ 1388 rshift = precision_bits - bipolar + (pga & GENMASK(2, 0)) - lshift; 1389 chan_info->scale_tbl[pga][0] = 0; 1390 chan_info->scale_tbl[pga][1] = div_u64(nv >> rshift, MILLI); 1391 1392 /* 1393 * If the negative input is not at GND, the conversion result 1394 * (which is relative to IN-) will be offset by the level at IN-. 1395 * Use the scale factor the other way around to go from a known 1396 * voltage to the corresponding ADC output code. 1397 * With that, we are able to get to what would be the output 1398 * code for the voltage at the negative input. 1399 * If the negative input is not fixed, there is no offset. 1400 */ 1401 offset = ((unsigned long long)abs(ainm_voltage)) * MICRO; 1402 offset = DIV_ROUND_CLOSEST_ULL(offset, chan_info->scale_tbl[pga][1]); 1403 1404 /* 1405 * After divided by the scale, offset will always fit into 31 1406 * bits. For _raw + _offset to be relative to GND, the value 1407 * provided as _offset is of opposite sign than the real offset. 1408 */ 1409 if (ainm_voltage > 0) 1410 chan_info->offset_tbl[pga] = -(int)(offset); 1411 else 1412 chan_info->offset_tbl[pga] = (int)(offset); 1413 } 1414 return 0; 1415 } 1416 1417 static int ad4170_read_avail(struct iio_dev *indio_dev, 1418 struct iio_chan_spec const *chan, 1419 const int **vals, int *type, int *length, 1420 long info) 1421 { 1422 struct ad4170_state *st = iio_priv(indio_dev); 1423 struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1424 enum ad4170_filter_type f_type; 1425 1426 switch (info) { 1427 case IIO_CHAN_INFO_SCALE: 1428 *vals = (int *)chan_info->scale_tbl; 1429 *length = ARRAY_SIZE(chan_info->scale_tbl) * 2; 1430 *type = IIO_VAL_INT_PLUS_NANO; 1431 return IIO_AVAIL_LIST; 1432 case IIO_CHAN_INFO_SAMP_FREQ: 1433 *type = IIO_VAL_INT_PLUS_MICRO; 1434 f_type = ad4170_get_filter_type(indio_dev, chan); 1435 switch (f_type) { 1436 case AD4170_SINC5_AVG: 1437 case AD4170_SINC3: 1438 /* Read sps_tbl here to ensure in bounds array access */ 1439 *vals = (int *)st->sps_tbl[f_type]; 1440 *length = ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl) * 2; 1441 return IIO_AVAIL_LIST; 1442 case AD4170_SINC5: 1443 /* Read sps_tbl here to ensure in bounds array access */ 1444 *vals = (int *)st->sps_tbl[f_type]; 1445 *length = ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl) * 2; 1446 return IIO_AVAIL_LIST; 1447 default: 1448 return -EINVAL; 1449 } 1450 default: 1451 return -EINVAL; 1452 } 1453 } 1454 1455 static int ad4170_set_pga(struct ad4170_state *st, 1456 struct iio_chan_spec const *chan, int val, int val2) 1457 { 1458 struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1459 struct ad4170_setup *setup = &chan_info->setup; 1460 unsigned int pga; 1461 1462 for (pga = 0; pga < AD4170_NUM_PGA_OPTIONS; pga++) { 1463 if (val == chan_info->scale_tbl[pga][0] && 1464 val2 == chan_info->scale_tbl[pga][1]) 1465 break; 1466 } 1467 1468 if (pga == AD4170_NUM_PGA_OPTIONS) 1469 return -EINVAL; 1470 1471 guard(mutex)(&st->lock); 1472 setup->afe &= ~AD4170_AFE_PGA_GAIN_MSK; 1473 setup->afe |= FIELD_PREP(AD4170_AFE_PGA_GAIN_MSK, pga); 1474 1475 return ad4170_write_channel_setup(st, chan->address, false); 1476 } 1477 1478 static int ad4170_set_channel_freq(struct ad4170_state *st, 1479 struct iio_chan_spec const *chan, int val, 1480 int val2) 1481 { 1482 struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1483 struct ad4170_setup *setup = &chan_info->setup; 1484 enum ad4170_filter_type f_type = __ad4170_get_filter_type(setup->filter); 1485 unsigned int filt_fs_tbl_size, i; 1486 1487 switch (f_type) { 1488 case AD4170_SINC5_AVG: 1489 case AD4170_SINC3: 1490 filt_fs_tbl_size = ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl); 1491 break; 1492 case AD4170_SINC5: 1493 filt_fs_tbl_size = ARRAY_SIZE(ad4170_sinc5_filt_fs_tbl); 1494 break; 1495 } 1496 1497 for (i = 0; i < filt_fs_tbl_size; i++) { 1498 if (st->sps_tbl[f_type][i][0] == val && 1499 st->sps_tbl[f_type][i][1] == val2) 1500 break; 1501 } 1502 if (i == filt_fs_tbl_size) 1503 return -EINVAL; 1504 1505 guard(mutex)(&st->lock); 1506 if (f_type == AD4170_SINC5) 1507 setup->filter_fs = ad4170_sinc5_filt_fs_tbl[i]; 1508 else 1509 setup->filter_fs = ad4170_sinc3_filt_fs_tbl[i]; 1510 1511 return ad4170_write_channel_setup(st, chan->address, false); 1512 } 1513 1514 static int ad4170_set_calib_offset(struct ad4170_state *st, 1515 struct iio_chan_spec const *chan, int val) 1516 { 1517 struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1518 struct ad4170_setup *setup = &chan_info->setup; 1519 1520 guard(mutex)(&st->lock); 1521 setup->offset = val; 1522 1523 return ad4170_write_channel_setup(st, chan->address, false); 1524 } 1525 1526 static int ad4170_set_calib_gain(struct ad4170_state *st, 1527 struct iio_chan_spec const *chan, int val) 1528 { 1529 struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; 1530 struct ad4170_setup *setup = &chan_info->setup; 1531 1532 guard(mutex)(&st->lock); 1533 setup->gain = val; 1534 1535 return ad4170_write_channel_setup(st, chan->address, false); 1536 } 1537 1538 static int __ad4170_write_raw(struct iio_dev *indio_dev, 1539 struct iio_chan_spec const *chan, int val, 1540 int val2, long info) 1541 { 1542 struct ad4170_state *st = iio_priv(indio_dev); 1543 1544 switch (info) { 1545 case IIO_CHAN_INFO_SCALE: 1546 return ad4170_set_pga(st, chan, val, val2); 1547 case IIO_CHAN_INFO_SAMP_FREQ: 1548 return ad4170_set_channel_freq(st, chan, val, val2); 1549 case IIO_CHAN_INFO_CALIBBIAS: 1550 return ad4170_set_calib_offset(st, chan, val); 1551 case IIO_CHAN_INFO_CALIBSCALE: 1552 return ad4170_set_calib_gain(st, chan, val); 1553 default: 1554 return -EINVAL; 1555 } 1556 } 1557 1558 static int ad4170_write_raw(struct iio_dev *indio_dev, 1559 struct iio_chan_spec const *chan, int val, 1560 int val2, long info) 1561 { 1562 int ret; 1563 1564 if (!iio_device_claim_direct(indio_dev)) 1565 return -EBUSY; 1566 1567 ret = __ad4170_write_raw(indio_dev, chan, val, val2, info); 1568 iio_device_release_direct(indio_dev); 1569 return ret; 1570 } 1571 1572 static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev, 1573 struct iio_chan_spec const *chan, 1574 long info) 1575 { 1576 switch (info) { 1577 case IIO_CHAN_INFO_SCALE: 1578 return IIO_VAL_INT_PLUS_NANO; 1579 case IIO_CHAN_INFO_SAMP_FREQ: 1580 return IIO_VAL_INT_PLUS_MICRO; 1581 case IIO_CHAN_INFO_CALIBBIAS: 1582 case IIO_CHAN_INFO_CALIBSCALE: 1583 return IIO_VAL_INT; 1584 default: 1585 return -EINVAL; 1586 } 1587 } 1588 1589 static int ad4170_update_scan_mode(struct iio_dev *indio_dev, 1590 const unsigned long *active_scan_mask) 1591 { 1592 struct ad4170_state *st = iio_priv(indio_dev); 1593 unsigned int chan_index; 1594 int ret; 1595 1596 iio_for_each_active_channel(indio_dev, chan_index) { 1597 ret = ad4170_set_channel_enable(st, chan_index, true); 1598 if (ret) 1599 return ret; 1600 } 1601 return 0; 1602 } 1603 1604 static const struct iio_info ad4170_info = { 1605 .read_raw = ad4170_read_raw, 1606 .read_avail = ad4170_read_avail, 1607 .write_raw = ad4170_write_raw, 1608 .write_raw_get_fmt = ad4170_write_raw_get_fmt, 1609 .update_scan_mode = ad4170_update_scan_mode, 1610 .debugfs_reg_access = ad4170_debugfs_reg_access, 1611 }; 1612 1613 static int ad4170_soft_reset(struct ad4170_state *st) 1614 { 1615 int ret; 1616 1617 ret = regmap_write(st->regmap, AD4170_CONFIG_A_REG, 1618 AD4170_SW_RESET_MSK); 1619 if (ret) 1620 return ret; 1621 1622 /* AD4170-4 requires 1 ms between reset and any register access. */ 1623 fsleep(1 * USEC_PER_MSEC); 1624 1625 return 0; 1626 } 1627 1628 static int ad4170_gpio_get(struct gpio_chip *gc, unsigned int offset) 1629 { 1630 struct iio_dev *indio_dev = gpiochip_get_data(gc); 1631 struct ad4170_state *st = iio_priv(indio_dev); 1632 unsigned int val; 1633 int ret; 1634 1635 if (!iio_device_claim_direct(indio_dev)) 1636 return -EBUSY; 1637 1638 ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val); 1639 if (ret) 1640 goto err_release; 1641 1642 /* 1643 * If the GPIO is configured as an input, read the current value from 1644 * AD4170_GPIO_INPUT_REG. Otherwise, read the input value from 1645 * AD4170_GPIO_OUTPUT_REG. 1646 */ 1647 if (val & BIT(offset * 2)) 1648 ret = regmap_read(st->regmap, AD4170_GPIO_INPUT_REG, &val); 1649 else 1650 ret = regmap_read(st->regmap, AD4170_GPIO_OUTPUT_REG, &val); 1651 if (ret) 1652 goto err_release; 1653 1654 ret = !!(val & BIT(offset)); 1655 err_release: 1656 iio_device_release_direct(indio_dev); 1657 1658 return ret; 1659 } 1660 1661 static int ad4170_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1662 { 1663 struct iio_dev *indio_dev = gpiochip_get_data(gc); 1664 struct ad4170_state *st = iio_priv(indio_dev); 1665 int ret; 1666 1667 if (!iio_device_claim_direct(indio_dev)) 1668 return -EBUSY; 1669 1670 ret = regmap_assign_bits(st->regmap, AD4170_GPIO_OUTPUT_REG, 1671 BIT(offset), !!value); 1672 1673 iio_device_release_direct(indio_dev); 1674 return ret; 1675 } 1676 1677 static int ad4170_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1678 { 1679 struct iio_dev *indio_dev = gpiochip_get_data(gc); 1680 struct ad4170_state *st = iio_priv(indio_dev); 1681 unsigned int val; 1682 int ret; 1683 1684 if (!iio_device_claim_direct(indio_dev)) 1685 return -EBUSY; 1686 1687 ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val); 1688 if (ret) 1689 goto err_release; 1690 1691 if (val & BIT(offset * 2 + 1)) 1692 ret = GPIO_LINE_DIRECTION_OUT; 1693 else 1694 ret = GPIO_LINE_DIRECTION_IN; 1695 1696 err_release: 1697 iio_device_release_direct(indio_dev); 1698 1699 return ret; 1700 } 1701 1702 static const unsigned long gpio_masks[] = { 1703 AD4170_GPIO_MODE_GPIO0_MSK, 1704 AD4170_GPIO_MODE_GPIO1_MSK, 1705 AD4170_GPIO_MODE_GPIO2_MSK, 1706 AD4170_GPIO_MODE_GPIO3_MSK, 1707 }; 1708 1709 static int ad4170_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1710 { 1711 struct iio_dev *indio_dev = gpiochip_get_data(gc); 1712 struct ad4170_state *st = iio_priv(indio_dev); 1713 int ret; 1714 1715 if (!iio_device_claim_direct(indio_dev)) 1716 return -EBUSY; 1717 1718 if (offset >= ARRAY_SIZE(gpio_masks)) { 1719 ret = -EINVAL; 1720 goto err_release; 1721 } 1722 1723 ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, 1724 gpio_masks[offset], 1725 AD4170_GPIO_MODE_GPIO_INPUT << (2 * offset)); 1726 1727 err_release: 1728 iio_device_release_direct(indio_dev); 1729 1730 return ret; 1731 } 1732 1733 static int ad4170_gpio_direction_output(struct gpio_chip *gc, 1734 unsigned int offset, int value) 1735 { 1736 struct iio_dev *indio_dev = gpiochip_get_data(gc); 1737 struct ad4170_state *st = iio_priv(indio_dev); 1738 int ret; 1739 1740 ret = ad4170_gpio_set(gc, offset, value); 1741 if (ret) 1742 return ret; 1743 1744 if (!iio_device_claim_direct(indio_dev)) 1745 return -EBUSY; 1746 1747 if (offset >= ARRAY_SIZE(gpio_masks)) { 1748 ret = -EINVAL; 1749 goto err_release; 1750 } 1751 1752 ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, 1753 gpio_masks[offset], 1754 AD4170_GPIO_MODE_GPIO_OUTPUT << (2 * offset)); 1755 1756 err_release: 1757 iio_device_release_direct(indio_dev); 1758 1759 return ret; 1760 } 1761 1762 static int ad4170_gpio_init_valid_mask(struct gpio_chip *gc, 1763 unsigned long *valid_mask, 1764 unsigned int ngpios) 1765 { 1766 struct ad4170_state *st = gpiochip_get_data(gc); 1767 unsigned int i; 1768 1769 /* Only expose GPIOs that were not assigned any other function. */ 1770 for (i = 0; i < ngpios; i++) { 1771 bool valid = st->gpio_fn[i] == AD4170_GPIO_UNASSIGNED; 1772 1773 __assign_bit(i, valid_mask, valid); 1774 } 1775 1776 return 0; 1777 } 1778 1779 static int ad4170_gpio_init(struct iio_dev *indio_dev) 1780 { 1781 struct ad4170_state *st = iio_priv(indio_dev); 1782 1783 st->gpiochip.label = "ad4170_gpios"; 1784 st->gpiochip.base = -1; 1785 st->gpiochip.ngpio = AD4170_NUM_GPIO_PINS; 1786 st->gpiochip.parent = &st->spi->dev; 1787 st->gpiochip.can_sleep = true; 1788 st->gpiochip.init_valid_mask = ad4170_gpio_init_valid_mask; 1789 st->gpiochip.get_direction = ad4170_gpio_get_direction; 1790 st->gpiochip.direction_input = ad4170_gpio_direction_input; 1791 st->gpiochip.direction_output = ad4170_gpio_direction_output; 1792 st->gpiochip.get = ad4170_gpio_get; 1793 st->gpiochip.set = ad4170_gpio_set; 1794 st->gpiochip.owner = THIS_MODULE; 1795 1796 return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev); 1797 } 1798 1799 static int ad4170_validate_excitation_pin(struct ad4170_state *st, u32 pin) 1800 { 1801 struct device *dev = &st->spi->dev; 1802 unsigned int i; 1803 1804 /* Check the pin number is valid */ 1805 for (i = 0; i < ARRAY_SIZE(ad4170_iout_pin_tbl); i++) 1806 if (ad4170_iout_pin_tbl[i] == pin) 1807 break; 1808 1809 if (i == ARRAY_SIZE(ad4170_iout_pin_tbl)) 1810 return dev_err_probe(dev, -EINVAL, 1811 "Invalid excitation pin: %u\n", 1812 pin); 1813 1814 /* Check the pin is available */ 1815 if (pin <= AD4170_MAX_ANALOG_PINS) { 1816 if (st->pins_fn[pin] != AD4170_PIN_UNASSIGNED) 1817 return dev_err_probe(dev, -EINVAL, 1818 "Pin %u already used with fn %u\n", 1819 pin, st->pins_fn[pin]); 1820 1821 st->pins_fn[pin] |= AD4170_PIN_CURRENT_OUT; 1822 } else { 1823 unsigned int gpio = pin - AD4170_CURRENT_SRC_I_OUT_PIN_GPIO(0); 1824 1825 if (st->gpio_fn[gpio] != AD4170_GPIO_UNASSIGNED) 1826 return dev_err_probe(dev, -EINVAL, 1827 "GPIO %u already used with fn %u\n", 1828 gpio, st->gpio_fn[gpio]); 1829 1830 st->gpio_fn[gpio] |= AD4170_GPIO_AC_EXCITATION; 1831 } 1832 1833 return 0; 1834 } 1835 1836 static int ad4170_validate_excitation_pins(struct ad4170_state *st, 1837 u32 *exc_pins, int num_exc_pins) 1838 { 1839 unsigned int i; 1840 int ret; 1841 1842 for (i = 0; i < num_exc_pins; i++) { 1843 ret = ad4170_validate_excitation_pin(st, exc_pins[i]); 1844 if (ret) 1845 return ret; 1846 } 1847 return 0; 1848 } 1849 1850 static const char *const ad4170_i_out_pin_dt_props[] = { 1851 "adi,excitation-pin-0", 1852 "adi,excitation-pin-1", 1853 "adi,excitation-pin-2", 1854 "adi,excitation-pin-3", 1855 }; 1856 1857 static const char *const ad4170_i_out_val_dt_props[] = { 1858 "adi,excitation-current-0-microamp", 1859 "adi,excitation-current-1-microamp", 1860 "adi,excitation-current-2-microamp", 1861 "adi,excitation-current-3-microamp", 1862 }; 1863 1864 /* 1865 * Parses firmware data describing output current source setup. There are 4 1866 * excitation currents (IOUT0 to IOUT3) that can be configured independently. 1867 * Excitation currents are added if they are output on the same pin. 1868 */ 1869 static int ad4170_parse_exc_current(struct ad4170_state *st, 1870 struct fwnode_handle *child, 1871 unsigned int *exc_pins, 1872 unsigned int *exc_curs, 1873 unsigned int *num_exc_pins) 1874 { 1875 struct device *dev = &st->spi->dev; 1876 unsigned int num_pins, i, j; 1877 u32 pin, val; 1878 int ret; 1879 1880 num_pins = 0; 1881 for (i = 0; i < AD4170_NUM_CURRENT_SRC; i++) { 1882 /* Parse excitation current output pin properties. */ 1883 pin = AD4170_CURRENT_SRC_I_OUT_PIN_AIN(0); 1884 ret = fwnode_property_read_u32(child, ad4170_i_out_pin_dt_props[i], 1885 &pin); 1886 if (ret) 1887 continue; 1888 1889 exc_pins[num_pins] = pin; 1890 1891 /* Parse excitation current value properties. */ 1892 val = ad4170_iout_current_ua_tbl[0]; 1893 fwnode_property_read_u32(child, 1894 ad4170_i_out_val_dt_props[i], &val); 1895 1896 for (j = 0; j < ARRAY_SIZE(ad4170_iout_current_ua_tbl); j++) 1897 if (ad4170_iout_current_ua_tbl[j] == val) 1898 break; 1899 1900 if (j == ARRAY_SIZE(ad4170_iout_current_ua_tbl)) 1901 return dev_err_probe(dev, -EINVAL, "Invalid %s: %uuA\n", 1902 ad4170_i_out_val_dt_props[i], val); 1903 1904 exc_curs[num_pins] = j; 1905 num_pins++; 1906 } 1907 *num_exc_pins = num_pins; 1908 1909 return 0; 1910 } 1911 1912 static int ad4170_setup_current_src(struct ad4170_state *st, 1913 struct fwnode_handle *child, 1914 struct ad4170_setup *setup, u32 *exc_pins, 1915 unsigned int *exc_curs, int num_exc_pins, 1916 bool ac_excited) 1917 { 1918 unsigned int exc_cur_pair, i, j; 1919 int ret; 1920 1921 for (i = 0; i < num_exc_pins; i++) { 1922 unsigned int exc_cur = exc_curs[i]; 1923 unsigned int pin = exc_pins[i]; 1924 unsigned int current_src = 0; 1925 1926 for (j = 0; j < AD4170_NUM_CURRENT_SRC; j++) 1927 if (st->cur_src_pins[j] == AD4170_CURRENT_SRC_DISABLED) 1928 break; 1929 1930 if (j == AD4170_NUM_CURRENT_SRC) 1931 return dev_err_probe(&st->spi->dev, -EINVAL, 1932 "Too many excitation current sources\n"); 1933 1934 current_src |= FIELD_PREP(AD4170_CURRENT_SRC_I_OUT_PIN_MSK, pin); 1935 current_src |= FIELD_PREP(AD4170_CURRENT_SRC_I_OUT_VAL_MSK, exc_cur); 1936 st->cur_src_pins[j] = pin; 1937 ret = regmap_write(st->regmap, AD4170_CURRENT_SRC_REG(j), 1938 current_src); 1939 if (ret) 1940 return ret; 1941 } 1942 1943 if (!ac_excited) 1944 return 0; 1945 1946 if (num_exc_pins < 2) 1947 return dev_err_probe(&st->spi->dev, -EINVAL, 1948 "Current chopping requested but only one pin provided: %u\n", 1949 exc_pins[0]); 1950 1951 /* 1952 * Two use cases to handle here: 1953 * - 2 pairs of excitation currents; 1954 * - 1 pair of excitation currents. 1955 */ 1956 if (num_exc_pins == 4) { 1957 for (i = 0; i < AD4170_NUM_CURRENT_SRC; i++) 1958 if (st->cur_src_pins[i] != exc_pins[i]) 1959 return dev_err_probe(&st->spi->dev, -EINVAL, 1960 "Unable to use 4 exc pins\n"); 1961 } else { 1962 /* 1963 * Excitation current chopping is configured in pairs. Current 1964 * sources IOUT0 and IOUT1 form pair 1, IOUT2 and IOUT3 make up 1965 * pair 2. So, if current chopping was requested, check if the 1966 * first end of the first pair of excitation currents is 1967 * available. Try the next pair if IOUT0 has already been 1968 * configured for another channel. 1969 */ 1970 i = st->cur_src_pins[0] == exc_pins[0] ? 0 : 2; 1971 1972 if (st->cur_src_pins[i] != exc_pins[0] || 1973 st->cur_src_pins[i + 1] != exc_pins[1]) 1974 return dev_err_probe(&st->spi->dev, -EINVAL, 1975 "Failed to setup current chopping\n"); 1976 1977 st->cur_src_pins[i] = exc_pins[0]; 1978 st->cur_src_pins[i + 1] = exc_pins[1]; 1979 1980 if (i == 0) 1981 exc_cur_pair = AD4170_MISC_CHOP_IEXC_PAIR1; 1982 else 1983 exc_cur_pair = AD4170_MISC_CHOP_IEXC_PAIR2; 1984 } 1985 1986 /* 1987 * Configure excitation current chopping. 1988 * Chop both pairs if using four excitation pins. 1989 */ 1990 setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_IEXC_MSK, 1991 num_exc_pins == 2 ? 1992 exc_cur_pair : 1993 AD4170_MISC_CHOP_IEXC_BOTH); 1994 1995 return 0; 1996 } 1997 1998 static int ad4170_setup_bridge(struct ad4170_state *st, 1999 struct fwnode_handle *child, 2000 struct ad4170_setup *setup, u32 *exc_pins, 2001 unsigned int *exc_curs, int num_exc_pins, 2002 bool ac_excited) 2003 { 2004 unsigned long gpio_mask; 2005 unsigned int i; 2006 int ret; 2007 2008 /* 2009 * If a specific current is provided through 2010 * adi,excitation-current-n-microamp, set excitation pins provided 2011 * through adi,excitation-pin-n to excite the bridge circuit. 2012 */ 2013 for (i = 0; i < num_exc_pins; i++) 2014 if (exc_curs[i] > 0) 2015 return ad4170_setup_current_src(st, child, setup, exc_pins, 2016 exc_curs, num_exc_pins, 2017 ac_excited); 2018 2019 /* 2020 * Else, use predefined ACX1, ACX1 negated, ACX2, ACX2 negated signals 2021 * to AC excite the bridge. Those signals are output on GPIO2, GPIO0, 2022 * GPIO3, and GPIO1, respectively. If only two pins are specified for AC 2023 * excitation, use ACX1 and ACX2 (GPIO2 and GPIO3). 2024 * 2025 * Also, to avoid any short-circuit condition when more than one channel 2026 * is enabled, set GPIO2 and GPIO0 high, and set GPIO1 and GPIO3 low to 2027 * DC excite the bridge whenever a channel without AC excitation is 2028 * selected. That is needed because GPIO pins are controlled by the next 2029 * highest priority GPIO function when a channel doesn't enable AC 2030 * excitation. See datasheet Figure 113 Weigh Scale (AC Excitation) for 2031 * the reference circuit diagram. 2032 */ 2033 if (num_exc_pins == 2) { 2034 setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_ADC_MSK, 0x3); 2035 2036 gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK | AD4170_GPIO_MODE_GPIO2_MSK; 2037 ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask, 2038 FIELD_PREP(AD4170_GPIO_MODE_GPIO3_MSK, 2039 AD4170_GPIO_MODE_GPIO_OUTPUT) | 2040 FIELD_PREP(AD4170_GPIO_MODE_GPIO2_MSK, 2041 AD4170_GPIO_MODE_GPIO_OUTPUT)); 2042 if (ret) 2043 return ret; 2044 2045 /* 2046 * Set GPIO2 high and GPIO3 low to DC excite the bridge when 2047 * a different channel is selected. 2048 */ 2049 gpio_mask = AD4170_GPIO_OUTPUT_GPIO_MSK(3) | 2050 AD4170_GPIO_OUTPUT_GPIO_MSK(2); 2051 ret = regmap_update_bits(st->regmap, AD4170_GPIO_OUTPUT_REG, gpio_mask, 2052 FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(3), 0) | 2053 FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(2), 1)); 2054 if (ret) 2055 return ret; 2056 2057 st->gpio_fn[3] |= AD4170_GPIO_OUTPUT; 2058 st->gpio_fn[2] |= AD4170_GPIO_OUTPUT; 2059 } else { 2060 setup->misc |= FIELD_PREP(AD4170_MISC_CHOP_ADC_MSK, 0x2); 2061 2062 gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK | AD4170_GPIO_MODE_GPIO2_MSK | 2063 AD4170_GPIO_MODE_GPIO1_MSK | AD4170_GPIO_MODE_GPIO0_MSK; 2064 ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask, 2065 FIELD_PREP(AD4170_GPIO_MODE_GPIO3_MSK, 2066 AD4170_GPIO_MODE_GPIO_OUTPUT) | 2067 FIELD_PREP(AD4170_GPIO_MODE_GPIO2_MSK, 2068 AD4170_GPIO_MODE_GPIO_OUTPUT) | 2069 FIELD_PREP(AD4170_GPIO_MODE_GPIO1_MSK, 2070 AD4170_GPIO_MODE_GPIO_OUTPUT) | 2071 FIELD_PREP(AD4170_GPIO_MODE_GPIO0_MSK, 2072 AD4170_GPIO_MODE_GPIO_OUTPUT)); 2073 if (ret) 2074 return ret; 2075 2076 /* 2077 * Set GPIO2 and GPIO0 high, and set GPIO1 and GPIO3 low to DC 2078 * excite the bridge when a different channel is selected. 2079 */ 2080 gpio_mask = AD4170_GPIO_OUTPUT_GPIO_MSK(3) | 2081 AD4170_GPIO_OUTPUT_GPIO_MSK(2) | 2082 AD4170_GPIO_OUTPUT_GPIO_MSK(1) | 2083 AD4170_GPIO_OUTPUT_GPIO_MSK(0); 2084 ret = regmap_update_bits(st->regmap, AD4170_GPIO_OUTPUT_REG, gpio_mask, 2085 FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(3), 0) | 2086 FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(2), 1) | 2087 FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(1), 0) | 2088 FIELD_PREP(AD4170_GPIO_OUTPUT_GPIO_MSK(0), 1)); 2089 if (ret) 2090 return ret; 2091 2092 st->gpio_fn[3] |= AD4170_GPIO_OUTPUT; 2093 st->gpio_fn[2] |= AD4170_GPIO_OUTPUT; 2094 st->gpio_fn[1] |= AD4170_GPIO_OUTPUT; 2095 st->gpio_fn[0] |= AD4170_GPIO_OUTPUT; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static int ad4170_setup_rtd(struct ad4170_state *st, 2102 struct fwnode_handle *child, 2103 struct ad4170_setup *setup, u32 *exc_pins, 2104 unsigned int *exc_curs, int num_exc_pins, bool ac_excited) 2105 { 2106 return ad4170_setup_current_src(st, child, setup, exc_pins, 2107 exc_curs, num_exc_pins, ac_excited); 2108 } 2109 2110 static int ad4170_parse_external_sensor(struct ad4170_state *st, 2111 struct fwnode_handle *child, 2112 struct ad4170_setup *setup, 2113 struct iio_chan_spec *chan, 2114 unsigned int s_type) 2115 { 2116 unsigned int num_exc_pins, reg_val; 2117 struct device *dev = &st->spi->dev; 2118 u32 pins[2], exc_pins[4], exc_curs[4]; 2119 bool ac_excited; 2120 int ret; 2121 2122 ret = fwnode_property_read_u32_array(child, "diff-channels", pins, 2123 ARRAY_SIZE(pins)); 2124 if (ret) 2125 return dev_err_probe(dev, ret, 2126 "Failed to read sensor diff-channels\n"); 2127 2128 chan->differential = true; 2129 chan->channel = pins[0]; 2130 chan->channel2 = pins[1]; 2131 2132 ret = ad4170_parse_exc_current(st, child, exc_pins, exc_curs, &num_exc_pins); 2133 if (ret) 2134 return ret; 2135 2136 /* The external sensor may not need excitation from the ADC chip. */ 2137 if (num_exc_pins == 0) 2138 return 0; 2139 2140 ret = ad4170_validate_excitation_pins(st, exc_pins, num_exc_pins); 2141 if (ret) 2142 return ret; 2143 2144 ac_excited = fwnode_property_read_bool(child, "adi,excitation-ac"); 2145 2146 if (s_type == AD4170_THERMOCOUPLE_SENSOR) { 2147 if (st->pins_fn[chan->channel2] & AD4170_PIN_VBIAS) { 2148 reg_val = BIT(chan->channel2); 2149 ret = regmap_write(st->regmap, AD4170_V_BIAS_REG, reg_val); 2150 if (ret) 2151 dev_err_probe(dev, ret, "Failed to set vbias\n"); 2152 } 2153 } 2154 if (s_type == AD4170_WEIGH_SCALE_SENSOR) 2155 ret = ad4170_setup_bridge(st, child, setup, exc_pins, exc_curs, 2156 num_exc_pins, ac_excited); 2157 else 2158 ret = ad4170_setup_rtd(st, child, setup, exc_pins, exc_curs, 2159 num_exc_pins, ac_excited); 2160 2161 return ret; 2162 } 2163 2164 static int ad4170_parse_reference(struct ad4170_state *st, 2165 struct fwnode_handle *child, 2166 struct ad4170_setup *setup) 2167 { 2168 struct device *dev = &st->spi->dev; 2169 const char *propname; 2170 u32 aux; 2171 int ret; 2172 2173 /* Optional positive reference buffering */ 2174 propname = "adi,positive-reference-buffer"; 2175 ret = device_property_match_property_string(dev, propname, 2176 ad4170_ref_buf_str, 2177 ARRAY_SIZE(ad4170_ref_buf_str)); 2178 2179 /* Default to full precharge buffer enabled. */ 2180 setup->afe |= FIELD_PREP(AD4170_AFE_REF_BUF_P_MSK, 2181 ret >= 0 ? ret : AD4170_REF_BUF_FULL); 2182 2183 /* Optional negative reference buffering */ 2184 propname = "adi,negative-reference-buffer"; 2185 ret = device_property_match_property_string(dev, propname, 2186 ad4170_ref_buf_str, 2187 ARRAY_SIZE(ad4170_ref_buf_str)); 2188 2189 /* Default to full precharge buffer enabled. */ 2190 setup->afe |= FIELD_PREP(AD4170_AFE_REF_BUF_M_MSK, 2191 ret >= 0 ? ret : AD4170_REF_BUF_FULL); 2192 2193 /* Optional voltage reference selection */ 2194 propname = "adi,reference-select"; 2195 aux = AD4170_REF_REFOUT; /* Default reference selection. */ 2196 fwnode_property_read_u32(child, propname, &aux); 2197 if (aux > AD4170_REF_AVDD) 2198 return dev_err_probe(dev, -EINVAL, "Invalid %s: %u\n", 2199 propname, aux); 2200 2201 setup->afe |= FIELD_PREP(AD4170_AFE_REF_SELECT_MSK, aux); 2202 2203 return 0; 2204 } 2205 2206 static int ad4170_parse_adc_channel_type(struct device *dev, 2207 struct fwnode_handle *child, 2208 struct iio_chan_spec *chan) 2209 { 2210 const char *propname, *propname2; 2211 int ret, ret2; 2212 u32 pins[2]; 2213 2214 propname = "single-channel"; 2215 propname2 = "diff-channels"; 2216 if (!fwnode_property_present(child, propname) && 2217 !fwnode_property_present(child, propname2)) 2218 return dev_err_probe(dev, -EINVAL, 2219 "Channel must define one of %s or %s.\n", 2220 propname, propname2); 2221 2222 /* Parse differential channel configuration */ 2223 ret = fwnode_property_read_u32_array(child, propname2, pins, 2224 ARRAY_SIZE(pins)); 2225 if (!ret) { 2226 chan->differential = true; 2227 chan->channel = pins[0]; 2228 chan->channel2 = pins[1]; 2229 return 0; 2230 } 2231 /* Failed to parse diff chan so try pseudo-diff chan props */ 2232 2233 propname2 = "common-mode-channel"; 2234 if (fwnode_property_present(child, propname) && 2235 !fwnode_property_present(child, propname2)) 2236 return dev_err_probe(dev, -EINVAL, 2237 "When %s is defined, %s must be defined too\n", 2238 propname, propname2); 2239 2240 /* Parse pseudo-differential channel configuration */ 2241 ret = fwnode_property_read_u32(child, propname, &pins[0]); 2242 ret2 = fwnode_property_read_u32(child, propname2, &pins[1]); 2243 2244 if (!ret && !ret2) { 2245 chan->differential = false; 2246 chan->channel = pins[0]; 2247 chan->channel2 = pins[1]; 2248 return 0; 2249 } 2250 return dev_err_probe(dev, -EINVAL, 2251 "Failed to parse channel %lu input. %d, %d\n", 2252 chan->address, ret, ret2); 2253 } 2254 2255 static int ad4170_parse_channel_node(struct iio_dev *indio_dev, 2256 struct fwnode_handle *child, 2257 unsigned int chan_num) 2258 { 2259 struct ad4170_state *st = iio_priv(indio_dev); 2260 unsigned int s_type = AD4170_ADC_SENSOR; 2261 struct device *dev = &st->spi->dev; 2262 struct ad4170_chan_info *chan_info; 2263 struct ad4170_setup *setup; 2264 struct iio_chan_spec *chan; 2265 unsigned int ref_select; 2266 unsigned int ch_reg; 2267 bool bipolar; 2268 int ret; 2269 2270 ret = fwnode_property_read_u32(child, "reg", &ch_reg); 2271 if (ret) 2272 return dev_err_probe(dev, ret, "Failed to read channel reg\n"); 2273 2274 if (ch_reg >= AD4170_MAX_ADC_CHANNELS) 2275 return dev_err_probe(dev, -EINVAL, 2276 "Channel idx greater than no of channels\n"); 2277 2278 chan = &st->chans[chan_num]; 2279 *chan = ad4170_channel_template; 2280 2281 chan->address = ch_reg; 2282 chan->scan_index = ch_reg; 2283 chan_info = &st->chan_infos[chan->address]; 2284 2285 chan_info->setup_num = AD4170_INVALID_SETUP; 2286 chan_info->initialized = true; 2287 2288 setup = &chan_info->setup; 2289 ret = ad4170_parse_reference(st, child, setup); 2290 if (ret) 2291 return ret; 2292 2293 ret = fwnode_property_match_property_string(child, "adi,sensor-type", 2294 ad4170_sensor_type, 2295 ARRAY_SIZE(ad4170_sensor_type)); 2296 2297 /* Default to conventional ADC channel if sensor type not present */ 2298 s_type = ret < 0 ? AD4170_ADC_SENSOR : ret; 2299 switch (s_type) { 2300 case AD4170_ADC_SENSOR: 2301 ret = ad4170_parse_adc_channel_type(dev, child, chan); 2302 if (ret) 2303 return ret; 2304 2305 break; 2306 case AD4170_WEIGH_SCALE_SENSOR: 2307 case AD4170_THERMOCOUPLE_SENSOR: 2308 case AD4170_RTD_SENSOR: 2309 ret = ad4170_parse_external_sensor(st, child, setup, chan, s_type); 2310 if (ret) 2311 return ret; 2312 2313 break; 2314 default: 2315 return -EINVAL; 2316 } 2317 2318 bipolar = fwnode_property_read_bool(child, "bipolar"); 2319 setup->afe |= FIELD_PREP(AD4170_AFE_BIPOLAR_MSK, bipolar); 2320 if (bipolar) 2321 chan->scan_type.sign = 's'; 2322 else 2323 chan->scan_type.sign = 'u'; 2324 2325 ret = ad4170_validate_channel(st, chan); 2326 if (ret) 2327 return ret; 2328 2329 ref_select = FIELD_GET(AD4170_AFE_REF_SELECT_MSK, setup->afe); 2330 ret = ad4170_get_input_range(st, chan, ch_reg, ref_select); 2331 if (ret < 0) 2332 return dev_err_probe(dev, ret, "Invalid input config\n"); 2333 2334 chan_info->input_range_uv = ret; 2335 return 0; 2336 } 2337 2338 static int ad4170_parse_channels(struct iio_dev *indio_dev) 2339 { 2340 struct ad4170_state *st = iio_priv(indio_dev); 2341 struct device *dev = &st->spi->dev; 2342 unsigned int num_channels; 2343 unsigned int chan_num; 2344 int ret; 2345 2346 num_channels = device_get_child_node_count(dev); 2347 2348 if (num_channels > AD4170_MAX_ADC_CHANNELS) 2349 return dev_err_probe(dev, -EINVAL, "Too many channels\n"); 2350 2351 /* Add one for temperature */ 2352 num_channels = min(num_channels + 1, AD4170_MAX_ADC_CHANNELS); 2353 2354 chan_num = 0; 2355 device_for_each_child_node_scoped(dev, child) { 2356 ret = ad4170_parse_channel_node(indio_dev, child, chan_num++); 2357 if (ret) 2358 return ret; 2359 } 2360 2361 /* 2362 * Add internal temperature sensor channel if the maximum number of 2363 * channels has not been reached. 2364 */ 2365 if (num_channels < AD4170_MAX_ADC_CHANNELS) { 2366 struct ad4170_setup *setup = &st->chan_infos[chan_num].setup; 2367 2368 st->chans[chan_num] = ad4170_temp_channel_template; 2369 st->chans[chan_num].address = chan_num; 2370 st->chans[chan_num].scan_index = chan_num; 2371 2372 st->chan_infos[chan_num].setup_num = AD4170_INVALID_SETUP; 2373 st->chan_infos[chan_num].initialized = true; 2374 2375 setup->afe |= FIELD_PREP(AD4170_AFE_REF_SELECT_MSK, 2376 AD4170_REF_AVDD); 2377 2378 ret = ad4170_get_input_range(st, &st->chans[chan_num], chan_num, 2379 AD4170_REF_AVDD); 2380 if (ret < 0) 2381 return dev_err_probe(dev, ret, "Invalid input config\n"); 2382 2383 st->chan_infos[chan_num].input_range_uv = ret; 2384 chan_num++; 2385 } 2386 2387 /* Add timestamp channel */ 2388 struct iio_chan_spec ts_chan = IIO_CHAN_SOFT_TIMESTAMP(chan_num); 2389 2390 st->chans[chan_num] = ts_chan; 2391 num_channels = num_channels + 1; 2392 2393 indio_dev->num_channels = num_channels; 2394 indio_dev->channels = st->chans; 2395 2396 return 0; 2397 } 2398 2399 static struct ad4170_state *clk_hw_to_ad4170(struct clk_hw *hw) 2400 { 2401 return container_of(hw, struct ad4170_state, int_clk_hw); 2402 } 2403 2404 static unsigned long ad4170_sel_clk(struct ad4170_state *st, 2405 unsigned int clk_sel) 2406 { 2407 st->clock_ctrl &= ~AD4170_CLOCK_CTRL_CLOCKSEL_MSK; 2408 st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, clk_sel); 2409 return regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl); 2410 } 2411 2412 static unsigned long ad4170_clk_recalc_rate(struct clk_hw *hw, 2413 unsigned long parent_rate) 2414 { 2415 return AD4170_INT_CLOCK_16MHZ; 2416 } 2417 2418 static int ad4170_clk_output_is_enabled(struct clk_hw *hw) 2419 { 2420 struct ad4170_state *st = clk_hw_to_ad4170(hw); 2421 u32 clk_sel; 2422 2423 clk_sel = FIELD_GET(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, st->clock_ctrl); 2424 return clk_sel == AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT; 2425 } 2426 2427 static int ad4170_clk_output_prepare(struct clk_hw *hw) 2428 { 2429 struct ad4170_state *st = clk_hw_to_ad4170(hw); 2430 2431 return ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT); 2432 } 2433 2434 static void ad4170_clk_output_unprepare(struct clk_hw *hw) 2435 { 2436 struct ad4170_state *st = clk_hw_to_ad4170(hw); 2437 2438 ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT); 2439 } 2440 2441 static const struct clk_ops ad4170_int_clk_ops = { 2442 .recalc_rate = ad4170_clk_recalc_rate, 2443 .is_enabled = ad4170_clk_output_is_enabled, 2444 .prepare = ad4170_clk_output_prepare, 2445 .unprepare = ad4170_clk_output_unprepare, 2446 }; 2447 2448 static int ad4170_register_clk_provider(struct iio_dev *indio_dev) 2449 { 2450 struct ad4170_state *st = iio_priv(indio_dev); 2451 struct device *dev = indio_dev->dev.parent; 2452 struct clk_init_data init = {}; 2453 int ret; 2454 2455 if (device_property_read_string(dev, "clock-output-names", &init.name)) { 2456 init.name = devm_kasprintf(dev, GFP_KERNEL, "%pfw", 2457 dev_fwnode(dev)); 2458 if (!init.name) 2459 return -ENOMEM; 2460 } 2461 2462 init.ops = &ad4170_int_clk_ops; 2463 2464 st->int_clk_hw.init = &init; 2465 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 2466 if (ret) 2467 return ret; 2468 2469 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2470 &st->int_clk_hw); 2471 } 2472 2473 static int ad4170_clock_select(struct iio_dev *indio_dev) 2474 { 2475 struct ad4170_state *st = iio_priv(indio_dev); 2476 struct device *dev = &st->spi->dev; 2477 struct clk *ext_clk; 2478 int ret; 2479 2480 ext_clk = devm_clk_get_optional_enabled(dev, NULL); 2481 if (IS_ERR(ext_clk)) 2482 return dev_err_probe(dev, PTR_ERR(ext_clk), 2483 "Failed to get external clock\n"); 2484 2485 if (!ext_clk) { 2486 /* Use internal clock reference */ 2487 st->mclk_hz = AD4170_INT_CLOCK_16MHZ; 2488 st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, 2489 AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT); 2490 2491 if (!device_property_present(&st->spi->dev, "#clock-cells")) 2492 return 0; 2493 2494 return ad4170_register_clk_provider(indio_dev); 2495 } 2496 2497 /* Read optional clock-names prop to specify the external clock type */ 2498 ret = device_property_match_property_string(dev, "clock-names", 2499 ad4170_clk_sel, 2500 ARRAY_SIZE(ad4170_clk_sel)); 2501 2502 ret = ret < 0 ? 0 : ret; /* Default to external clock if no clock-names */ 2503 st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, 2504 AD4170_CLOCK_CTRL_CLOCKSEL_EXT + ret); 2505 2506 st->mclk_hz = clk_get_rate(ext_clk); 2507 if (st->mclk_hz < AD4170_EXT_CLOCK_MHZ_MIN || 2508 st->mclk_hz > AD4170_EXT_CLOCK_MHZ_MAX) { 2509 return dev_err_probe(dev, -EINVAL, 2510 "Invalid external clock frequency %u\n", 2511 st->mclk_hz); 2512 } 2513 2514 return 0; 2515 } 2516 2517 static int ad4170_parse_firmware(struct iio_dev *indio_dev) 2518 { 2519 unsigned int vbias_pins[AD4170_MAX_ANALOG_PINS]; 2520 struct ad4170_state *st = iio_priv(indio_dev); 2521 struct device *dev = &st->spi->dev; 2522 unsigned int num_vbias_pins; 2523 int reg_data, ret; 2524 u32 int_pin_sel; 2525 unsigned int i; 2526 2527 ret = ad4170_clock_select(indio_dev); 2528 if (ret) 2529 return dev_err_probe(dev, ret, "Failed to setup device clock\n"); 2530 2531 ret = regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl); 2532 if (ret) 2533 return ret; 2534 2535 for (i = 0; i < AD4170_NUM_CURRENT_SRC; i++) 2536 st->cur_src_pins[i] = AD4170_CURRENT_SRC_DISABLED; 2537 2538 /* On power on, device defaults to using SDO pin for data ready signal */ 2539 int_pin_sel = AD4170_INT_PIN_SDO; 2540 ret = device_property_match_property_string(dev, "interrupt-names", 2541 ad4170_int_pin_names, 2542 ARRAY_SIZE(ad4170_int_pin_names)); 2543 if (ret >= 0) 2544 int_pin_sel = ret; 2545 2546 reg_data = FIELD_PREP(AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK, 2547 int_pin_sel == AD4170_INT_PIN_DIG_AUX1 ? 2548 AD4170_PIN_MUXING_DIG_AUX1_RDY : 2549 AD4170_PIN_MUXING_DIG_AUX1_DISABLED); 2550 2551 ret = regmap_update_bits(st->regmap, AD4170_PIN_MUXING_REG, 2552 AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK, reg_data); 2553 if (ret) 2554 return ret; 2555 2556 ret = device_property_count_u32(dev, "adi,vbias-pins"); 2557 if (ret > 0) { 2558 if (ret > AD4170_MAX_ANALOG_PINS) 2559 return dev_err_probe(dev, -EINVAL, 2560 "Too many vbias pins %u\n", ret); 2561 2562 num_vbias_pins = ret; 2563 2564 ret = device_property_read_u32_array(dev, "adi,vbias-pins", 2565 vbias_pins, 2566 num_vbias_pins); 2567 if (ret) 2568 return dev_err_probe(dev, ret, 2569 "Failed to read vbias pins\n"); 2570 2571 for (i = 0; i < num_vbias_pins; i++) 2572 st->pins_fn[vbias_pins[i]] |= AD4170_PIN_VBIAS; 2573 } 2574 2575 ret = ad4170_parse_channels(indio_dev); 2576 if (ret) 2577 return ret; 2578 2579 /* Only create a GPIO chip if flagged for it */ 2580 if (device_property_read_bool(dev, "gpio-controller")) { 2581 ret = ad4170_gpio_init(indio_dev); 2582 if (ret) 2583 return ret; 2584 } 2585 2586 return 0; 2587 } 2588 2589 static int ad4170_initial_config(struct iio_dev *indio_dev) 2590 { 2591 struct ad4170_state *st = iio_priv(indio_dev); 2592 struct device *dev = &st->spi->dev; 2593 unsigned int i; 2594 int ret; 2595 2596 ad4170_fill_sps_tbl(st); 2597 2598 ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2599 AD4170_ADC_CTRL_MODE_MSK, 2600 FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK, 2601 AD4170_ADC_CTRL_MODE_IDLE)); 2602 if (ret) 2603 return dev_err_probe(dev, ret, 2604 "Failed to set ADC mode to idle\n"); 2605 2606 for (i = 0; i < indio_dev->num_channels; i++) { 2607 struct ad4170_chan_info *chan_info; 2608 struct iio_chan_spec const *chan; 2609 struct ad4170_setup *setup; 2610 unsigned int val; 2611 2612 chan = &indio_dev->channels[i]; 2613 if (chan->type == IIO_TIMESTAMP) 2614 continue; 2615 2616 chan_info = &st->chan_infos[chan->address]; 2617 2618 setup = &chan_info->setup; 2619 setup->gain = AD4170_GAIN_REG_DEFAULT; 2620 ret = ad4170_write_channel_setup(st, chan->address, false); 2621 if (ret) 2622 return dev_err_probe(dev, ret, 2623 "Failed to write channel setup\n"); 2624 2625 val = FIELD_PREP(AD4170_CHAN_MAP_AINP_MSK, chan->channel) | 2626 FIELD_PREP(AD4170_CHAN_MAP_AINM_MSK, chan->channel2); 2627 2628 ret = regmap_write(st->regmap, AD4170_CHAN_MAP_REG(i), val); 2629 if (ret) 2630 return dev_err_probe(dev, ret, 2631 "Failed to write CHAN_MAP_REG\n"); 2632 2633 ret = ad4170_set_channel_freq(st, chan, 2634 AD4170_DEFAULT_SAMP_RATE, 0); 2635 if (ret) 2636 return dev_err_probe(dev, ret, 2637 "Failed to set channel freq\n"); 2638 2639 ret = ad4170_fill_scale_tbl(indio_dev, chan); 2640 if (ret) 2641 return dev_err_probe(dev, ret, 2642 "Failed to fill scale tbl\n"); 2643 } 2644 2645 /* Disable all channels to avoid reading from unexpected channel */ 2646 ret = regmap_write(st->regmap, AD4170_CHAN_EN_REG, 0); 2647 if (ret) 2648 return dev_err_probe(dev, ret, 2649 "Failed to disable channels\n"); 2650 2651 /* 2652 * Configure channels to share the same data output register, i.e. data 2653 * can be read from the same register address regardless of channel 2654 * number. 2655 */ 2656 return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2657 AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK, 2658 AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK); 2659 } 2660 2661 static int ad4170_prepare_spi_message(struct ad4170_state *st) 2662 { 2663 /* 2664 * Continuous data register read is enabled on buffer postenable so 2665 * no instruction phase is needed meaning we don't need to send the 2666 * register address to read data. Transfer only needs the read buffer. 2667 */ 2668 st->xfer.rx_buf = &st->rx_buf; 2669 st->xfer.len = BITS_TO_BYTES(ad4170_channel_template.scan_type.realbits); 2670 2671 spi_message_init_with_transfers(&st->msg, &st->xfer, 1); 2672 2673 return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg); 2674 } 2675 2676 static int ad4170_buffer_postenable(struct iio_dev *indio_dev) 2677 { 2678 struct ad4170_state *st = iio_priv(indio_dev); 2679 int ret; 2680 2681 ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2682 AD4170_ADC_CTRL_MODE_MSK, 2683 FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK, 2684 AD4170_ADC_CTRL_MODE_CONT)); 2685 if (ret) 2686 return ret; 2687 2688 /* 2689 * This enables continuous read of the ADC data register. The ADC must 2690 * be in continuous conversion mode. 2691 */ 2692 return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2693 AD4170_ADC_CTRL_CONT_READ_MSK, 2694 FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK, 2695 AD4170_ADC_CTRL_CONT_READ_ENABLE)); 2696 } 2697 2698 static int ad4170_buffer_predisable(struct iio_dev *indio_dev) 2699 { 2700 struct ad4170_state *st = iio_priv(indio_dev); 2701 unsigned int i; 2702 int ret; 2703 2704 /* 2705 * Use a high register address (virtual register) to request a write of 2706 * 0xA5 to the ADC during the first 8 SCLKs of the ADC data read cycle, 2707 * thus exiting continuous read. 2708 */ 2709 ret = regmap_write(st->regmap, AD4170_ADC_CTRL_CONT_READ_EXIT_REG, 0); 2710 if (ret) 2711 return ret; 2712 2713 ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2714 AD4170_ADC_CTRL_CONT_READ_MSK, 2715 FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK, 2716 AD4170_ADC_CTRL_CONT_READ_DISABLE)); 2717 if (ret) 2718 return ret; 2719 2720 ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, 2721 AD4170_ADC_CTRL_MODE_MSK, 2722 FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK, 2723 AD4170_ADC_CTRL_MODE_IDLE)); 2724 if (ret) 2725 return ret; 2726 2727 /* 2728 * The ADC sequences through all the enabled channels (see datasheet 2729 * page 95). That can lead to incorrect channel being read if a 2730 * single-shot read (or buffered read with different active_scan_mask) 2731 * is done after buffer disable. Disable all channels so only requested 2732 * channels will be read. 2733 */ 2734 for (i = 0; i < indio_dev->num_channels; i++) { 2735 if (indio_dev->channels[i].type == IIO_TIMESTAMP) 2736 continue; 2737 2738 ret = ad4170_set_channel_enable(st, i, false); 2739 if (ret) 2740 return ret; 2741 } 2742 2743 return 0; 2744 } 2745 2746 static bool ad4170_validate_scan_mask(struct iio_dev *indio_dev, 2747 const unsigned long *scan_mask) 2748 { 2749 unsigned int masklength = iio_get_masklength(indio_dev); 2750 unsigned int enabled; 2751 2752 /* 2753 * The channel sequencer cycles through the enabled channels in 2754 * sequential order, from channel 0 to channel 15, bypassing disabled 2755 * channels. When more than one channel is enabled, channel 0 must 2756 * always be enabled. See datasheet channel_en register description at 2757 * page 95. 2758 */ 2759 enabled = bitmap_weight(scan_mask, masklength); 2760 if (enabled > 1) 2761 return test_bit(0, scan_mask); 2762 2763 return enabled == 1; 2764 } 2765 2766 static const struct iio_buffer_setup_ops ad4170_buffer_ops = { 2767 .postenable = ad4170_buffer_postenable, 2768 .predisable = ad4170_buffer_predisable, 2769 .validate_scan_mask = ad4170_validate_scan_mask, 2770 }; 2771 2772 static irqreturn_t ad4170_trigger_handler(int irq, void *p) 2773 { 2774 struct iio_poll_func *pf = p; 2775 struct iio_dev *indio_dev = pf->indio_dev; 2776 struct ad4170_state *st = iio_priv(indio_dev); 2777 unsigned int chan_index; 2778 unsigned int i = 0; 2779 int ret; 2780 2781 iio_for_each_active_channel(indio_dev, chan_index) { 2782 ret = spi_sync(st->spi, &st->msg); 2783 if (ret) 2784 goto err_out; 2785 2786 memcpy(&st->bounce_buffer[i++], st->rx_buf, ARRAY_SIZE(st->rx_buf)); 2787 } 2788 2789 iio_push_to_buffers_with_ts(indio_dev, st->bounce_buffer, 2790 sizeof(st->bounce_buffer), 2791 iio_get_time_ns(indio_dev)); 2792 err_out: 2793 iio_trigger_notify_done(indio_dev->trig); 2794 return IRQ_HANDLED; 2795 } 2796 2797 static const struct iio_trigger_ops ad4170_trigger_ops = { 2798 .validate_device = iio_trigger_validate_own_device, 2799 }; 2800 2801 static irqreturn_t ad4170_irq_handler(int irq, void *dev_id) 2802 { 2803 struct iio_dev *indio_dev = dev_id; 2804 struct ad4170_state *st = iio_priv(indio_dev); 2805 2806 if (iio_buffer_enabled(indio_dev)) 2807 iio_trigger_poll(st->trig); 2808 else 2809 complete(&st->completion); 2810 2811 return IRQ_HANDLED; 2812 }; 2813 2814 static int ad4170_trigger_setup(struct iio_dev *indio_dev) 2815 { 2816 struct ad4170_state *st = iio_priv(indio_dev); 2817 struct device *dev = &st->spi->dev; 2818 int ret; 2819 2820 st->trig = devm_iio_trigger_alloc(dev, "%s-trig%d", 2821 indio_dev->name, 2822 iio_device_id(indio_dev)); 2823 if (!st->trig) 2824 return -ENOMEM; 2825 2826 st->trig->ops = &ad4170_trigger_ops; 2827 2828 iio_trigger_set_drvdata(st->trig, indio_dev); 2829 ret = devm_iio_trigger_register(dev, st->trig); 2830 if (ret) 2831 return dev_err_probe(dev, ret, "Failed to register trigger\n"); 2832 2833 indio_dev->trig = iio_trigger_get(st->trig); 2834 2835 return 0; 2836 } 2837 2838 static int ad4170_regulator_setup(struct ad4170_state *st) 2839 { 2840 struct device *dev = &st->spi->dev; 2841 int ret; 2842 2843 /* Required regulators */ 2844 ret = devm_regulator_get_enable_read_voltage(dev, "avdd"); 2845 if (ret < 0) 2846 return dev_err_probe(dev, ret, "Failed to get AVDD voltage.\n"); 2847 2848 st->vrefs_uv[AD4170_AVDD_SUP] = ret; 2849 2850 ret = devm_regulator_get_enable_read_voltage(dev, "iovdd"); 2851 if (ret < 0) 2852 return dev_err_probe(dev, ret, "Failed to get IOVDD voltage.\n"); 2853 2854 st->vrefs_uv[AD4170_IOVDD_SUP] = ret; 2855 2856 /* Optional regulators */ 2857 ret = devm_regulator_get_enable_read_voltage(dev, "avss"); 2858 if (ret < 0 && ret != -ENODEV) 2859 return dev_err_probe(dev, ret, "Failed to get AVSS voltage.\n"); 2860 2861 /* 2862 * Assume AVSS at GND (0V) if not provided. 2863 * REVISIT: AVSS is never above system ground level (i.e. AVSS is either 2864 * GND or a negative voltage). But we currently don't have support for 2865 * reading negative voltages with the regulator framework. So, the 2866 * current AD4170 support reads a positive value from the regulator, 2867 * then inverts sign to make that negative. 2868 */ 2869 st->vrefs_uv[AD4170_AVSS_SUP] = ret == -ENODEV ? 0 : -ret; 2870 2871 ret = devm_regulator_get_enable_read_voltage(dev, "refin1p"); 2872 if (ret < 0 && ret != -ENODEV) 2873 return dev_err_probe(dev, ret, "Failed to get REFIN+ voltage.\n"); 2874 2875 st->vrefs_uv[AD4170_REFIN1P_SUP] = ret; 2876 2877 ret = devm_regulator_get_enable_read_voltage(dev, "refin1n"); 2878 if (ret < 0 && ret != -ENODEV) 2879 return dev_err_probe(dev, ret, "Failed to get REFIN- voltage.\n"); 2880 2881 /* 2882 * Negative supplies are assumed to provide negative voltage. 2883 * REVISIT when support for negative regulator voltage read be available 2884 * in the regulator framework. 2885 */ 2886 st->vrefs_uv[AD4170_REFIN1N_SUP] = ret == -ENODEV ? -ENODEV : -ret; 2887 2888 ret = devm_regulator_get_enable_read_voltage(dev, "refin2p"); 2889 if (ret < 0 && ret != -ENODEV) 2890 return dev_err_probe(dev, ret, "Failed to get REFIN2+ voltage.\n"); 2891 2892 st->vrefs_uv[AD4170_REFIN2P_SUP] = ret; 2893 2894 ret = devm_regulator_get_enable_read_voltage(dev, "refin2n"); 2895 if (ret < 0 && ret != -ENODEV) 2896 return dev_err_probe(dev, ret, "Failed to get REFIN2- voltage.\n"); 2897 2898 /* 2899 * Negative supplies are assumed to provide negative voltage. 2900 * REVISIT when support for negative regulator voltage read be available 2901 * in the regulator framework. 2902 */ 2903 st->vrefs_uv[AD4170_REFIN2N_SUP] = ret == -ENODEV ? -ENODEV : -ret; 2904 2905 return 0; 2906 } 2907 2908 static int ad4170_probe(struct spi_device *spi) 2909 { 2910 const struct ad4170_chip_info *chip; 2911 struct device *dev = &spi->dev; 2912 struct iio_dev *indio_dev; 2913 struct ad4170_state *st; 2914 int ret; 2915 2916 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 2917 if (!indio_dev) 2918 return -ENOMEM; 2919 2920 st = iio_priv(indio_dev); 2921 st->spi = spi; 2922 2923 ret = devm_mutex_init(dev, &st->lock); 2924 if (ret) 2925 return ret; 2926 2927 chip = spi_get_device_match_data(spi); 2928 if (!chip) 2929 return -EINVAL; 2930 2931 indio_dev->name = chip->name; 2932 indio_dev->info = &ad4170_info; 2933 2934 st->regmap = devm_regmap_init(dev, NULL, st, &ad4170_regmap_config); 2935 if (IS_ERR(st->regmap)) 2936 return dev_err_probe(dev, PTR_ERR(st->regmap), 2937 "Failed to initialize regmap\n"); 2938 2939 ret = ad4170_regulator_setup(st); 2940 if (ret) 2941 return ret; 2942 2943 ret = ad4170_soft_reset(st); 2944 if (ret) 2945 return ret; 2946 2947 ret = ad4170_parse_firmware(indio_dev); 2948 if (ret) 2949 return dev_err_probe(dev, ret, "Failed to parse firmware\n"); 2950 2951 ret = ad4170_initial_config(indio_dev); 2952 if (ret) 2953 return dev_err_probe(dev, ret, "Failed to setup device\n"); 2954 2955 init_completion(&st->completion); 2956 2957 if (spi->irq) { 2958 ret = devm_request_irq(dev, spi->irq, &ad4170_irq_handler, 2959 IRQF_NO_THREAD, indio_dev->name, indio_dev); 2960 if (ret) 2961 return ret; 2962 2963 ret = ad4170_trigger_setup(indio_dev); 2964 if (ret) 2965 return ret; 2966 } 2967 2968 ret = ad4170_prepare_spi_message(st); 2969 if (ret) 2970 return dev_err_probe(dev, ret, "Failed to prepare SPI message\n"); 2971 2972 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 2973 &ad4170_trigger_handler, 2974 &ad4170_buffer_ops); 2975 if (ret) 2976 return dev_err_probe(dev, ret, "Failed to setup read buffer\n"); 2977 2978 return devm_iio_device_register(dev, indio_dev); 2979 } 2980 2981 static const struct spi_device_id ad4170_id_table[] = { 2982 { "ad4170-4", (kernel_ulong_t)&ad4170_chip_info }, 2983 { "ad4190-4", (kernel_ulong_t)&ad4190_chip_info }, 2984 { "ad4195-4", (kernel_ulong_t)&ad4195_chip_info }, 2985 { } 2986 }; 2987 MODULE_DEVICE_TABLE(spi, ad4170_id_table); 2988 2989 static const struct of_device_id ad4170_of_match[] = { 2990 { .compatible = "adi,ad4170-4", .data = &ad4170_chip_info }, 2991 { .compatible = "adi,ad4190-4", .data = &ad4190_chip_info }, 2992 { .compatible = "adi,ad4195-4", .data = &ad4195_chip_info }, 2993 { } 2994 }; 2995 MODULE_DEVICE_TABLE(of, ad4170_of_match); 2996 2997 static struct spi_driver ad4170_driver = { 2998 .driver = { 2999 .name = "ad4170-4", 3000 .of_match_table = ad4170_of_match, 3001 }, 3002 .probe = ad4170_probe, 3003 .id_table = ad4170_id_table, 3004 }; 3005 module_spi_driver(ad4170_driver); 3006 3007 MODULE_AUTHOR("Ana-Maria Cusco <ana-maria.cusco@analog.com>"); 3008 MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>"); 3009 MODULE_DESCRIPTION("Analog Devices AD4170 SPI driver"); 3010 MODULE_LICENSE("GPL"); 3011