1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD4080 SPI ADC driver 4 * 5 * Copyright 2025 Analog Devices Inc. 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/iio/backend.h> 15 #include <linux/iio/iio.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/spi/spi.h> 23 #include <linux/types.h> 24 #include <linux/unaligned.h> 25 #include <linux/units.h> 26 27 /* Register Definition */ 28 #define AD4080_REG_INTERFACE_CONFIG_A 0x00 29 #define AD4080_REG_INTERFACE_CONFIG_B 0x01 30 #define AD4080_REG_DEVICE_CONFIG 0x02 31 #define AD4080_REG_CHIP_TYPE 0x03 32 #define AD4080_REG_PRODUCT_ID_L 0x04 33 #define AD4080_REG_PRODUCT_ID_H 0x05 34 #define AD4080_REG_CHIP_GRADE 0x06 35 #define AD4080_REG_SCRATCH_PAD 0x0A 36 #define AD4080_REG_SPI_REVISION 0x0B 37 #define AD4080_REG_VENDOR_L 0x0C 38 #define AD4080_REG_VENDOR_H 0x0D 39 #define AD4080_REG_STREAM_MODE 0x0E 40 #define AD4080_REG_TRANSFER_CONFIG 0x0F 41 #define AD4080_REG_INTERFACE_CONFIG_C 0x10 42 #define AD4080_REG_INTERFACE_STATUS_A 0x11 43 #define AD4080_REG_DEVICE_STATUS 0x14 44 #define AD4080_REG_ADC_DATA_INTF_CONFIG_A 0x15 45 #define AD4080_REG_ADC_DATA_INTF_CONFIG_B 0x16 46 #define AD4080_REG_ADC_DATA_INTF_CONFIG_C 0x17 47 #define AD4080_REG_PWR_CTRL 0x18 48 #define AD4080_REG_GPIO_CONFIG_A 0x19 49 #define AD4080_REG_GPIO_CONFIG_B 0x1A 50 #define AD4080_REG_GPIO_CONFIG_C 0x1B 51 #define AD4080_REG_GENERAL_CONFIG 0x1C 52 #define AD4080_REG_FIFO_WATERMARK_LSB 0x1D 53 #define AD4080_REG_FIFO_WATERMARK_MSB 0x1E 54 #define AD4080_REG_EVENT_HYSTERESIS_LSB 0x1F 55 #define AD4080_REG_EVENT_HYSTERESIS_MSB 0x20 56 #define AD4080_REG_EVENT_DETECTION_HI_LSB 0x21 57 #define AD4080_REG_EVENT_DETECTION_HI_MSB 0x22 58 #define AD4080_REG_EVENT_DETECTION_LO_LSB 0x23 59 #define AD4080_REG_EVENT_DETECTION_LO_MSB 0x24 60 #define AD4080_REG_OFFSET_LSB 0x25 61 #define AD4080_REG_OFFSET_MSB 0x26 62 #define AD4080_REG_GAIN_LSB 0x27 63 #define AD4080_REG_GAIN_MSB 0x28 64 #define AD4080_REG_FILTER_CONFIG 0x29 65 66 /* AD4080_REG_INTERFACE_CONFIG_A Bit Definition */ 67 #define AD4080_INTERFACE_CONFIG_A_SW_RESET (BIT(7) | BIT(0)) 68 #define AD4080_INTERFACE_CONFIG_A_ADDR_ASC BIT(5) 69 #define AD4080_INTERFACE_CONFIG_A_SDO_ENABLE BIT(4) 70 71 /* AD4080_REG_INTERFACE_CONFIG_B Bit Definition */ 72 #define AD4080_INTERFACE_CONFIG_B_SINGLE_INST BIT(7) 73 #define AD4080_INTERFACE_CONFIG_B_SHORT_INST BIT(3) 74 75 /* AD4080_REG_DEVICE_CONFIG Bit Definition */ 76 #define AD4080_DEVICE_CONFIG_OPERATING_MODES_MSK GENMASK(1, 0) 77 78 /* AD4080_REG_TRANSFER_CONFIG Bit Definition */ 79 #define AD4080_TRANSFER_CONFIG_KEEP_STREAM_LENGTH_VAL BIT(2) 80 81 /* AD4080_REG_INTERFACE_CONFIG_C Bit Definition */ 82 #define AD4080_INTERFACE_CONFIG_C_STRICT_REG_ACCESS BIT(5) 83 84 /* AD4080_REG_ADC_DATA_INTF_CONFIG_A Bit Definition */ 85 #define AD4080_ADC_DATA_INTF_CONFIG_A_RESERVED_CONFIG_A BIT(6) 86 #define AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN BIT(4) 87 #define AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES BIT(2) 88 #define AD4080_ADC_DATA_INTF_CONFIG_A_DATA_INTF_MODE BIT(0) 89 90 /* AD4080_REG_ADC_DATA_INTF_CONFIG_B Bit Definition */ 91 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK GENMASK(7, 4) 92 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_SELF_CLK_MODE BIT(3) 93 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN BIT(0) 94 95 /* AD4080_REG_ADC_DATA_INTF_CONFIG_C Bit Definition */ 96 #define AD4080_ADC_DATA_INTF_CONFIG_C_LVDS_VOD_MSK GENMASK(6, 4) 97 98 /* AD4080_REG_PWR_CTRL Bit Definition */ 99 #define AD4080_PWR_CTRL_ANA_DIG_LDO_PD BIT(1) 100 #define AD4080_PWR_CTRL_INTF_LDO_PD BIT(0) 101 102 /* AD4080_REG_GPIO_CONFIG_A Bit Definition */ 103 #define AD4080_GPIO_CONFIG_A_GPO_1_EN BIT(1) 104 #define AD4080_GPIO_CONFIG_A_GPO_0_EN BIT(0) 105 106 /* AD4080_REG_GPIO_CONFIG_B Bit Definition */ 107 #define AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK GENMASK(7, 4) 108 #define AD4080_GPIO_CONFIG_B_GPIO_0_SEL_MSK GENMASK(3, 0) 109 #define AD4080_GPIO_CONFIG_B_GPIO_SPI_SDO 0 110 #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_FULL 1 111 #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_READ_DONE 2 112 #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY 3 113 #define AD4080_GPIO_CONFIG_B_GPIO_H_THRESH 4 114 #define AD4080_GPIO_CONFIG_B_GPIO_L_THRESH 5 115 #define AD4080_GPIO_CONFIG_B_GPIO_STATUS_ALERT 6 116 #define AD4080_GPIO_CONFIG_B_GPIO_GPIO_DATA 7 117 #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_SYNC 8 118 #define AD4080_GPIO_CONFIG_B_GPIO_EXTERNAL_EVENT 9 119 120 /* AD4080_REG_FIFO_CONFIG Bit Definition */ 121 #define AD4080_FIFO_CONFIG_FIFO_MODE_MSK GENMASK(1, 0) 122 123 /* AD4080_REG_FILTER_CONFIG Bit Definition */ 124 #define AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK GENMASK(6, 3) 125 #define AD4080_FILTER_CONFIG_FILTER_SEL_MSK GENMASK(1, 0) 126 127 /* Miscellaneous Definitions */ 128 #define AD4080_SPI_READ BIT(7) 129 #define AD4080_CHIP_ID 0x0050 130 #define AD4081_CHIP_ID 0x0051 131 #define AD4082_CHIP_ID 0x0052 132 #define AD4083_CHIP_ID 0x0053 133 #define AD4084_CHIP_ID 0x0054 134 #define AD4085_CHIP_ID 0x0055 135 #define AD4086_CHIP_ID 0x0056 136 #define AD4087_CHIP_ID 0x0057 137 #define AD4088_CHIP_ID 0x0058 138 #define AD4880_CHIP_ID 0x0059 139 #define AD4884_CHIP_ID 0x005C 140 141 #define AD4080_MAX_CHANNELS 2 142 143 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 144 145 #define AD4080_MAX_SAMP_FREQ 40000000 146 #define AD4080_MIN_SAMP_FREQ 1250000 147 148 enum ad4080_filter_type { 149 FILTER_NONE, 150 SINC_1, 151 SINC_5, 152 SINC_5_COMP 153 }; 154 155 static const unsigned int ad4080_scale_table[][2] = { 156 { 6000, 0 }, 157 }; 158 159 static const char *const ad4080_filter_type_iio_enum[] = { 160 [FILTER_NONE] = "none", 161 [SINC_1] = "sinc1", 162 [SINC_5] = "sinc5", 163 [SINC_5_COMP] = "sinc5+pf1", 164 }; 165 166 static const int ad4080_dec_rate_avail[] = { 167 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 168 }; 169 170 static const int ad4080_dec_rate_none[] = { 1 }; 171 172 static const char * const ad4080_power_supplies[] = { 173 "vdd33", "vdd11", "vddldo", "iovdd", "vrefin", 174 }; 175 176 struct ad4080_chip_info { 177 const char *name; 178 unsigned int product_id; 179 int num_scales; 180 const unsigned int (*scale_table)[2]; 181 const struct iio_chan_spec *channels; 182 unsigned int num_channels; 183 unsigned int lvds_cnv_clk_cnt_max; 184 }; 185 186 struct ad4080_state { 187 struct spi_device *spi[AD4080_MAX_CHANNELS]; 188 struct regmap *regmap[AD4080_MAX_CHANNELS]; 189 struct iio_backend *back[AD4080_MAX_CHANNELS]; 190 const struct ad4080_chip_info *info; 191 /* 192 * Synchronize access to members the of driver state, and ensure 193 * atomicity of consecutive regmap operations. 194 */ 195 struct mutex lock; 196 unsigned int num_lanes; 197 unsigned long clk_rate; 198 enum ad4080_filter_type filter_type[AD4080_MAX_CHANNELS]; 199 bool lvds_cnv_en; 200 }; 201 202 static const struct regmap_config ad4080_regmap_config = { 203 .reg_bits = 16, 204 .val_bits = 8, 205 .read_flag_mask = BIT(7), 206 .max_register = 0x29, 207 }; 208 209 static int ad4080_reg_access(struct iio_dev *indio_dev, unsigned int reg, 210 unsigned int writeval, unsigned int *readval) 211 { 212 struct ad4080_state *st = iio_priv(indio_dev); 213 214 if (readval) 215 return regmap_read(st->regmap[0], reg, readval); 216 217 return regmap_write(st->regmap[0], reg, writeval); 218 } 219 220 static int ad4080_get_scale(struct ad4080_state *st, int *val, int *val2) 221 { 222 unsigned int tmp; 223 224 tmp = (st->info->scale_table[0][0] * 1000000ULL) >> 225 st->info->channels[0].scan_type.realbits; 226 *val = tmp / 1000000; 227 *val2 = tmp % 1000000; 228 229 return IIO_VAL_INT_PLUS_NANO; 230 } 231 232 static unsigned int ad4080_get_dec_rate(struct iio_dev *dev, 233 const struct iio_chan_spec *chan) 234 { 235 struct ad4080_state *st = iio_priv(dev); 236 int ret; 237 unsigned int data; 238 unsigned int ch = chan->channel; 239 240 ret = regmap_read(st->regmap[ch], AD4080_REG_FILTER_CONFIG, &data); 241 if (ret) 242 return ret; 243 244 return 1 << (FIELD_GET(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, data) + 1); 245 } 246 247 static int ad4080_set_dec_rate(struct iio_dev *dev, 248 const struct iio_chan_spec *chan, 249 unsigned int mode) 250 { 251 struct ad4080_state *st = iio_priv(dev); 252 unsigned int ch = chan->channel; 253 254 guard(mutex)(&st->lock); 255 256 if ((st->filter_type[ch] >= SINC_5 && mode >= 512) || mode < 2) 257 return -EINVAL; 258 259 return regmap_update_bits(st->regmap[ch], AD4080_REG_FILTER_CONFIG, 260 AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, 261 FIELD_PREP(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, 262 (ilog2(mode) - 1))); 263 } 264 265 static int ad4080_read_raw(struct iio_dev *indio_dev, 266 struct iio_chan_spec const *chan, 267 int *val, int *val2, long m) 268 { 269 struct ad4080_state *st = iio_priv(indio_dev); 270 int dec_rate; 271 272 switch (m) { 273 case IIO_CHAN_INFO_SCALE: 274 return ad4080_get_scale(st, val, val2); 275 case IIO_CHAN_INFO_SAMP_FREQ: 276 dec_rate = ad4080_get_dec_rate(indio_dev, chan); 277 if (dec_rate < 0) 278 return dec_rate; 279 if (st->filter_type[chan->channel] == SINC_5_COMP) 280 dec_rate *= 2; 281 if (st->filter_type[chan->channel]) 282 *val = DIV_ROUND_CLOSEST(st->clk_rate, dec_rate); 283 else 284 *val = st->clk_rate; 285 return IIO_VAL_INT; 286 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 287 if (st->filter_type[chan->channel] == FILTER_NONE) { 288 *val = 1; 289 } else { 290 *val = ad4080_get_dec_rate(indio_dev, chan); 291 if (*val < 0) 292 return *val; 293 } 294 return IIO_VAL_INT; 295 default: 296 return -EINVAL; 297 } 298 } 299 300 static int ad4080_write_raw(struct iio_dev *indio_dev, 301 struct iio_chan_spec const *chan, 302 int val, int val2, long mask) 303 { 304 struct ad4080_state *st = iio_priv(indio_dev); 305 306 switch (mask) { 307 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 308 if (st->filter_type[chan->channel] == FILTER_NONE && val > 1) 309 return -EINVAL; 310 311 return ad4080_set_dec_rate(indio_dev, chan, val); 312 default: 313 return -EINVAL; 314 } 315 } 316 317 static int ad4080_lvds_sync_write(struct ad4080_state *st, unsigned int ch) 318 { 319 struct device *dev = regmap_get_device(st->regmap[ch]); 320 int ret; 321 322 ret = regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A, 323 AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); 324 if (ret) 325 return ret; 326 327 ret = iio_backend_interface_data_align(st->back[ch], 10000); 328 if (ret) 329 return dev_err_probe(dev, ret, 330 "Data alignment process failed\n"); 331 332 dev_dbg(dev, "Success: Pattern correct and Locked!\n"); 333 return regmap_clear_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A, 334 AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); 335 } 336 337 static int ad4080_get_filter_type(struct iio_dev *dev, 338 const struct iio_chan_spec *chan) 339 { 340 struct ad4080_state *st = iio_priv(dev); 341 unsigned int data; 342 unsigned int ch = chan->channel; 343 int ret; 344 345 ret = regmap_read(st->regmap[ch], AD4080_REG_FILTER_CONFIG, &data); 346 if (ret) 347 return ret; 348 349 return FIELD_GET(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, data); 350 } 351 352 static int ad4080_set_filter_type(struct iio_dev *dev, 353 const struct iio_chan_spec *chan, 354 unsigned int mode) 355 { 356 struct ad4080_state *st = iio_priv(dev); 357 unsigned int ch = chan->channel; 358 int dec_rate; 359 int ret; 360 361 guard(mutex)(&st->lock); 362 363 dec_rate = ad4080_get_dec_rate(dev, chan); 364 if (dec_rate < 0) 365 return dec_rate; 366 367 if (mode >= SINC_5 && dec_rate >= 512) 368 return -EINVAL; 369 370 ret = iio_backend_filter_type_set(st->back[ch], mode); 371 if (ret) 372 return ret; 373 374 ret = regmap_update_bits(st->regmap[ch], AD4080_REG_FILTER_CONFIG, 375 AD4080_FILTER_CONFIG_FILTER_SEL_MSK, 376 FIELD_PREP(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, 377 mode)); 378 if (ret) 379 return ret; 380 381 st->filter_type[ch] = mode; 382 383 return 0; 384 } 385 386 static int ad4080_read_avail(struct iio_dev *indio_dev, 387 struct iio_chan_spec const *chan, 388 const int **vals, int *type, int *length, 389 long mask) 390 { 391 struct ad4080_state *st = iio_priv(indio_dev); 392 393 switch (mask) { 394 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 395 switch (st->filter_type[chan->channel]) { 396 case FILTER_NONE: 397 *vals = ad4080_dec_rate_none; 398 *length = ARRAY_SIZE(ad4080_dec_rate_none); 399 break; 400 default: 401 *vals = ad4080_dec_rate_avail; 402 *length = st->filter_type[chan->channel] >= SINC_5 ? 403 (ARRAY_SIZE(ad4080_dec_rate_avail) - 2) : 404 ARRAY_SIZE(ad4080_dec_rate_avail); 405 break; 406 } 407 *type = IIO_VAL_INT; 408 return IIO_AVAIL_LIST; 409 default: 410 return -EINVAL; 411 } 412 } 413 414 static int ad4880_update_scan_mode(struct iio_dev *indio_dev, 415 const unsigned long *scan_mask) 416 { 417 struct ad4080_state *st = iio_priv(indio_dev); 418 int ret; 419 420 for (unsigned int ch = 0; ch < st->info->num_channels; ch++) { 421 /* 422 * Each backend has a single channel (channel 0 from the 423 * backend's perspective), so always use channel index 0. 424 */ 425 if (test_bit(ch, scan_mask)) 426 ret = iio_backend_chan_enable(st->back[ch], 0); 427 else 428 ret = iio_backend_chan_disable(st->back[ch], 0); 429 if (ret) 430 return ret; 431 } 432 433 return 0; 434 } 435 436 static const struct iio_info ad4080_iio_info = { 437 .debugfs_reg_access = ad4080_reg_access, 438 .read_raw = ad4080_read_raw, 439 .write_raw = ad4080_write_raw, 440 .read_avail = ad4080_read_avail, 441 }; 442 443 /* 444 * AD4880 needs update_scan_mode to enable/disable individual backend channels. 445 * Single-channel devices don't need this as their backends may not implement 446 * chan_enable/chan_disable operations. 447 */ 448 static const struct iio_info ad4880_iio_info = { 449 .debugfs_reg_access = ad4080_reg_access, 450 .read_raw = ad4080_read_raw, 451 .write_raw = ad4080_write_raw, 452 .read_avail = ad4080_read_avail, 453 .update_scan_mode = ad4880_update_scan_mode, 454 }; 455 456 static const struct iio_enum ad4080_filter_type_enum = { 457 .items = ad4080_filter_type_iio_enum, 458 .num_items = ARRAY_SIZE(ad4080_filter_type_iio_enum), 459 .set = ad4080_set_filter_type, 460 .get = ad4080_get_filter_type, 461 }; 462 463 static struct iio_chan_spec_ext_info ad4080_ext_info[] = { 464 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad4080_filter_type_enum), 465 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, 466 &ad4080_filter_type_enum), 467 { } 468 }; 469 470 /* 471 * AD4880 needs per-channel filter configuration since each channel has 472 * its own independent ADC with separate SPI interface. 473 */ 474 static struct iio_chan_spec_ext_info ad4880_ext_info[] = { 475 IIO_ENUM("filter_type", IIO_SEPARATE, &ad4080_filter_type_enum), 476 IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, 477 &ad4080_filter_type_enum), 478 { } 479 }; 480 481 #define AD4080_CHANNEL_DEFINE(bits, storage, idx) { \ 482 .type = IIO_VOLTAGE, \ 483 .indexed = 1, \ 484 .channel = (idx), \ 485 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), \ 486 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 487 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 488 .info_mask_shared_by_all_available = \ 489 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 490 .ext_info = ad4080_ext_info, \ 491 .scan_index = (idx), \ 492 .scan_type = { \ 493 .sign = 's', \ 494 .realbits = (bits), \ 495 .storagebits = (storage), \ 496 }, \ 497 } 498 499 /* 500 * AD4880 has per-channel attributes (filter_type, oversampling_ratio, 501 * sampling_frequency) since each channel has its own independent ADC 502 * with separate SPI configuration interface. 503 */ 504 #define AD4880_CHANNEL_DEFINE(bits, storage, idx) { \ 505 .type = IIO_VOLTAGE, \ 506 .indexed = 1, \ 507 .channel = (idx), \ 508 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) | \ 509 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 510 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 511 .info_mask_separate_available = \ 512 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 513 .ext_info = ad4880_ext_info, \ 514 .scan_index = (idx), \ 515 .scan_type = { \ 516 .sign = 's', \ 517 .realbits = (bits), \ 518 .storagebits = (storage), \ 519 }, \ 520 } 521 522 static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32, 0); 523 524 static const struct iio_chan_spec ad4081_channel = AD4080_CHANNEL_DEFINE(20, 32, 0); 525 526 static const struct iio_chan_spec ad4082_channel = AD4080_CHANNEL_DEFINE(20, 32, 0); 527 528 static const struct iio_chan_spec ad4083_channel = AD4080_CHANNEL_DEFINE(16, 16, 0); 529 530 static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16, 0); 531 532 static const struct iio_chan_spec ad4085_channel = AD4080_CHANNEL_DEFINE(16, 16, 0); 533 534 static const struct iio_chan_spec ad4086_channel = AD4080_CHANNEL_DEFINE(14, 16, 0); 535 536 static const struct iio_chan_spec ad4087_channel = AD4080_CHANNEL_DEFINE(14, 16, 0); 537 538 static const struct iio_chan_spec ad4088_channel = AD4080_CHANNEL_DEFINE(14, 16, 0); 539 540 static const struct iio_chan_spec ad4880_channels[] = { 541 AD4880_CHANNEL_DEFINE(20, 32, 0), 542 AD4880_CHANNEL_DEFINE(20, 32, 1), 543 }; 544 545 static const struct iio_chan_spec ad4884_channels[] = { 546 AD4880_CHANNEL_DEFINE(16, 16, 0), 547 AD4880_CHANNEL_DEFINE(16, 16, 1), 548 }; 549 550 static const struct ad4080_chip_info ad4080_chip_info = { 551 .name = "ad4080", 552 .product_id = AD4080_CHIP_ID, 553 .scale_table = ad4080_scale_table, 554 .num_scales = ARRAY_SIZE(ad4080_scale_table), 555 .num_channels = 1, 556 .channels = &ad4080_channel, 557 .lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX, 558 }; 559 560 static const struct ad4080_chip_info ad4081_chip_info = { 561 .name = "ad4081", 562 .product_id = AD4081_CHIP_ID, 563 .scale_table = ad4080_scale_table, 564 .num_scales = ARRAY_SIZE(ad4080_scale_table), 565 .num_channels = 1, 566 .channels = &ad4081_channel, 567 .lvds_cnv_clk_cnt_max = 2, 568 }; 569 570 static const struct ad4080_chip_info ad4082_chip_info = { 571 .name = "ad4082", 572 .product_id = AD4082_CHIP_ID, 573 .scale_table = ad4080_scale_table, 574 .num_scales = ARRAY_SIZE(ad4080_scale_table), 575 .num_channels = 1, 576 .channels = &ad4082_channel, 577 .lvds_cnv_clk_cnt_max = 8, 578 }; 579 580 static const struct ad4080_chip_info ad4083_chip_info = { 581 .name = "ad4083", 582 .product_id = AD4083_CHIP_ID, 583 .scale_table = ad4080_scale_table, 584 .num_scales = ARRAY_SIZE(ad4080_scale_table), 585 .num_channels = 1, 586 .channels = &ad4083_channel, 587 .lvds_cnv_clk_cnt_max = 5, 588 }; 589 590 static const struct ad4080_chip_info ad4084_chip_info = { 591 .name = "ad4084", 592 .product_id = AD4084_CHIP_ID, 593 .scale_table = ad4080_scale_table, 594 .num_scales = ARRAY_SIZE(ad4080_scale_table), 595 .num_channels = 1, 596 .channels = &ad4084_channel, 597 .lvds_cnv_clk_cnt_max = 2, 598 }; 599 600 static const struct ad4080_chip_info ad4085_chip_info = { 601 .name = "ad4085", 602 .product_id = AD4085_CHIP_ID, 603 .scale_table = ad4080_scale_table, 604 .num_scales = ARRAY_SIZE(ad4080_scale_table), 605 .num_channels = 1, 606 .channels = &ad4085_channel, 607 .lvds_cnv_clk_cnt_max = 8, 608 }; 609 610 static const struct ad4080_chip_info ad4086_chip_info = { 611 .name = "ad4086", 612 .product_id = AD4086_CHIP_ID, 613 .scale_table = ad4080_scale_table, 614 .num_scales = ARRAY_SIZE(ad4080_scale_table), 615 .num_channels = 1, 616 .channels = &ad4086_channel, 617 .lvds_cnv_clk_cnt_max = 4, 618 }; 619 620 static const struct ad4080_chip_info ad4087_chip_info = { 621 .name = "ad4087", 622 .product_id = AD4087_CHIP_ID, 623 .scale_table = ad4080_scale_table, 624 .num_scales = ARRAY_SIZE(ad4080_scale_table), 625 .num_channels = 1, 626 .channels = &ad4087_channel, 627 .lvds_cnv_clk_cnt_max = 1, 628 }; 629 630 static const struct ad4080_chip_info ad4088_chip_info = { 631 .name = "ad4088", 632 .product_id = AD4088_CHIP_ID, 633 .scale_table = ad4080_scale_table, 634 .num_scales = ARRAY_SIZE(ad4080_scale_table), 635 .num_channels = 1, 636 .channels = &ad4088_channel, 637 .lvds_cnv_clk_cnt_max = 8, 638 }; 639 640 static const struct ad4080_chip_info ad4880_chip_info = { 641 .name = "ad4880", 642 .product_id = AD4880_CHIP_ID, 643 .scale_table = ad4080_scale_table, 644 .num_scales = ARRAY_SIZE(ad4080_scale_table), 645 .num_channels = 2, 646 .channels = ad4880_channels, 647 .lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX, 648 }; 649 650 static const struct ad4080_chip_info ad4884_chip_info = { 651 .name = "ad4884", 652 .product_id = AD4884_CHIP_ID, 653 .scale_table = ad4080_scale_table, 654 .num_scales = ARRAY_SIZE(ad4080_scale_table), 655 .num_channels = 2, 656 .channels = ad4884_channels, 657 .lvds_cnv_clk_cnt_max = 2, 658 }; 659 660 static int ad4080_setup_channel(struct ad4080_state *st, unsigned int ch) 661 { 662 struct device *dev = regmap_get_device(st->regmap[ch]); 663 __le16 id_le; 664 u16 id; 665 int ret; 666 667 ret = regmap_write(st->regmap[ch], AD4080_REG_INTERFACE_CONFIG_A, 668 AD4080_INTERFACE_CONFIG_A_SW_RESET); 669 if (ret) 670 return ret; 671 672 ret = regmap_write(st->regmap[ch], AD4080_REG_INTERFACE_CONFIG_A, 673 AD4080_INTERFACE_CONFIG_A_SDO_ENABLE); 674 if (ret) 675 return ret; 676 677 ret = regmap_bulk_read(st->regmap[ch], AD4080_REG_PRODUCT_ID_L, &id_le, 678 sizeof(id_le)); 679 if (ret) 680 return ret; 681 682 id = le16_to_cpu(id_le); 683 if (id != st->info->product_id) 684 dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); 685 686 ret = regmap_set_bits(st->regmap[ch], AD4080_REG_GPIO_CONFIG_A, 687 AD4080_GPIO_CONFIG_A_GPO_1_EN); 688 if (ret) 689 return ret; 690 691 ret = regmap_write(st->regmap[ch], AD4080_REG_GPIO_CONFIG_B, 692 FIELD_PREP(AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK, 693 AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY)); 694 if (ret) 695 return ret; 696 697 ret = iio_backend_num_lanes_set(st->back[ch], st->num_lanes); 698 if (ret) 699 return ret; 700 701 if (!st->lvds_cnv_en) 702 return 0; 703 704 /* Set maximum LVDS Data Transfer Latency */ 705 ret = regmap_update_bits(st->regmap[ch], 706 AD4080_REG_ADC_DATA_INTF_CONFIG_B, 707 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, 708 FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, 709 st->info->lvds_cnv_clk_cnt_max)); 710 if (ret) 711 return ret; 712 713 if (st->num_lanes > 1) { 714 ret = regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A, 715 AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES); 716 if (ret) 717 return ret; 718 } 719 720 ret = regmap_set_bits(st->regmap[ch], 721 AD4080_REG_ADC_DATA_INTF_CONFIG_B, 722 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN); 723 if (ret) 724 return ret; 725 726 return ad4080_lvds_sync_write(st, ch); 727 } 728 729 static int ad4080_setup(struct iio_dev *indio_dev) 730 { 731 struct ad4080_state *st = iio_priv(indio_dev); 732 int ret; 733 734 for (unsigned int ch = 0; ch < st->info->num_channels; ch++) { 735 ret = ad4080_setup_channel(st, ch); 736 if (ret) 737 return ret; 738 } 739 740 return 0; 741 } 742 743 static int ad4080_properties_parse(struct ad4080_state *st, 744 struct device *dev) 745 { 746 747 st->lvds_cnv_en = device_property_read_bool(dev, "adi,lvds-cnv-enable"); 748 749 st->num_lanes = 1; 750 device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes); 751 if (!st->num_lanes || st->num_lanes > 2) 752 return dev_err_probe(dev, -EINVAL, 753 "Invalid 'adi,num-lanes' value: %u", 754 st->num_lanes); 755 756 return 0; 757 } 758 759 static int ad4080_probe(struct spi_device *spi) 760 { 761 struct iio_dev *indio_dev; 762 struct device *dev = &spi->dev; 763 struct ad4080_state *st; 764 struct clk *clk; 765 int ret; 766 767 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 768 if (!indio_dev) 769 return -ENOMEM; 770 771 st = iio_priv(indio_dev); 772 773 ret = devm_regulator_bulk_get_enable(dev, 774 ARRAY_SIZE(ad4080_power_supplies), 775 ad4080_power_supplies); 776 if (ret) 777 return dev_err_probe(dev, ret, 778 "failed to get and enable supplies\n"); 779 780 /* Setup primary SPI device (channel 0) */ 781 st->spi[0] = spi; 782 st->regmap[0] = devm_regmap_init_spi(spi, &ad4080_regmap_config); 783 if (IS_ERR(st->regmap[0])) 784 return PTR_ERR(st->regmap[0]); 785 786 st->info = spi_get_device_match_data(spi); 787 if (!st->info) 788 return -ENODEV; 789 790 /* Setup ancillary SPI devices for additional channels */ 791 for (unsigned int ch = 1; ch < st->info->num_channels; ch++) { 792 st->spi[ch] = devm_spi_new_ancillary_device(spi, spi_get_chipselect(spi, ch)); 793 if (IS_ERR(st->spi[ch])) 794 return dev_err_probe(dev, PTR_ERR(st->spi[ch]), 795 "failed to register ancillary device\n"); 796 797 st->regmap[ch] = devm_regmap_init_spi(st->spi[ch], &ad4080_regmap_config); 798 if (IS_ERR(st->regmap[ch])) 799 return PTR_ERR(st->regmap[ch]); 800 } 801 802 ret = devm_mutex_init(dev, &st->lock); 803 if (ret) 804 return ret; 805 806 indio_dev->name = st->info->name; 807 indio_dev->channels = st->info->channels; 808 indio_dev->num_channels = st->info->num_channels; 809 indio_dev->info = st->info->num_channels > 1 ? 810 &ad4880_iio_info : &ad4080_iio_info; 811 812 ret = ad4080_properties_parse(st, dev); 813 if (ret) 814 return ret; 815 816 clk = devm_clk_get_enabled(&spi->dev, "cnv"); 817 if (IS_ERR(clk)) 818 return PTR_ERR(clk); 819 820 st->clk_rate = clk_get_rate(clk); 821 822 /* Get backends for all channels */ 823 for (unsigned int ch = 0; ch < st->info->num_channels; ch++) { 824 st->back[ch] = devm_iio_backend_get_by_index(dev, ch); 825 if (IS_ERR(st->back[ch])) 826 return PTR_ERR(st->back[ch]); 827 828 ret = devm_iio_backend_enable(dev, st->back[ch]); 829 if (ret) 830 return ret; 831 } 832 833 /* 834 * Request buffer from the first backend only. For multi-channel 835 * devices (e.g., AD4880), the FPGA uses two axi_ad408x IP instances 836 * (one per ADC channel) whose outputs are combined by a packer block 837 * that interleaves all channel data into a single DMA stream routed 838 * through the first backend's clock domain. 839 */ 840 ret = devm_iio_backend_request_buffer(dev, st->back[0], indio_dev); 841 if (ret) 842 return ret; 843 844 ret = ad4080_setup(indio_dev); 845 if (ret) 846 return ret; 847 848 return devm_iio_device_register(&spi->dev, indio_dev); 849 } 850 851 static const struct spi_device_id ad4080_id[] = { 852 { "ad4080", (kernel_ulong_t)&ad4080_chip_info }, 853 { "ad4081", (kernel_ulong_t)&ad4081_chip_info }, 854 { "ad4082", (kernel_ulong_t)&ad4082_chip_info }, 855 { "ad4083", (kernel_ulong_t)&ad4083_chip_info }, 856 { "ad4084", (kernel_ulong_t)&ad4084_chip_info }, 857 { "ad4085", (kernel_ulong_t)&ad4085_chip_info }, 858 { "ad4086", (kernel_ulong_t)&ad4086_chip_info }, 859 { "ad4087", (kernel_ulong_t)&ad4087_chip_info }, 860 { "ad4088", (kernel_ulong_t)&ad4088_chip_info }, 861 { "ad4880", (kernel_ulong_t)&ad4880_chip_info }, 862 { "ad4884", (kernel_ulong_t)&ad4884_chip_info }, 863 { } 864 }; 865 MODULE_DEVICE_TABLE(spi, ad4080_id); 866 867 static const struct of_device_id ad4080_of_match[] = { 868 { .compatible = "adi,ad4080", &ad4080_chip_info }, 869 { .compatible = "adi,ad4081", &ad4081_chip_info }, 870 { .compatible = "adi,ad4082", &ad4082_chip_info }, 871 { .compatible = "adi,ad4083", &ad4083_chip_info }, 872 { .compatible = "adi,ad4084", &ad4084_chip_info }, 873 { .compatible = "adi,ad4085", &ad4085_chip_info }, 874 { .compatible = "adi,ad4086", &ad4086_chip_info }, 875 { .compatible = "adi,ad4087", &ad4087_chip_info }, 876 { .compatible = "adi,ad4088", &ad4088_chip_info }, 877 { .compatible = "adi,ad4880", &ad4880_chip_info }, 878 { .compatible = "adi,ad4884", &ad4884_chip_info }, 879 { } 880 }; 881 MODULE_DEVICE_TABLE(of, ad4080_of_match); 882 883 static struct spi_driver ad4080_driver = { 884 .driver = { 885 .name = "ad4080", 886 .of_match_table = ad4080_of_match, 887 }, 888 .probe = ad4080_probe, 889 .id_table = ad4080_id, 890 }; 891 module_spi_driver(ad4080_driver); 892 893 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); 894 MODULE_DESCRIPTION("Analog Devices AD4080"); 895 MODULE_LICENSE("GPL"); 896 MODULE_IMPORT_NS("IIO_BACKEND"); 897