1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Name: actbl1.h - Additional ACPI table definitions 5 * 6 * Copyright (C) 2000 - 2025, Intel Corp. 7 * 8 *****************************************************************************/ 9 10 #ifndef __ACTBL1_H__ 11 #define __ACTBL1_H__ 12 13 /******************************************************************************* 14 * 15 * Additional ACPI Tables 16 * 17 * These tables are not consumed directly by the ACPICA subsystem, but are 18 * included here to support device drivers and the AML disassembler. 19 * 20 ******************************************************************************/ 21 22 /* 23 * Values for description table header signatures for tables defined in this 24 * file. Useful because they make it more difficult to inadvertently type in 25 * the wrong signature. 26 */ 27 #define ACPI_SIG_AEST "AEST" /* Arm Error Source Table */ 28 #define ACPI_SIG_ASF "ASF!" /* Alert Standard Format table */ 29 #define ACPI_SIG_ASPT "ASPT" /* AMD Secure Processor Table */ 30 #define ACPI_SIG_BERT "BERT" /* Boot Error Record Table */ 31 #define ACPI_SIG_BGRT "BGRT" /* Boot Graphics Resource Table */ 32 #define ACPI_SIG_BOOT "BOOT" /* Simple Boot Flag Table */ 33 #define ACPI_SIG_CEDT "CEDT" /* CXL Early Discovery Table */ 34 #define ACPI_SIG_CPEP "CPEP" /* Corrected Platform Error Polling table */ 35 #define ACPI_SIG_CSRT "CSRT" /* Core System Resource Table */ 36 #define ACPI_SIG_DBG2 "DBG2" /* Debug Port table type 2 */ 37 #define ACPI_SIG_DBGP "DBGP" /* Debug Port table */ 38 #define ACPI_SIG_DMAR "DMAR" /* DMA Remapping table */ 39 #define ACPI_SIG_DRTM "DRTM" /* Dynamic Root of Trust for Measurement table */ 40 #define ACPI_SIG_DTPR "DTPR" /* DMA TXT Protection Ranges table */ 41 #define ACPI_SIG_ECDT "ECDT" /* Embedded Controller Boot Resources Table */ 42 #define ACPI_SIG_EINJ "EINJ" /* Error Injection table */ 43 #define ACPI_SIG_ERST "ERST" /* Error Record Serialization Table */ 44 #define ACPI_SIG_FPDT "FPDT" /* Firmware Performance Data Table */ 45 #define ACPI_SIG_GTDT "GTDT" /* Generic Timer Description Table */ 46 #define ACPI_SIG_HEST "HEST" /* Hardware Error Source Table */ 47 #define ACPI_SIG_HMAT "HMAT" /* Heterogeneous Memory Attributes Table */ 48 #define ACPI_SIG_HPET "HPET" /* High Precision Event Timer table */ 49 #define ACPI_SIG_IBFT "IBFT" /* iSCSI Boot Firmware Table */ 50 #define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */ 51 52 #define ACPI_SIG_S3PT "S3PT" /* S3 Performance (sub)Table */ 53 #define ACPI_SIG_PCCS "PCC" /* PCC Shared Memory Region */ 54 55 #define ACPI_SIG_NBFT "NBFT" /* NVMe Boot Firmware Table */ 56 57 /* Reserved table signatures */ 58 59 #define ACPI_SIG_MATR "MATR" /* Memory Address Translation Table */ 60 #define ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */ 61 62 /* 63 * These tables have been seen in the field, but no definition has been found 64 */ 65 #ifdef ACPI_UNDEFINED_TABLES 66 #define ACPI_SIG_ATKG "ATKG" 67 #define ACPI_SIG_GSCI "GSCI" /* GMCH SCI table */ 68 #define ACPI_SIG_IEIT "IEIT" 69 #endif 70 71 /* 72 * All tables must be byte-packed to match the ACPI specification, since 73 * the tables are provided by the system BIOS. 74 */ 75 #pragma pack(1) 76 77 /* 78 * Note: C bitfields are not used for this reason: 79 * 80 * "Bitfields are great and easy to read, but unfortunately the C language 81 * does not specify the layout of bitfields in memory, which means they are 82 * essentially useless for dealing with packed data in on-disk formats or 83 * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me, 84 * this decision was a design error in C. Ritchie could have picked an order 85 * and stuck with it." Norman Ramsey. 86 * See http://stackoverflow.com/a/1053662/41661 87 */ 88 89 /******************************************************************************* 90 * 91 * Common subtable headers 92 * 93 ******************************************************************************/ 94 95 /* Generic subtable header (used in MADT, SRAT, etc.) */ 96 97 struct acpi_subtable_header { 98 u8 type; 99 u8 length; 100 }; 101 102 /* Subtable header for WHEA tables (EINJ, ERST, WDAT) */ 103 104 struct acpi_whea_header { 105 u8 action; 106 u8 instruction; 107 u8 flags; 108 u8 reserved; 109 struct acpi_generic_address register_region; 110 u64 value; /* Value used with Read/Write register */ 111 u64 mask; /* Bitmask required for this register instruction */ 112 }; 113 114 /* https://docs.microsoft.com/en-us/windows-hardware/drivers/ddi/acpitabl/ns-acpitabl-aspt_table */ 115 #define ASPT_REVISION_ID 0x01 116 struct acpi_table_aspt { 117 struct acpi_table_header header; 118 u32 num_entries; 119 }; 120 121 struct acpi_aspt_header { 122 u16 type; 123 u16 length; 124 }; 125 126 enum acpi_aspt_type { 127 ACPI_ASPT_TYPE_GLOBAL_REGS = 0, 128 ACPI_ASPT_TYPE_SEV_MBOX_REGS = 1, 129 ACPI_ASPT_TYPE_ACPI_MBOX_REGS = 2, 130 }; 131 132 /* 0: ASPT Global Registers */ 133 struct acpi_aspt_global_regs { 134 struct acpi_aspt_header header; 135 u32 reserved; 136 u64 feature_reg_addr; 137 u64 irq_en_reg_addr; 138 u64 irq_st_reg_addr; 139 }; 140 141 /* 1: ASPT SEV Mailbox Registers */ 142 struct acpi_aspt_sev_mbox_regs { 143 struct acpi_aspt_header header; 144 u8 mbox_irq_id; 145 u8 reserved[3]; 146 u64 cmd_resp_reg_addr; 147 u64 cmd_buf_lo_reg_addr; 148 u64 cmd_buf_hi_reg_addr; 149 }; 150 151 /* 2: ASPT ACPI Mailbox Registers */ 152 struct acpi_aspt_acpi_mbox_regs { 153 struct acpi_aspt_header header; 154 u32 reserved1; 155 u64 cmd_resp_reg_addr; 156 u64 reserved2[2]; 157 }; 158 159 /* Larger subtable header (when Length can exceed 255) */ 160 161 struct acpi_subtbl_hdr_16 { 162 u16 type; 163 u16 length; 164 }; 165 166 /******************************************************************************* 167 * 168 * ASF - Alert Standard Format table (Signature "ASF!") 169 * Revision 0x10 170 * 171 * Conforms to the Alert Standard Format Specification V2.0, 23 April 2003 172 * 173 ******************************************************************************/ 174 175 struct acpi_table_asf { 176 struct acpi_table_header header; /* Common ACPI table header */ 177 }; 178 179 /* ASF subtable header */ 180 181 struct acpi_asf_header { 182 u8 type; 183 u8 reserved; 184 u16 length; 185 }; 186 187 /* Values for Type field above */ 188 189 enum acpi_asf_type { 190 ACPI_ASF_TYPE_INFO = 0, 191 ACPI_ASF_TYPE_ALERT = 1, 192 ACPI_ASF_TYPE_CONTROL = 2, 193 ACPI_ASF_TYPE_BOOT = 3, 194 ACPI_ASF_TYPE_ADDRESS = 4, 195 ACPI_ASF_TYPE_RESERVED = 5 196 }; 197 198 /* 199 * ASF subtables 200 */ 201 202 /* 0: ASF Information */ 203 204 struct acpi_asf_info { 205 struct acpi_asf_header header; 206 u8 min_reset_value; 207 u8 min_poll_interval; 208 u16 system_id; 209 u32 mfg_id; 210 u8 flags; 211 u8 reserved2[3]; 212 }; 213 214 /* Masks for Flags field above */ 215 216 #define ACPI_ASF_SMBUS_PROTOCOLS (1) 217 218 /* 1: ASF Alerts */ 219 220 struct acpi_asf_alert { 221 struct acpi_asf_header header; 222 u8 assert_mask; 223 u8 deassert_mask; 224 u8 alerts; 225 u8 data_length; 226 }; 227 228 struct acpi_asf_alert_data { 229 u8 address; 230 u8 command; 231 u8 mask; 232 u8 value; 233 u8 sensor_type; 234 u8 type; 235 u8 offset; 236 u8 source_type; 237 u8 severity; 238 u8 sensor_number; 239 u8 entity; 240 u8 instance; 241 }; 242 243 /* 2: ASF Remote Control */ 244 245 struct acpi_asf_remote { 246 struct acpi_asf_header header; 247 u8 controls; 248 u8 data_length; 249 u16 reserved2; 250 }; 251 252 struct acpi_asf_control_data { 253 u8 function; 254 u8 address; 255 u8 command; 256 u8 value; 257 }; 258 259 /* 3: ASF RMCP Boot Options */ 260 261 struct acpi_asf_rmcp { 262 struct acpi_asf_header header; 263 u8 capabilities[7]; 264 u8 completion_code; 265 u32 enterprise_id; 266 u8 command; 267 u16 parameter; 268 u16 boot_options; 269 u16 oem_parameters; 270 }; 271 272 /* 4: ASF Address */ 273 274 struct acpi_asf_address { 275 struct acpi_asf_header header; 276 u8 eprom_address; 277 u8 devices; 278 }; 279 280 /******************************************************************************* 281 * 282 * BERT - Boot Error Record Table (ACPI 4.0) 283 * Version 1 284 * 285 ******************************************************************************/ 286 287 struct acpi_table_bert { 288 struct acpi_table_header header; /* Common ACPI table header */ 289 u32 region_length; /* Length of the boot error region */ 290 u64 address; /* Physical address of the error region */ 291 }; 292 293 /* Boot Error Region (not a subtable, pointed to by Address field above) */ 294 295 struct acpi_bert_region { 296 u32 block_status; /* Type of error information */ 297 u32 raw_data_offset; /* Offset to raw error data */ 298 u32 raw_data_length; /* Length of raw error data */ 299 u32 data_length; /* Length of generic error data */ 300 u32 error_severity; /* Severity code */ 301 }; 302 303 /* Values for block_status flags above */ 304 305 #define ACPI_BERT_UNCORRECTABLE (1) 306 #define ACPI_BERT_CORRECTABLE (1<<1) 307 #define ACPI_BERT_MULTIPLE_UNCORRECTABLE (1<<2) 308 #define ACPI_BERT_MULTIPLE_CORRECTABLE (1<<3) 309 #define ACPI_BERT_ERROR_ENTRY_COUNT (0xFF<<4) /* 8 bits, error count */ 310 311 /* Values for error_severity above */ 312 313 enum acpi_bert_error_severity { 314 ACPI_BERT_ERROR_CORRECTABLE = 0, 315 ACPI_BERT_ERROR_FATAL = 1, 316 ACPI_BERT_ERROR_CORRECTED = 2, 317 ACPI_BERT_ERROR_NONE = 3, 318 ACPI_BERT_ERROR_RESERVED = 4 /* 4 and greater are reserved */ 319 }; 320 321 /* 322 * Note: The generic error data that follows the error_severity field above 323 * uses the struct acpi_hest_generic_data defined under the HEST table below 324 */ 325 326 /******************************************************************************* 327 * 328 * BGRT - Boot Graphics Resource Table (ACPI 5.0) 329 * Version 1 330 * 331 ******************************************************************************/ 332 333 struct acpi_table_bgrt { 334 struct acpi_table_header header; /* Common ACPI table header */ 335 u16 version; 336 u8 status; 337 u8 image_type; 338 u64 image_address; 339 u32 image_offset_x; 340 u32 image_offset_y; 341 }; 342 343 /* Flags for Status field above */ 344 345 #define ACPI_BGRT_DISPLAYED (1) 346 #define ACPI_BGRT_ORIENTATION_OFFSET (3 << 1) 347 348 /******************************************************************************* 349 * 350 * BOOT - Simple Boot Flag Table 351 * Version 1 352 * 353 * Conforms to the "Simple Boot Flag Specification", Version 2.1 354 * 355 ******************************************************************************/ 356 357 struct acpi_table_boot { 358 struct acpi_table_header header; /* Common ACPI table header */ 359 u8 cmos_index; /* Index in CMOS RAM for the boot register */ 360 u8 reserved[3]; 361 }; 362 363 /******************************************************************************* 364 * 365 * CDAT - Coherent Device Attribute Table 366 * Version 1 367 * 368 * Conforms to the "Coherent Device Attribute Table (CDAT) Specification 369 " (Revision 1.01, October 2020.) 370 * 371 ******************************************************************************/ 372 373 struct acpi_table_cdat { 374 u32 length; /* Length of table in bytes, including this header */ 375 u8 revision; /* ACPI Specification minor version number */ 376 u8 checksum; /* To make sum of entire table == 0 */ 377 u8 reserved[6]; 378 u32 sequence; /* Used to detect runtime CDAT table changes */ 379 }; 380 381 /* CDAT common subtable header */ 382 383 struct acpi_cdat_header { 384 u8 type; 385 u8 reserved; 386 u16 length; 387 }; 388 389 /* Values for Type field above */ 390 391 enum acpi_cdat_type { 392 ACPI_CDAT_TYPE_DSMAS = 0, 393 ACPI_CDAT_TYPE_DSLBIS = 1, 394 ACPI_CDAT_TYPE_DSMSCIS = 2, 395 ACPI_CDAT_TYPE_DSIS = 3, 396 ACPI_CDAT_TYPE_DSEMTS = 4, 397 ACPI_CDAT_TYPE_SSLBIS = 5, 398 ACPI_CDAT_TYPE_RESERVED = 6 /* 6 through 0xFF are reserved */ 399 }; 400 401 /* Subtable 0: Device Scoped Memory Affinity Structure (DSMAS) */ 402 403 struct acpi_cdat_dsmas { 404 u8 dsmad_handle; 405 u8 flags; 406 u16 reserved; 407 u64 dpa_base_address; 408 u64 dpa_length; 409 }; 410 411 /* Flags for subtable above */ 412 413 #define ACPI_CDAT_DSMAS_NON_VOLATILE (1 << 2) 414 #define ACPI_CDAT_DSMAS_SHAREABLE (1 << 3) 415 #define ACPI_CDAT_DSMAS_READ_ONLY (1 << 6) 416 417 /* Subtable 1: Device scoped Latency and Bandwidth Information Structure (DSLBIS) */ 418 419 struct acpi_cdat_dslbis { 420 u8 handle; 421 u8 flags; /* If Handle matches a DSMAS handle, the definition of this field matches 422 * Flags field in HMAT System Locality Latency */ 423 u8 data_type; 424 u8 reserved; 425 u64 entry_base_unit; 426 u16 entry[3]; 427 u16 reserved2; 428 }; 429 430 /* Subtable 2: Device Scoped Memory Side Cache Information Structure (DSMSCIS) */ 431 432 struct acpi_cdat_dsmscis { 433 u8 dsmas_handle; 434 u8 reserved[3]; 435 u64 side_cache_size; 436 u32 cache_attributes; 437 }; 438 439 /* Subtable 3: Device Scoped Initiator Structure (DSIS) */ 440 441 struct acpi_cdat_dsis { 442 u8 flags; 443 u8 handle; 444 u16 reserved; 445 }; 446 447 /* Flags for above subtable */ 448 449 #define ACPI_CDAT_DSIS_MEM_ATTACHED (1 << 0) 450 451 /* Subtable 4: Device Scoped EFI Memory Type Structure (DSEMTS) */ 452 453 struct acpi_cdat_dsemts { 454 u8 dsmas_handle; 455 u8 memory_type; 456 u16 reserved; 457 u64 dpa_offset; 458 u64 range_length; 459 }; 460 461 /* Subtable 5: Switch Scoped Latency and Bandwidth Information Structure (SSLBIS) */ 462 463 struct acpi_cdat_sslbis { 464 u8 data_type; 465 u8 reserved[3]; 466 u64 entry_base_unit; 467 }; 468 469 /* Sub-subtable for above, sslbe_entries field */ 470 471 struct acpi_cdat_sslbe { 472 u16 portx_id; 473 u16 porty_id; 474 u16 latency_or_bandwidth; 475 u16 reserved; 476 }; 477 478 #define ACPI_CDAT_SSLBIS_US_PORT 0x0100 479 #define ACPI_CDAT_SSLBIS_ANY_PORT 0xffff 480 481 /******************************************************************************* 482 * 483 * CEDT - CXL Early Discovery Table 484 * Version 1 485 * 486 * Conforms to the "CXL Early Discovery Table" (CXL 2.0, October 2020) 487 * 488 ******************************************************************************/ 489 490 struct acpi_table_cedt { 491 struct acpi_table_header header; /* Common ACPI table header */ 492 }; 493 494 /* CEDT subtable header (Performance Record Structure) */ 495 496 struct acpi_cedt_header { 497 u8 type; 498 u8 reserved; 499 u16 length; 500 }; 501 502 /* Values for Type field above */ 503 504 enum acpi_cedt_type { 505 ACPI_CEDT_TYPE_CHBS = 0, 506 ACPI_CEDT_TYPE_CFMWS = 1, 507 ACPI_CEDT_TYPE_CXIMS = 2, 508 ACPI_CEDT_TYPE_RDPAS = 3, 509 ACPI_CEDT_TYPE_RESERVED = 4, 510 }; 511 512 /* Values for version field above */ 513 514 #define ACPI_CEDT_CHBS_VERSION_CXL11 (0) 515 #define ACPI_CEDT_CHBS_VERSION_CXL20 (1) 516 517 /* Values for length field above */ 518 519 #define ACPI_CEDT_CHBS_LENGTH_CXL11 (0x2000) 520 #define ACPI_CEDT_CHBS_LENGTH_CXL20 (0x10000) 521 522 /* 523 * CEDT subtables 524 */ 525 526 /* 0: CXL Host Bridge Structure */ 527 528 struct acpi_cedt_chbs { 529 struct acpi_cedt_header header; 530 u32 uid; 531 u32 cxl_version; 532 u32 reserved; 533 u64 base; 534 u64 length; 535 }; 536 537 /* 1: CXL Fixed Memory Window Structure */ 538 539 struct acpi_cedt_cfmws { 540 struct acpi_cedt_header header; 541 u32 reserved1; 542 u64 base_hpa; 543 u64 window_size; 544 u8 interleave_ways; 545 u8 interleave_arithmetic; 546 u16 reserved2; 547 u32 granularity; 548 u16 restrictions; 549 u16 qtg_id; 550 u32 interleave_targets[]; 551 }; 552 553 struct acpi_cedt_cfmws_target_element { 554 u32 interleave_target; 555 }; 556 557 /* Values for Interleave Arithmetic field above */ 558 559 #define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0) 560 #define ACPI_CEDT_CFMWS_ARITHMETIC_XOR (1) 561 562 /* Values for Restrictions field above */ 563 564 #define ACPI_CEDT_CFMWS_RESTRICT_DEVMEM (1) 565 #define ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYMEM (1<<1) 566 #define ACPI_CEDT_CFMWS_RESTRICT_VOLATILE (1<<2) 567 #define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3) 568 #define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4) 569 #define ACPI_CEDT_CFMWS_RESTRICT_BI (1<<5) 570 571 /* 2: CXL XOR Interleave Math Structure */ 572 573 struct acpi_cedt_cxims { 574 struct acpi_cedt_header header; 575 u16 reserved1; 576 u8 hbig; 577 u8 nr_xormaps; 578 u64 xormap_list[]; 579 }; 580 581 struct acpi_cedt_cxims_target_element { 582 u64 xormap; 583 }; 584 585 /* 3: CXL RCEC Downstream Port Association Structure */ 586 587 struct acpi_cedt_rdpas { 588 struct acpi_cedt_header header; 589 u16 segment; 590 u16 bdf; 591 u8 protocol; 592 u64 address; 593 }; 594 595 /* Masks for bdf field above */ 596 #define ACPI_CEDT_RDPAS_BUS_MASK 0xff00 597 #define ACPI_CEDT_RDPAS_DEVICE_MASK 0x00f8 598 #define ACPI_CEDT_RDPAS_FUNCTION_MASK 0x0007 599 600 #define ACPI_CEDT_RDPAS_PROTOCOL_IO (0) 601 #define ACPI_CEDT_RDPAS_PROTOCOL_CACHEMEM (1) 602 603 /******************************************************************************* 604 * 605 * CPEP - Corrected Platform Error Polling table (ACPI 4.0) 606 * Version 1 607 * 608 ******************************************************************************/ 609 610 struct acpi_table_cpep { 611 struct acpi_table_header header; /* Common ACPI table header */ 612 u64 reserved; 613 }; 614 615 /* Subtable */ 616 617 struct acpi_cpep_polling { 618 struct acpi_subtable_header header; 619 u8 id; /* Processor ID */ 620 u8 eid; /* Processor EID */ 621 u32 interval; /* Polling interval (msec) */ 622 }; 623 624 /******************************************************************************* 625 * 626 * CSRT - Core System Resource Table 627 * Version 0 628 * 629 * Conforms to the "Core System Resource Table (CSRT)", November 14, 2011 630 * 631 ******************************************************************************/ 632 633 struct acpi_table_csrt { 634 struct acpi_table_header header; /* Common ACPI table header */ 635 }; 636 637 /* Resource Group subtable */ 638 639 struct acpi_csrt_group { 640 u32 length; 641 u32 vendor_id; 642 u32 subvendor_id; 643 u16 device_id; 644 u16 subdevice_id; 645 u16 revision; 646 u16 reserved; 647 u32 shared_info_length; 648 649 /* Shared data immediately follows (Length = shared_info_length) */ 650 }; 651 652 /* Shared Info subtable */ 653 654 struct acpi_csrt_shared_info { 655 u16 major_version; 656 u16 minor_version; 657 u32 mmio_base_low; 658 u32 mmio_base_high; 659 u32 gsi_interrupt; 660 u8 interrupt_polarity; 661 u8 interrupt_mode; 662 u8 num_channels; 663 u8 dma_address_width; 664 u16 base_request_line; 665 u16 num_handshake_signals; 666 u32 max_block_size; 667 668 /* Resource descriptors immediately follow (Length = Group length - shared_info_length) */ 669 }; 670 671 /* Resource Descriptor subtable */ 672 673 struct acpi_csrt_descriptor { 674 u32 length; 675 u16 type; 676 u16 subtype; 677 u32 uid; 678 679 /* Resource-specific information immediately follows */ 680 }; 681 682 /* Resource Types */ 683 684 #define ACPI_CSRT_TYPE_INTERRUPT 0x0001 685 #define ACPI_CSRT_TYPE_TIMER 0x0002 686 #define ACPI_CSRT_TYPE_DMA 0x0003 687 688 /* Resource Subtypes */ 689 690 #define ACPI_CSRT_XRUPT_LINE 0x0000 691 #define ACPI_CSRT_XRUPT_CONTROLLER 0x0001 692 #define ACPI_CSRT_TIMER 0x0000 693 #define ACPI_CSRT_DMA_CHANNEL 0x0000 694 #define ACPI_CSRT_DMA_CONTROLLER 0x0001 695 696 /******************************************************************************* 697 * 698 * DBG2 - Debug Port Table 2 699 * Version 0 (Both main table and subtables) 700 * 701 * Conforms to "Microsoft Debug Port Table 2 (DBG2)", September 21, 2020 702 * 703 ******************************************************************************/ 704 705 struct acpi_table_dbg2 { 706 struct acpi_table_header header; /* Common ACPI table header */ 707 u32 info_offset; 708 u32 info_count; 709 }; 710 711 struct acpi_dbg2_header { 712 u32 info_offset; 713 u32 info_count; 714 }; 715 716 /* Debug Device Information Subtable */ 717 718 struct acpi_dbg2_device { 719 u8 revision; 720 u16 length; 721 u8 register_count; /* Number of base_address registers */ 722 u16 namepath_length; 723 u16 namepath_offset; 724 u16 oem_data_length; 725 u16 oem_data_offset; 726 u16 port_type; 727 u16 port_subtype; 728 u16 reserved; 729 u16 base_address_offset; 730 u16 address_size_offset; 731 /* 732 * Data that follows: 733 * base_address (required) - Each in 12-byte Generic Address Structure format. 734 * address_size (required) - Array of u32 sizes corresponding to each base_address register. 735 * Namepath (required) - Null terminated string. Single dot if not supported. 736 * oem_data (optional) - Length is oem_data_length. 737 */ 738 }; 739 740 /* Types for port_type field above */ 741 742 #define ACPI_DBG2_SERIAL_PORT 0x8000 743 #define ACPI_DBG2_1394_PORT 0x8001 744 #define ACPI_DBG2_USB_PORT 0x8002 745 #define ACPI_DBG2_NET_PORT 0x8003 746 747 /* Subtypes for port_subtype field above */ 748 749 #define ACPI_DBG2_16550_COMPATIBLE 0x0000 750 #define ACPI_DBG2_16550_SUBSET 0x0001 751 #define ACPI_DBG2_MAX311XE_SPI 0x0002 752 #define ACPI_DBG2_ARM_PL011 0x0003 753 #define ACPI_DBG2_MSM8X60 0x0004 754 #define ACPI_DBG2_16550_NVIDIA 0x0005 755 #define ACPI_DBG2_TI_OMAP 0x0006 756 #define ACPI_DBG2_APM88XXXX 0x0008 757 #define ACPI_DBG2_MSM8974 0x0009 758 #define ACPI_DBG2_SAM5250 0x000A 759 #define ACPI_DBG2_INTEL_USIF 0x000B 760 #define ACPI_DBG2_IMX6 0x000C 761 #define ACPI_DBG2_ARM_SBSA_32BIT 0x000D 762 #define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E 763 #define ACPI_DBG2_ARM_DCC 0x000F 764 #define ACPI_DBG2_BCM2835 0x0010 765 #define ACPI_DBG2_SDM845_1_8432MHZ 0x0011 766 #define ACPI_DBG2_16550_WITH_GAS 0x0012 767 #define ACPI_DBG2_SDM845_7_372MHZ 0x0013 768 #define ACPI_DBG2_INTEL_LPSS 0x0014 769 #define ACPI_DBG2_RISCV_SBI_CON 0x0015 770 771 #define ACPI_DBG2_1394_STANDARD 0x0000 772 773 #define ACPI_DBG2_USB_XHCI 0x0000 774 #define ACPI_DBG2_USB_EHCI 0x0001 775 776 /******************************************************************************* 777 * 778 * DBGP - Debug Port table 779 * Version 1 780 * 781 * Conforms to the "Debug Port Specification", Version 1.00, 2/9/2000 782 * 783 ******************************************************************************/ 784 785 struct acpi_table_dbgp { 786 struct acpi_table_header header; /* Common ACPI table header */ 787 u8 type; /* 0=full 16550, 1=subset of 16550 */ 788 u8 reserved[3]; 789 struct acpi_generic_address debug_port; 790 }; 791 792 /******************************************************************************* 793 * 794 * DMAR - DMA Remapping table 795 * Version 1 796 * 797 * Conforms to "Intel Virtualization Technology for Directed I/O", 798 * Version 2.3, October 2014 799 * 800 ******************************************************************************/ 801 802 struct acpi_table_dmar { 803 struct acpi_table_header header; /* Common ACPI table header */ 804 u8 width; /* Host Address Width */ 805 u8 flags; 806 u8 reserved[10]; 807 }; 808 809 /* Masks for Flags field above */ 810 811 #define ACPI_DMAR_INTR_REMAP (1) 812 #define ACPI_DMAR_X2APIC_OPT_OUT (1<<1) 813 #define ACPI_DMAR_X2APIC_MODE (1<<2) 814 815 /* DMAR subtable header */ 816 817 struct acpi_dmar_header { 818 u16 type; 819 u16 length; 820 }; 821 822 /* Values for subtable type in struct acpi_dmar_header */ 823 824 enum acpi_dmar_type { 825 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, 826 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, 827 ACPI_DMAR_TYPE_ROOT_ATS = 2, 828 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, 829 ACPI_DMAR_TYPE_NAMESPACE = 4, 830 ACPI_DMAR_TYPE_SATC = 5, 831 ACPI_DMAR_TYPE_SIDP = 6, 832 ACPI_DMAR_TYPE_RESERVED = 7 /* 7 and greater are reserved */ 833 }; 834 835 /* DMAR Device Scope structure */ 836 837 struct acpi_dmar_device_scope { 838 u8 entry_type; 839 u8 length; 840 u8 flags; 841 u8 reserved; 842 u8 enumeration_id; 843 u8 bus; 844 }; 845 846 /* Values for entry_type in struct acpi_dmar_device_scope - device types */ 847 848 enum acpi_dmar_scope_type { 849 ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0, 850 ACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1, 851 ACPI_DMAR_SCOPE_TYPE_BRIDGE = 2, 852 ACPI_DMAR_SCOPE_TYPE_IOAPIC = 3, 853 ACPI_DMAR_SCOPE_TYPE_HPET = 4, 854 ACPI_DMAR_SCOPE_TYPE_NAMESPACE = 5, 855 ACPI_DMAR_SCOPE_TYPE_RESERVED = 6 /* 6 and greater are reserved */ 856 }; 857 858 struct acpi_dmar_pci_path { 859 u8 device; 860 u8 function; 861 }; 862 863 /* 864 * DMAR Subtables, correspond to Type in struct acpi_dmar_header 865 */ 866 867 /* 0: Hardware Unit Definition */ 868 869 struct acpi_dmar_hardware_unit { 870 struct acpi_dmar_header header; 871 u8 flags; 872 u8 size; /* Size of the register set */ 873 u16 segment; 874 u64 address; /* Register Base Address */ 875 }; 876 877 /* Masks for Flags field above */ 878 879 #define ACPI_DMAR_INCLUDE_ALL (1) 880 881 /* 1: Reserved Memory Definition */ 882 883 struct acpi_dmar_reserved_memory { 884 struct acpi_dmar_header header; 885 u16 reserved; 886 u16 segment; 887 u64 base_address; /* 4K aligned base address */ 888 u64 end_address; /* 4K aligned limit address */ 889 }; 890 891 /* Masks for Flags field above */ 892 893 #define ACPI_DMAR_ALLOW_ALL (1) 894 895 /* 2: Root Port ATS Capability Reporting Structure */ 896 897 struct acpi_dmar_atsr { 898 struct acpi_dmar_header header; 899 u8 flags; 900 u8 reserved; 901 u16 segment; 902 }; 903 904 /* Masks for Flags field above */ 905 906 #define ACPI_DMAR_ALL_PORTS (1) 907 908 /* 3: Remapping Hardware Static Affinity Structure */ 909 910 struct acpi_dmar_rhsa { 911 struct acpi_dmar_header header; 912 u32 reserved; 913 u64 base_address; 914 u32 proximity_domain; 915 }; 916 917 /* 4: ACPI Namespace Device Declaration Structure */ 918 919 struct acpi_dmar_andd { 920 struct acpi_dmar_header header; 921 u8 reserved[3]; 922 u8 device_number; 923 union { 924 char __pad; 925 ACPI_FLEX_ARRAY(char, device_name); 926 }; 927 }; 928 929 /* 5: SOC Integrated Address Translation Cache Reporting Structure */ 930 931 struct acpi_dmar_satc { 932 struct acpi_dmar_header header; 933 u8 flags; 934 u8 reserved; 935 u16 segment; 936 }; 937 938 /* 6: so_c Integrated Device Property Reporting Structure */ 939 940 struct acpi_dmar_sidp { 941 struct acpi_dmar_header header; 942 u16 reserved; 943 u16 segment; 944 }; 945 946 /******************************************************************************* 947 * 948 * DRTM - Dynamic Root of Trust for Measurement table 949 * Conforms to "TCG D-RTM Architecture" June 17 2013, Version 1.0.0 950 * Table version 1 951 * 952 ******************************************************************************/ 953 954 struct acpi_table_drtm { 955 struct acpi_table_header header; /* Common ACPI table header */ 956 u64 entry_base_address; 957 u64 entry_length; 958 u32 entry_address32; 959 u64 entry_address64; 960 u64 exit_address; 961 u64 log_area_address; 962 u32 log_area_length; 963 u64 arch_dependent_address; 964 u32 flags; 965 }; 966 967 /* Flag Definitions for above */ 968 969 #define ACPI_DRTM_ACCESS_ALLOWED (1) 970 #define ACPI_DRTM_ENABLE_GAP_CODE (1<<1) 971 #define ACPI_DRTM_INCOMPLETE_MEASUREMENTS (1<<2) 972 #define ACPI_DRTM_AUTHORITY_ORDER (1<<3) 973 974 /* 1) Validated Tables List (64-bit addresses) */ 975 976 struct acpi_drtm_vtable_list { 977 u32 validated_table_count; 978 u64 validated_tables[]; 979 }; 980 981 /* 2) Resources List (of Resource Descriptors) */ 982 983 /* Resource Descriptor */ 984 985 struct acpi_drtm_resource { 986 u8 size[7]; 987 u8 type; 988 u64 address; 989 }; 990 991 struct acpi_drtm_resource_list { 992 u32 resource_count; 993 struct acpi_drtm_resource resources[]; 994 }; 995 996 /* 3) Platform-specific Identifiers List */ 997 998 struct acpi_drtm_dps_id { 999 u32 dps_id_length; 1000 u8 dps_id[16]; 1001 }; 1002 1003 /******************************************************************************* 1004 * 1005 * DTPR - DMA TXT Protection Ranges Table 1006 * Version 1 1007 * 1008 * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection 1009 * Ranges", 1010 * Revision 0.73, August 2021 1011 * 1012 ******************************************************************************/ 1013 1014 struct acpi_table_dtpr { 1015 struct acpi_table_header header; 1016 u32 flags; /* 36 */ 1017 u32 ins_cnt; 1018 }; 1019 1020 struct acpi_tpr_array { 1021 u64 base; 1022 }; 1023 1024 struct acpi_tpr_instance { 1025 u32 flags; 1026 u32 tpr_cnt; 1027 }; 1028 1029 struct acpi_tpr_aux_sr { 1030 u32 srl_cnt; 1031 }; 1032 1033 /* 1034 * TPRn_BASE (ACPI_TPRN_BASE_REG) 1035 * 1036 * Specifies the start address of TPRn region. TPR region address and size must 1037 * be with 1MB resolution. These bits are compared with the result of the 1038 * TPRn_LIMIT[63:20], which is applied to the incoming address, to 1039 * determine if an access fall within the TPRn defined region. 1040 * 1041 * Minimal TPRn_Base resolution is 1MB. Applied to the incoming address, to 1042 * determine if an access fall within the TPRn defined region. Width is 1043 * determined by a bus width which can be obtained via CPUID 1044 * function 0x80000008. 1045 */ 1046 1047 typedef u64 ACPI_TPRN_BASE_REG; 1048 1049 /* TPRn_BASE Register Bit Masks */ 1050 1051 /* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ 1052 #define ACPI_TPRN_BASE_RW_SHIFT 3 1053 1054 #define ACPI_TPRN_BASE_RW_MASK ((u64) 1 << ACPI_TPRN_BASE_RW_SHIFT) 1055 1056 /* 1057 * Bit 4 - Enable: 0 – TPRn address range enabled; 1058 * 1 – TPRn address range disabled. 1059 */ 1060 #define ACPI_TPRN_BASE_ENABLE_SHIFT 4 1061 1062 #define ACPI_TPRN_BASE_ENABLE_MASK ((u64) 1 << ACPI_TPRN_BASE_ENABLE_SHIFT) 1063 1064 /* Bits 63:20 - tpr_base_rw */ 1065 #define ACPI_TPRN_BASE_ADDR_SHIFT 20 1066 1067 #define ACPI_TPRN_BASE_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \ 1068 ACPI_TPRN_BASE_ADDR_SHIFT) 1069 1070 /* TPRn_BASE Register Bit Handlers*/ 1071 1072 /* 1073 * GET_TPRN_BASE_RW: 1074 * 1075 * Read RW bit from TPRn Base register - bit 3. 1076 * 1077 * Input: 1078 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1079 * 1080 * Output: 1081 * 1082 * Returns RW bit value (u64). 1083 */ 1084 #define GET_TPRN_BASE_RW(reg) (((u64) reg & ACPI_TPRN_BASE_RW_MASK) >> \ 1085 ACPI_TPRN_BASE_RW_SHIFT) 1086 1087 /* 1088 * GET_TPRN_BASE_ENABLE: 1089 * 1090 * Read Enable bit from TPRn Base register - bit 4. 1091 * 1092 * Input: 1093 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1094 * 1095 * Output: 1096 * 1097 * Returns Enable bit value (u64). 1098 */ 1099 #define GET_TPRN_BASE_ENABLE(reg) (((u64) reg & ACPI_TPRN_BASE_ENABLE_MASK) \ 1100 >> ACPI_TPRN_BASE_ENABLE_SHIFT) 1101 1102 /* 1103 * GET_TPRN_BASE_ADDR: 1104 * 1105 * Read TPRn Base Register address from bits 63:20. 1106 * 1107 * Input: 1108 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1109 * 1110 * Output: 1111 * 1112 * Returns TPRn Base Register address (u64). 1113 */ 1114 #define GET_TPRN_BASE_ADDR(reg) (((u64) reg & ACPI_TPRN_BASE_ADDR_MASK) \ 1115 >> ACPI_TPRN_BASE_ADDR_SHIFT) 1116 1117 /* 1118 * SET_TPRN_BASE_RW: 1119 * 1120 * Set RW bit in TPRn Base register - bit 3. 1121 * 1122 * Input: 1123 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1124 * - val (represents RW value to be set (u64)) 1125 */ 1126 #define SET_TPRN_BASE_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1127 ACPI_TPRN_BASE_RW_SHIFT, \ 1128 ACPI_TPRN_BASE_RW_MASK, val); 1129 1130 /* 1131 * SET_TPRN_BASE_ENABLE: 1132 * 1133 * Set Enable bit in TPRn Base register - bit 4. 1134 * 1135 * Input: 1136 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1137 * - val (represents Enable value to be set (u64)) 1138 */ 1139 #define SET_TPRN_BASE_ENABLE(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1140 ACPI_TPRN_BASE_ENABLE_SHIFT, \ 1141 ACPI_TPRN_BASE_ENABLE_MASK, val); 1142 1143 /* 1144 * SET_TPRN_BASE_ADDR: 1145 * 1146 * Set TPRn Base Register address - bits 63:20 1147 * 1148 * Input 1149 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1150 * - val (represents address value to be set (u64)) 1151 */ 1152 #define SET_TPRN_BASE_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1153 ACPI_TPRN_BASE_ADDR_SHIFT, \ 1154 ACPI_TPRN_BASE_ADDR_MASK, val); 1155 1156 /* 1157 * TPRn_LIMIT 1158 * 1159 * This register defines an isolated region of memory that can be enabled 1160 * to prohibit certain system agents from accessing memory. When an agent 1161 * sends a request upstream, whether snooped or not, a TPR prevents that 1162 * transaction from changing the state of memory. 1163 * 1164 * Minimal TPRn_Limit resolution is 1MB. Width is determined by a bus width. 1165 */ 1166 1167 typedef u64 ACPI_TPRN_LIMIT_REG; 1168 1169 /* TPRn_LIMIT Register Bit Masks */ 1170 1171 /* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ 1172 #define ACPI_TPRN_LIMIT_RW_SHIFT 3 1173 1174 #define ACPI_TPRN_LIMIT_RW_MASK ((u64) 1 << ACPI_TPRN_LIMIT_RW_SHIFT) 1175 1176 /* Bits 63:20 - tpr_limit_rw */ 1177 #define ACPI_TPRN_LIMIT_ADDR_SHIFT 20 1178 1179 #define ACPI_TPRN_LIMIT_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \ 1180 ACPI_TPRN_LIMIT_ADDR_SHIFT) 1181 1182 /* TPRn_LIMIT Register Bit Handlers*/ 1183 1184 /* 1185 * GET_TPRN_LIMIT_RW: 1186 * 1187 * Read RW bit from TPRn Limit register - bit 3. 1188 * 1189 * Input: 1190 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1191 * 1192 * Output: 1193 * 1194 * Returns RW bit value (u64). 1195 */ 1196 #define GET_TPRN_LIMIT_RW(reg) (((u64) reg & ACPI_TPRN_LIMIT_RW_MASK) \ 1197 >> ACPI_TPRN_LIMIT_RW_SHIFT) 1198 1199 /* 1200 * GET_TPRN_LIMIT_ADDR: 1201 * 1202 * Read TPRn Limit Register address from bits 63:20. 1203 * 1204 * Input: 1205 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1206 * 1207 * Output: 1208 * 1209 * Returns TPRn Limit Register address (u64). 1210 */ 1211 #define GET_TPRN_LIMIT_ADDR(reg) (((u64) reg & ACPI_TPRN_LIMIT_ADDR_MASK) \ 1212 >> ACPI_TPRN_LIMIT_ADDR_SHIFT) 1213 1214 /* 1215 * SET_TPRN_LIMIT_RW: 1216 * 1217 * Set RW bit in TPRn Limit register - bit 3. 1218 * 1219 * Input: 1220 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1221 * - val (represents RW value to be set (u64)) 1222 */ 1223 #define SET_TPRN_LIMIT_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1224 ACPI_TPRN_LIMIT_RW_SHIFT, \ 1225 ACPI_TPRN_LIMIT_RW_MASK, val); 1226 1227 /* 1228 * SET_TPRN_LIMIT_ADDR: 1229 * 1230 * Set TPRn Limit Register address - bits 63:20. 1231 * 1232 * Input: 1233 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1234 * - val (represents address value to be set (u64)) 1235 */ 1236 #define SET_TPRN_LIMIT_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1237 ACPI_TPRN_LIMIT_ADDR_SHIFT, \ 1238 ACPI_TPRN_LIMIT_ADDR_MASK, val); 1239 1240 /* 1241 * SERIALIZE_REQUEST 1242 * 1243 * This register is used to request serialization of non-coherent DMA 1244 * transactions. OS shall issue it before changing of TPR settings 1245 * (base / size). 1246 */ 1247 1248 struct acpi_tpr_serialize_request { 1249 u64 sr_register; 1250 /* 1251 * BIT 1 - Status of serialization request (RO) 1252 * 0 == register idle, 1 == serialization in progress 1253 * BIT 2 - Control field to initiate serialization (RW) 1254 * 0 == normal, 1 == initialize serialization 1255 * (self-clear to allow multiple serialization requests) 1256 */ 1257 }; 1258 1259 /******************************************************************************* 1260 * 1261 * ECDT - Embedded Controller Boot Resources Table 1262 * Version 1 1263 * 1264 ******************************************************************************/ 1265 1266 struct acpi_table_ecdt { 1267 struct acpi_table_header header; /* Common ACPI table header */ 1268 struct acpi_generic_address control; /* Address of EC command/status register */ 1269 struct acpi_generic_address data; /* Address of EC data register */ 1270 u32 uid; /* Unique ID - must be same as the EC _UID method */ 1271 u8 gpe; /* The GPE for the EC */ 1272 u8 id[]; /* Full namepath of the EC in the ACPI namespace */ 1273 }; 1274 1275 /******************************************************************************* 1276 * 1277 * EINJ - Error Injection Table (ACPI 4.0) 1278 * Version 1 1279 * 1280 ******************************************************************************/ 1281 1282 struct acpi_table_einj { 1283 struct acpi_table_header header; /* Common ACPI table header */ 1284 u32 header_length; 1285 u8 flags; 1286 u8 reserved[3]; 1287 u32 entries; 1288 }; 1289 1290 /* EINJ Injection Instruction Entries (actions) */ 1291 1292 struct acpi_einj_entry { 1293 struct acpi_whea_header whea_header; /* Common header for WHEA tables */ 1294 }; 1295 1296 /* Masks for Flags field above */ 1297 1298 #define ACPI_EINJ_PRESERVE (1) 1299 1300 /* Values for Action field above */ 1301 1302 enum acpi_einj_actions { 1303 ACPI_EINJ_BEGIN_OPERATION = 0x0, 1304 ACPI_EINJ_GET_TRIGGER_TABLE = 0x1, 1305 ACPI_EINJ_SET_ERROR_TYPE = 0x2, 1306 ACPI_EINJ_GET_ERROR_TYPE = 0x3, 1307 ACPI_EINJ_END_OPERATION = 0x4, 1308 ACPI_EINJ_EXECUTE_OPERATION = 0x5, 1309 ACPI_EINJ_CHECK_BUSY_STATUS = 0x6, 1310 ACPI_EINJ_GET_COMMAND_STATUS = 0x7, 1311 ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS = 0x8, 1312 ACPI_EINJ_GET_EXECUTE_TIMINGS = 0x9, 1313 ACPI_EINJV2_GET_ERROR_TYPE = 0x11, 1314 ACPI_EINJ_ACTION_RESERVED = 0x12, /* 0x12 and greater are reserved */ 1315 ACPI_EINJ_TRIGGER_ERROR = 0xFF /* Except for this value */ 1316 }; 1317 1318 /* Values for Instruction field above */ 1319 1320 enum acpi_einj_instructions { 1321 ACPI_EINJ_READ_REGISTER = 0, 1322 ACPI_EINJ_READ_REGISTER_VALUE = 1, 1323 ACPI_EINJ_WRITE_REGISTER = 2, 1324 ACPI_EINJ_WRITE_REGISTER_VALUE = 3, 1325 ACPI_EINJ_NOOP = 4, 1326 ACPI_EINJ_FLUSH_CACHELINE = 5, 1327 ACPI_EINJ_INSTRUCTION_RESERVED = 6 /* 6 and greater are reserved */ 1328 }; 1329 1330 struct acpi_einj_error_type_with_addr { 1331 u32 error_type; 1332 u32 vendor_struct_offset; 1333 u32 flags; 1334 u32 apic_id; 1335 u64 address; 1336 u64 range; 1337 u32 pcie_id; 1338 }; 1339 1340 struct acpi_einj_vendor { 1341 u32 length; 1342 u32 pcie_id; 1343 u16 vendor_id; 1344 u16 device_id; 1345 u8 revision_id; 1346 u8 reserved[3]; 1347 }; 1348 1349 /* EINJ Trigger Error Action Table */ 1350 1351 struct acpi_einj_trigger { 1352 u32 header_size; 1353 u32 revision; 1354 u32 table_size; 1355 u32 entry_count; 1356 }; 1357 1358 /* Command status return values */ 1359 1360 enum acpi_einj_command_status { 1361 ACPI_EINJ_SUCCESS = 0, 1362 ACPI_EINJ_FAILURE = 1, 1363 ACPI_EINJ_INVALID_ACCESS = 2, 1364 ACPI_EINJ_STATUS_RESERVED = 3 /* 3 and greater are reserved */ 1365 }; 1366 1367 /* Error types returned from ACPI_EINJ_GET_ERROR_TYPE (bitfield) */ 1368 1369 #define ACPI_EINJ_PROCESSOR_CORRECTABLE (1) 1370 #define ACPI_EINJ_PROCESSOR_UNCORRECTABLE (1<<1) 1371 #define ACPI_EINJ_PROCESSOR_FATAL (1<<2) 1372 #define ACPI_EINJ_MEMORY_CORRECTABLE (1<<3) 1373 #define ACPI_EINJ_MEMORY_UNCORRECTABLE (1<<4) 1374 #define ACPI_EINJ_MEMORY_FATAL (1<<5) 1375 #define ACPI_EINJ_PCIX_CORRECTABLE (1<<6) 1376 #define ACPI_EINJ_PCIX_UNCORRECTABLE (1<<7) 1377 #define ACPI_EINJ_PCIX_FATAL (1<<8) 1378 #define ACPI_EINJ_PLATFORM_CORRECTABLE (1<<9) 1379 #define ACPI_EINJ_PLATFORM_UNCORRECTABLE (1<<10) 1380 #define ACPI_EINJ_PLATFORM_FATAL (1<<11) 1381 #define ACPI_EINJ_CXL_CACHE_CORRECTABLE (1<<12) 1382 #define ACPI_EINJ_CXL_CACHE_UNCORRECTABLE (1<<13) 1383 #define ACPI_EINJ_CXL_CACHE_FATAL (1<<14) 1384 #define ACPI_EINJ_CXL_MEM_CORRECTABLE (1<<15) 1385 #define ACPI_EINJ_CXL_MEM_UNCORRECTABLE (1<<16) 1386 #define ACPI_EINJ_CXL_MEM_FATAL (1<<17) 1387 #define ACPI_EINJ_VENDOR_DEFINED (1<<31) 1388 1389 /******************************************************************************* 1390 * 1391 * ERST - Error Record Serialization Table (ACPI 4.0) 1392 * Version 1 1393 * 1394 ******************************************************************************/ 1395 1396 struct acpi_table_erst { 1397 struct acpi_table_header header; /* Common ACPI table header */ 1398 u32 header_length; 1399 u32 reserved; 1400 u32 entries; 1401 }; 1402 1403 /* ERST Serialization Entries (actions) */ 1404 1405 struct acpi_erst_entry { 1406 struct acpi_whea_header whea_header; /* Common header for WHEA tables */ 1407 }; 1408 1409 /* Masks for Flags field above */ 1410 1411 #define ACPI_ERST_PRESERVE (1) 1412 1413 /* Values for Action field above */ 1414 1415 enum acpi_erst_actions { 1416 ACPI_ERST_BEGIN_WRITE = 0, 1417 ACPI_ERST_BEGIN_READ = 1, 1418 ACPI_ERST_BEGIN_CLEAR = 2, 1419 ACPI_ERST_END = 3, 1420 ACPI_ERST_SET_RECORD_OFFSET = 4, 1421 ACPI_ERST_EXECUTE_OPERATION = 5, 1422 ACPI_ERST_CHECK_BUSY_STATUS = 6, 1423 ACPI_ERST_GET_COMMAND_STATUS = 7, 1424 ACPI_ERST_GET_RECORD_ID = 8, 1425 ACPI_ERST_SET_RECORD_ID = 9, 1426 ACPI_ERST_GET_RECORD_COUNT = 10, 1427 ACPI_ERST_BEGIN_DUMMY_WRIITE = 11, 1428 ACPI_ERST_NOT_USED = 12, 1429 ACPI_ERST_GET_ERROR_RANGE = 13, 1430 ACPI_ERST_GET_ERROR_LENGTH = 14, 1431 ACPI_ERST_GET_ERROR_ATTRIBUTES = 15, 1432 ACPI_ERST_EXECUTE_TIMINGS = 16, 1433 ACPI_ERST_ACTION_RESERVED = 17 /* 17 and greater are reserved */ 1434 }; 1435 1436 /* Values for Instruction field above */ 1437 1438 enum acpi_erst_instructions { 1439 ACPI_ERST_READ_REGISTER = 0, 1440 ACPI_ERST_READ_REGISTER_VALUE = 1, 1441 ACPI_ERST_WRITE_REGISTER = 2, 1442 ACPI_ERST_WRITE_REGISTER_VALUE = 3, 1443 ACPI_ERST_NOOP = 4, 1444 ACPI_ERST_LOAD_VAR1 = 5, 1445 ACPI_ERST_LOAD_VAR2 = 6, 1446 ACPI_ERST_STORE_VAR1 = 7, 1447 ACPI_ERST_ADD = 8, 1448 ACPI_ERST_SUBTRACT = 9, 1449 ACPI_ERST_ADD_VALUE = 10, 1450 ACPI_ERST_SUBTRACT_VALUE = 11, 1451 ACPI_ERST_STALL = 12, 1452 ACPI_ERST_STALL_WHILE_TRUE = 13, 1453 ACPI_ERST_SKIP_NEXT_IF_TRUE = 14, 1454 ACPI_ERST_GOTO = 15, 1455 ACPI_ERST_SET_SRC_ADDRESS_BASE = 16, 1456 ACPI_ERST_SET_DST_ADDRESS_BASE = 17, 1457 ACPI_ERST_MOVE_DATA = 18, 1458 ACPI_ERST_INSTRUCTION_RESERVED = 19 /* 19 and greater are reserved */ 1459 }; 1460 1461 /* Command status return values */ 1462 1463 enum acpi_erst_command_status { 1464 ACPI_ERST_SUCCESS = 0, 1465 ACPI_ERST_NO_SPACE = 1, 1466 ACPI_ERST_NOT_AVAILABLE = 2, 1467 ACPI_ERST_FAILURE = 3, 1468 ACPI_ERST_RECORD_EMPTY = 4, 1469 ACPI_ERST_NOT_FOUND = 5, 1470 ACPI_ERST_STATUS_RESERVED = 6 /* 6 and greater are reserved */ 1471 }; 1472 1473 /* Error Record Serialization Information */ 1474 1475 struct acpi_erst_info { 1476 u16 signature; /* Should be "ER" */ 1477 u8 data[48]; 1478 }; 1479 1480 /******************************************************************************* 1481 * 1482 * FPDT - Firmware Performance Data Table (ACPI 5.0) 1483 * Version 1 1484 * 1485 ******************************************************************************/ 1486 1487 struct acpi_table_fpdt { 1488 struct acpi_table_header header; /* Common ACPI table header */ 1489 }; 1490 1491 /* FPDT subtable header (Performance Record Structure) */ 1492 1493 struct acpi_fpdt_header { 1494 u16 type; 1495 u8 length; 1496 u8 revision; 1497 }; 1498 1499 /* Values for Type field above */ 1500 1501 enum acpi_fpdt_type { 1502 ACPI_FPDT_TYPE_BOOT = 0, 1503 ACPI_FPDT_TYPE_S3PERF = 1 1504 }; 1505 1506 /* 1507 * FPDT subtables 1508 */ 1509 1510 /* 0: Firmware Basic Boot Performance Record */ 1511 1512 struct acpi_fpdt_boot_pointer { 1513 struct acpi_fpdt_header header; 1514 u8 reserved[4]; 1515 u64 address; 1516 }; 1517 1518 /* 1: S3 Performance Table Pointer Record */ 1519 1520 struct acpi_fpdt_s3pt_pointer { 1521 struct acpi_fpdt_header header; 1522 u8 reserved[4]; 1523 u64 address; 1524 }; 1525 1526 /* 1527 * S3PT - S3 Performance Table. This table is pointed to by the 1528 * S3 Pointer Record above. 1529 */ 1530 struct acpi_table_s3pt { 1531 u8 signature[4]; /* "S3PT" */ 1532 u32 length; 1533 }; 1534 1535 /* 1536 * S3PT Subtables (Not part of the actual FPDT) 1537 */ 1538 1539 /* Values for Type field in S3PT header */ 1540 1541 enum acpi_s3pt_type { 1542 ACPI_S3PT_TYPE_RESUME = 0, 1543 ACPI_S3PT_TYPE_SUSPEND = 1, 1544 ACPI_FPDT_BOOT_PERFORMANCE = 2 1545 }; 1546 1547 struct acpi_s3pt_resume { 1548 struct acpi_fpdt_header header; 1549 u32 resume_count; 1550 u64 full_resume; 1551 u64 average_resume; 1552 }; 1553 1554 struct acpi_s3pt_suspend { 1555 struct acpi_fpdt_header header; 1556 u64 suspend_start; 1557 u64 suspend_end; 1558 }; 1559 1560 /* 1561 * FPDT Boot Performance Record (Not part of the actual FPDT) 1562 */ 1563 struct acpi_fpdt_boot { 1564 struct acpi_fpdt_header header; 1565 u8 reserved[4]; 1566 u64 reset_end; 1567 u64 load_start; 1568 u64 startup_start; 1569 u64 exit_services_entry; 1570 u64 exit_services_exit; 1571 }; 1572 1573 /******************************************************************************* 1574 * 1575 * GTDT - Generic Timer Description Table (ACPI 5.1) 1576 * Version 2 1577 * 1578 ******************************************************************************/ 1579 1580 struct acpi_table_gtdt { 1581 struct acpi_table_header header; /* Common ACPI table header */ 1582 u64 counter_block_addresss; 1583 u32 reserved; 1584 u32 secure_el1_interrupt; 1585 u32 secure_el1_flags; 1586 u32 non_secure_el1_interrupt; 1587 u32 non_secure_el1_flags; 1588 u32 virtual_timer_interrupt; 1589 u32 virtual_timer_flags; 1590 u32 non_secure_el2_interrupt; 1591 u32 non_secure_el2_flags; 1592 u64 counter_read_block_address; 1593 u32 platform_timer_count; 1594 u32 platform_timer_offset; 1595 }; 1596 1597 /* Flag Definitions: Timer Block Physical Timers and Virtual timers */ 1598 1599 #define ACPI_GTDT_INTERRUPT_MODE (1) 1600 #define ACPI_GTDT_INTERRUPT_POLARITY (1<<1) 1601 #define ACPI_GTDT_ALWAYS_ON (1<<2) 1602 1603 struct acpi_gtdt_el2 { 1604 u32 virtual_el2_timer_gsiv; 1605 u32 virtual_el2_timer_flags; 1606 }; 1607 1608 /* Common GTDT subtable header */ 1609 1610 struct acpi_gtdt_header { 1611 u8 type; 1612 u16 length; 1613 }; 1614 1615 /* Values for GTDT subtable type above */ 1616 1617 enum acpi_gtdt_type { 1618 ACPI_GTDT_TYPE_TIMER_BLOCK = 0, 1619 ACPI_GTDT_TYPE_WATCHDOG = 1, 1620 ACPI_GTDT_TYPE_RESERVED = 2 /* 2 and greater are reserved */ 1621 }; 1622 1623 /* GTDT Subtables, correspond to Type in struct acpi_gtdt_header */ 1624 1625 /* 0: Generic Timer Block */ 1626 1627 struct acpi_gtdt_timer_block { 1628 struct acpi_gtdt_header header; 1629 u8 reserved; 1630 u64 block_address; 1631 u32 timer_count; 1632 u32 timer_offset; 1633 }; 1634 1635 /* Timer Sub-Structure, one per timer */ 1636 1637 struct acpi_gtdt_timer_entry { 1638 u8 frame_number; 1639 u8 reserved[3]; 1640 u64 base_address; 1641 u64 el0_base_address; 1642 u32 timer_interrupt; 1643 u32 timer_flags; 1644 u32 virtual_timer_interrupt; 1645 u32 virtual_timer_flags; 1646 u32 common_flags; 1647 }; 1648 1649 /* Flag Definitions: timer_flags and virtual_timer_flags above */ 1650 1651 #define ACPI_GTDT_GT_IRQ_MODE (1) 1652 #define ACPI_GTDT_GT_IRQ_POLARITY (1<<1) 1653 1654 /* Flag Definitions: common_flags above */ 1655 1656 #define ACPI_GTDT_GT_IS_SECURE_TIMER (1) 1657 #define ACPI_GTDT_GT_ALWAYS_ON (1<<1) 1658 1659 /* 1: SBSA Generic Watchdog Structure */ 1660 1661 struct acpi_gtdt_watchdog { 1662 struct acpi_gtdt_header header; 1663 u8 reserved; 1664 u64 refresh_frame_address; 1665 u64 control_frame_address; 1666 u32 timer_interrupt; 1667 u32 timer_flags; 1668 }; 1669 1670 /* Flag Definitions: timer_flags above */ 1671 1672 #define ACPI_GTDT_WATCHDOG_IRQ_MODE (1) 1673 #define ACPI_GTDT_WATCHDOG_IRQ_POLARITY (1<<1) 1674 #define ACPI_GTDT_WATCHDOG_SECURE (1<<2) 1675 1676 /******************************************************************************* 1677 * 1678 * HEST - Hardware Error Source Table (ACPI 4.0) 1679 * Version 1 1680 * 1681 ******************************************************************************/ 1682 1683 struct acpi_table_hest { 1684 struct acpi_table_header header; /* Common ACPI table header */ 1685 u32 error_source_count; 1686 }; 1687 1688 /* HEST subtable header */ 1689 1690 struct acpi_hest_header { 1691 u16 type; 1692 u16 source_id; 1693 }; 1694 1695 /* Values for Type field above for subtables */ 1696 1697 enum acpi_hest_types { 1698 ACPI_HEST_TYPE_IA32_CHECK = 0, 1699 ACPI_HEST_TYPE_IA32_CORRECTED_CHECK = 1, 1700 ACPI_HEST_TYPE_IA32_NMI = 2, 1701 ACPI_HEST_TYPE_NOT_USED3 = 3, 1702 ACPI_HEST_TYPE_NOT_USED4 = 4, 1703 ACPI_HEST_TYPE_NOT_USED5 = 5, 1704 ACPI_HEST_TYPE_AER_ROOT_PORT = 6, 1705 ACPI_HEST_TYPE_AER_ENDPOINT = 7, 1706 ACPI_HEST_TYPE_AER_BRIDGE = 8, 1707 ACPI_HEST_TYPE_GENERIC_ERROR = 9, 1708 ACPI_HEST_TYPE_GENERIC_ERROR_V2 = 10, 1709 ACPI_HEST_TYPE_IA32_DEFERRED_CHECK = 11, 1710 ACPI_HEST_TYPE_RESERVED = 12 /* 12 and greater are reserved */ 1711 }; 1712 1713 /* 1714 * HEST substructures contained in subtables 1715 */ 1716 1717 /* 1718 * IA32 Error Bank(s) - Follows the struct acpi_hest_ia_machine_check and 1719 * struct acpi_hest_ia_corrected structures. 1720 */ 1721 struct acpi_hest_ia_error_bank { 1722 u8 bank_number; 1723 u8 clear_status_on_init; 1724 u8 status_format; 1725 u8 reserved; 1726 u32 control_register; 1727 u64 control_data; 1728 u32 status_register; 1729 u32 address_register; 1730 u32 misc_register; 1731 }; 1732 1733 /* Common HEST sub-structure for PCI/AER structures below (6,7,8) */ 1734 1735 struct acpi_hest_aer_common { 1736 u16 reserved1; 1737 u8 flags; 1738 u8 enabled; 1739 u32 records_to_preallocate; 1740 u32 max_sections_per_record; 1741 u32 bus; /* Bus and Segment numbers */ 1742 u16 device; 1743 u16 function; 1744 u16 device_control; 1745 u16 reserved2; 1746 u32 uncorrectable_mask; 1747 u32 uncorrectable_severity; 1748 u32 correctable_mask; 1749 u32 advanced_capabilities; 1750 }; 1751 1752 /* Masks for HEST Flags fields */ 1753 1754 #define ACPI_HEST_FIRMWARE_FIRST (1) 1755 #define ACPI_HEST_GLOBAL (1<<1) 1756 #define ACPI_HEST_GHES_ASSIST (1<<2) 1757 1758 /* 1759 * Macros to access the bus/segment numbers in Bus field above: 1760 * Bus number is encoded in bits 7:0 1761 * Segment number is encoded in bits 23:8 1762 */ 1763 #define ACPI_HEST_BUS(bus) ((bus) & 0xFF) 1764 #define ACPI_HEST_SEGMENT(bus) (((bus) >> 8) & 0xFFFF) 1765 1766 /* Hardware Error Notification */ 1767 1768 struct acpi_hest_notify { 1769 u8 type; 1770 u8 length; 1771 u16 config_write_enable; 1772 u32 poll_interval; 1773 u32 vector; 1774 u32 polling_threshold_value; 1775 u32 polling_threshold_window; 1776 u32 error_threshold_value; 1777 u32 error_threshold_window; 1778 }; 1779 1780 /* Values for Notify Type field above */ 1781 1782 enum acpi_hest_notify_types { 1783 ACPI_HEST_NOTIFY_POLLED = 0, 1784 ACPI_HEST_NOTIFY_EXTERNAL = 1, 1785 ACPI_HEST_NOTIFY_LOCAL = 2, 1786 ACPI_HEST_NOTIFY_SCI = 3, 1787 ACPI_HEST_NOTIFY_NMI = 4, 1788 ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ 1789 ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ 1790 ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ 1791 ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ 1792 ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ 1793 ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ 1794 ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED = 11, /* ACPI 6.2 */ 1795 ACPI_HEST_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */ 1796 }; 1797 1798 /* Values for config_write_enable bitfield above */ 1799 1800 #define ACPI_HEST_TYPE (1) 1801 #define ACPI_HEST_POLL_INTERVAL (1<<1) 1802 #define ACPI_HEST_POLL_THRESHOLD_VALUE (1<<2) 1803 #define ACPI_HEST_POLL_THRESHOLD_WINDOW (1<<3) 1804 #define ACPI_HEST_ERR_THRESHOLD_VALUE (1<<4) 1805 #define ACPI_HEST_ERR_THRESHOLD_WINDOW (1<<5) 1806 1807 /* 1808 * HEST subtables 1809 */ 1810 1811 /* 0: IA32 Machine Check Exception */ 1812 1813 struct acpi_hest_ia_machine_check { 1814 struct acpi_hest_header header; 1815 u16 reserved1; 1816 u8 flags; /* See flags ACPI_HEST_GLOBAL, etc. above */ 1817 u8 enabled; 1818 u32 records_to_preallocate; 1819 u32 max_sections_per_record; 1820 u64 global_capability_data; 1821 u64 global_control_data; 1822 u8 num_hardware_banks; 1823 u8 reserved3[7]; 1824 }; 1825 1826 /* 1: IA32 Corrected Machine Check */ 1827 1828 struct acpi_hest_ia_corrected { 1829 struct acpi_hest_header header; 1830 u16 reserved1; 1831 u8 flags; /* See flags ACPI_HEST_GLOBAL, etc. above */ 1832 u8 enabled; 1833 u32 records_to_preallocate; 1834 u32 max_sections_per_record; 1835 struct acpi_hest_notify notify; 1836 u8 num_hardware_banks; 1837 u8 reserved2[3]; 1838 }; 1839 1840 /* 2: IA32 Non-Maskable Interrupt */ 1841 1842 struct acpi_hest_ia_nmi { 1843 struct acpi_hest_header header; 1844 u32 reserved; 1845 u32 records_to_preallocate; 1846 u32 max_sections_per_record; 1847 u32 max_raw_data_length; 1848 }; 1849 1850 /* 3,4,5: Not used */ 1851 1852 /* 6: PCI Express Root Port AER */ 1853 1854 struct acpi_hest_aer_root { 1855 struct acpi_hest_header header; 1856 struct acpi_hest_aer_common aer; 1857 u32 root_error_command; 1858 }; 1859 1860 /* 7: PCI Express AER (AER Endpoint) */ 1861 1862 struct acpi_hest_aer { 1863 struct acpi_hest_header header; 1864 struct acpi_hest_aer_common aer; 1865 }; 1866 1867 /* 8: PCI Express/PCI-X Bridge AER */ 1868 1869 struct acpi_hest_aer_bridge { 1870 struct acpi_hest_header header; 1871 struct acpi_hest_aer_common aer; 1872 u32 uncorrectable_mask2; 1873 u32 uncorrectable_severity2; 1874 u32 advanced_capabilities2; 1875 }; 1876 1877 /* 9: Generic Hardware Error Source */ 1878 1879 struct acpi_hest_generic { 1880 struct acpi_hest_header header; 1881 u16 related_source_id; 1882 u8 reserved; 1883 u8 enabled; 1884 u32 records_to_preallocate; 1885 u32 max_sections_per_record; 1886 u32 max_raw_data_length; 1887 struct acpi_generic_address error_status_address; 1888 struct acpi_hest_notify notify; 1889 u32 error_block_length; 1890 }; 1891 1892 /* 10: Generic Hardware Error Source, version 2 */ 1893 1894 struct acpi_hest_generic_v2 { 1895 struct acpi_hest_header header; 1896 u16 related_source_id; 1897 u8 reserved; 1898 u8 enabled; 1899 u32 records_to_preallocate; 1900 u32 max_sections_per_record; 1901 u32 max_raw_data_length; 1902 struct acpi_generic_address error_status_address; 1903 struct acpi_hest_notify notify; 1904 u32 error_block_length; 1905 struct acpi_generic_address read_ack_register; 1906 u64 read_ack_preserve; 1907 u64 read_ack_write; 1908 }; 1909 1910 /* Generic Error Status block */ 1911 1912 struct acpi_hest_generic_status { 1913 u32 block_status; 1914 u32 raw_data_offset; 1915 u32 raw_data_length; 1916 u32 data_length; 1917 u32 error_severity; 1918 }; 1919 1920 /* Values for block_status flags above */ 1921 1922 #define ACPI_HEST_UNCORRECTABLE (1) 1923 #define ACPI_HEST_CORRECTABLE (1<<1) 1924 #define ACPI_HEST_MULTIPLE_UNCORRECTABLE (1<<2) 1925 #define ACPI_HEST_MULTIPLE_CORRECTABLE (1<<3) 1926 #define ACPI_HEST_ERROR_ENTRY_COUNT (0xFF<<4) /* 8 bits, error count */ 1927 1928 /* Generic Error Data entry */ 1929 1930 struct acpi_hest_generic_data { 1931 u8 section_type[16]; 1932 u32 error_severity; 1933 u16 revision; 1934 u8 validation_bits; 1935 u8 flags; 1936 u32 error_data_length; 1937 u8 fru_id[16]; 1938 u8 fru_text[20]; 1939 }; 1940 1941 /* Extension for revision 0x0300 */ 1942 1943 struct acpi_hest_generic_data_v300 { 1944 u8 section_type[16]; 1945 u32 error_severity; 1946 u16 revision; 1947 u8 validation_bits; 1948 u8 flags; 1949 u32 error_data_length; 1950 u8 fru_id[16]; 1951 u8 fru_text[20]; 1952 u64 time_stamp; 1953 }; 1954 1955 /* Values for error_severity above */ 1956 1957 #define ACPI_HEST_GEN_ERROR_RECOVERABLE 0 1958 #define ACPI_HEST_GEN_ERROR_FATAL 1 1959 #define ACPI_HEST_GEN_ERROR_CORRECTED 2 1960 #define ACPI_HEST_GEN_ERROR_NONE 3 1961 1962 /* Flags for validation_bits above */ 1963 1964 #define ACPI_HEST_GEN_VALID_FRU_ID (1) 1965 #define ACPI_HEST_GEN_VALID_FRU_STRING (1<<1) 1966 #define ACPI_HEST_GEN_VALID_TIMESTAMP (1<<2) 1967 1968 /* 11: IA32 Deferred Machine Check Exception (ACPI 6.2) */ 1969 1970 struct acpi_hest_ia_deferred_check { 1971 struct acpi_hest_header header; 1972 u16 reserved1; 1973 u8 flags; /* See flags ACPI_HEST_GLOBAL, etc. above */ 1974 u8 enabled; 1975 u32 records_to_preallocate; 1976 u32 max_sections_per_record; 1977 struct acpi_hest_notify notify; 1978 u8 num_hardware_banks; 1979 u8 reserved2[3]; 1980 }; 1981 1982 /******************************************************************************* 1983 * 1984 * HMAT - Heterogeneous Memory Attributes Table (ACPI 6.2) 1985 * Version 1 1986 * 1987 ******************************************************************************/ 1988 1989 struct acpi_table_hmat { 1990 struct acpi_table_header header; /* Common ACPI table header */ 1991 u32 reserved; 1992 }; 1993 1994 /* Values for HMAT structure types */ 1995 1996 enum acpi_hmat_type { 1997 ACPI_HMAT_TYPE_PROXIMITY = 0, /* Memory proximity domain attributes */ 1998 ACPI_HMAT_TYPE_LOCALITY = 1, /* System locality latency and bandwidth information */ 1999 ACPI_HMAT_TYPE_CACHE = 2, /* Memory side cache information */ 2000 ACPI_HMAT_TYPE_RESERVED = 3 /* 3 and greater are reserved */ 2001 }; 2002 2003 struct acpi_hmat_structure { 2004 u16 type; 2005 u16 reserved; 2006 u32 length; 2007 }; 2008 2009 /* 2010 * HMAT Structures, correspond to Type in struct acpi_hmat_structure 2011 */ 2012 2013 /* 0: Memory proximity domain attributes */ 2014 2015 struct acpi_hmat_proximity_domain { 2016 struct acpi_hmat_structure header; 2017 u16 flags; 2018 u16 reserved1; 2019 u32 processor_PD; /* Processor proximity domain */ 2020 u32 memory_PD; /* Memory proximity domain */ 2021 u32 reserved2; 2022 u64 reserved3; 2023 u64 reserved4; 2024 }; 2025 2026 /* Masks for Flags field above */ 2027 2028 #define ACPI_HMAT_PROCESSOR_PD_VALID (1) /* 1: processor_PD field is valid */ 2029 #define ACPI_HMAT_MEMORY_PD_VALID (1<<1) /* 1: memory_PD field is valid */ 2030 #define ACPI_HMAT_RESERVATION_HINT (1<<2) /* 1: Reservation hint */ 2031 2032 /* 1: System locality latency and bandwidth information */ 2033 2034 struct acpi_hmat_locality { 2035 struct acpi_hmat_structure header; 2036 u8 flags; 2037 u8 data_type; 2038 u8 min_transfer_size; 2039 u8 reserved1; 2040 u32 number_of_initiator_Pds; 2041 u32 number_of_target_Pds; 2042 u32 reserved2; 2043 u64 entry_base_unit; 2044 }; 2045 2046 /* Masks for Flags field above */ 2047 2048 #define ACPI_HMAT_MEMORY_HIERARCHY (0x0F) /* Bits 0-3 */ 2049 2050 /* Values for Memory Hierarchy flags */ 2051 2052 #define ACPI_HMAT_MEMORY 0 2053 #define ACPI_HMAT_LAST_LEVEL_CACHE 1 2054 #define ACPI_HMAT_1ST_LEVEL_CACHE 2 2055 #define ACPI_HMAT_2ND_LEVEL_CACHE 3 2056 #define ACPI_HMAT_3RD_LEVEL_CACHE 4 2057 #define ACPI_HMAT_MINIMUM_XFER_SIZE 0x10 /* Bit 4: ACPI 6.4 */ 2058 #define ACPI_HMAT_NON_SEQUENTIAL_XFERS 0x20 /* Bit 5: ACPI 6.4 */ 2059 2060 2061 /* Values for data_type field above */ 2062 2063 #define ACPI_HMAT_ACCESS_LATENCY 0 2064 #define ACPI_HMAT_READ_LATENCY 1 2065 #define ACPI_HMAT_WRITE_LATENCY 2 2066 #define ACPI_HMAT_ACCESS_BANDWIDTH 3 2067 #define ACPI_HMAT_READ_BANDWIDTH 4 2068 #define ACPI_HMAT_WRITE_BANDWIDTH 5 2069 2070 /* 2: Memory side cache information */ 2071 2072 struct acpi_hmat_cache { 2073 struct acpi_hmat_structure header; 2074 u32 memory_PD; 2075 u32 reserved1; 2076 u64 cache_size; 2077 u32 cache_attributes; 2078 u16 address_mode; 2079 u16 number_of_SMBIOShandles; 2080 }; 2081 2082 /* Masks for cache_attributes field above */ 2083 2084 #define ACPI_HMAT_TOTAL_CACHE_LEVEL (0x0000000F) 2085 #define ACPI_HMAT_CACHE_LEVEL (0x000000F0) 2086 #define ACPI_HMAT_CACHE_ASSOCIATIVITY (0x00000F00) 2087 #define ACPI_HMAT_WRITE_POLICY (0x0000F000) 2088 #define ACPI_HMAT_CACHE_LINE_SIZE (0xFFFF0000) 2089 2090 #define ACPI_HMAT_CACHE_MODE_UNKNOWN (0) 2091 #define ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR (1) 2092 2093 /* Values for cache associativity flag */ 2094 2095 #define ACPI_HMAT_CA_NONE (0) 2096 #define ACPI_HMAT_CA_DIRECT_MAPPED (1) 2097 #define ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING (2) 2098 2099 /* Values for write policy flag */ 2100 2101 #define ACPI_HMAT_CP_NONE (0) 2102 #define ACPI_HMAT_CP_WB (1) 2103 #define ACPI_HMAT_CP_WT (2) 2104 2105 /******************************************************************************* 2106 * 2107 * HPET - High Precision Event Timer table 2108 * Version 1 2109 * 2110 * Conforms to "IA-PC HPET (High Precision Event Timers) Specification", 2111 * Version 1.0a, October 2004 2112 * 2113 ******************************************************************************/ 2114 2115 struct acpi_table_hpet { 2116 struct acpi_table_header header; /* Common ACPI table header */ 2117 u32 id; /* Hardware ID of event timer block */ 2118 struct acpi_generic_address address; /* Address of event timer block */ 2119 u8 sequence; /* HPET sequence number */ 2120 u16 minimum_tick; /* Main counter min tick, periodic mode */ 2121 u8 flags; 2122 }; 2123 2124 /* Masks for Flags field above */ 2125 2126 #define ACPI_HPET_PAGE_PROTECT_MASK (3) 2127 2128 /* Values for Page Protect flags */ 2129 2130 enum acpi_hpet_page_protect { 2131 ACPI_HPET_NO_PAGE_PROTECT = 0, 2132 ACPI_HPET_PAGE_PROTECT4 = 1, 2133 ACPI_HPET_PAGE_PROTECT64 = 2 2134 }; 2135 2136 /******************************************************************************* 2137 * 2138 * IBFT - Boot Firmware Table 2139 * Version 1 2140 * 2141 * Conforms to "iSCSI Boot Firmware Table (iBFT) as Defined in ACPI 3.0b 2142 * Specification", Version 1.01, March 1, 2007 2143 * 2144 * Note: It appears that this table is not intended to appear in the RSDT/XSDT. 2145 * Therefore, it is not currently supported by the disassembler. 2146 * 2147 ******************************************************************************/ 2148 2149 struct acpi_table_ibft { 2150 struct acpi_table_header header; /* Common ACPI table header */ 2151 u8 reserved[12]; 2152 }; 2153 2154 /* IBFT common subtable header */ 2155 2156 struct acpi_ibft_header { 2157 u8 type; 2158 u8 version; 2159 u16 length; 2160 u8 index; 2161 u8 flags; 2162 }; 2163 2164 /* Values for Type field above */ 2165 2166 enum acpi_ibft_type { 2167 ACPI_IBFT_TYPE_NOT_USED = 0, 2168 ACPI_IBFT_TYPE_CONTROL = 1, 2169 ACPI_IBFT_TYPE_INITIATOR = 2, 2170 ACPI_IBFT_TYPE_NIC = 3, 2171 ACPI_IBFT_TYPE_TARGET = 4, 2172 ACPI_IBFT_TYPE_EXTENSIONS = 5, 2173 ACPI_IBFT_TYPE_RESERVED = 6 /* 6 and greater are reserved */ 2174 }; 2175 2176 /* IBFT subtables */ 2177 2178 struct acpi_ibft_control { 2179 struct acpi_ibft_header header; 2180 u16 extensions; 2181 u16 initiator_offset; 2182 u16 nic0_offset; 2183 u16 target0_offset; 2184 u16 nic1_offset; 2185 u16 target1_offset; 2186 }; 2187 2188 struct acpi_ibft_initiator { 2189 struct acpi_ibft_header header; 2190 u8 sns_server[16]; 2191 u8 slp_server[16]; 2192 u8 primary_server[16]; 2193 u8 secondary_server[16]; 2194 u16 name_length; 2195 u16 name_offset; 2196 }; 2197 2198 struct acpi_ibft_nic { 2199 struct acpi_ibft_header header; 2200 u8 ip_address[16]; 2201 u8 subnet_mask_prefix; 2202 u8 origin; 2203 u8 gateway[16]; 2204 u8 primary_dns[16]; 2205 u8 secondary_dns[16]; 2206 u8 dhcp[16]; 2207 u16 vlan; 2208 u8 mac_address[6]; 2209 u16 pci_address; 2210 u16 name_length; 2211 u16 name_offset; 2212 }; 2213 2214 struct acpi_ibft_target { 2215 struct acpi_ibft_header header; 2216 u8 target_ip_address[16]; 2217 u16 target_ip_socket; 2218 u8 target_boot_lun[8]; 2219 u8 chap_type; 2220 u8 nic_association; 2221 u16 target_name_length; 2222 u16 target_name_offset; 2223 u16 chap_name_length; 2224 u16 chap_name_offset; 2225 u16 chap_secret_length; 2226 u16 chap_secret_offset; 2227 u16 reverse_chap_name_length; 2228 u16 reverse_chap_name_offset; 2229 u16 reverse_chap_secret_length; 2230 u16 reverse_chap_secret_offset; 2231 }; 2232 2233 /* Reset to default packing */ 2234 2235 #pragma pack() 2236 2237 #endif /* __ACTBL1_H__ */ 2238