1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_RESCTRL_INTERNAL_H
3 #define _ASM_X86_RESCTRL_INTERNAL_H
4
5 #include <linux/resctrl.h>
6
7 #define L3_QOS_CDP_ENABLE 0x01ULL
8
9 #define L2_QOS_CDP_ENABLE 0x01ULL
10
11 #define MBM_CNTR_WIDTH_BASE 24
12
13 #define MBA_IS_LINEAR 0x4
14
15 #define MBM_CNTR_WIDTH_OFFSET_AMD 20
16
17 #define RMID_VAL_ERROR BIT_ULL(63)
18
19 #define RMID_VAL_UNAVAIL BIT_ULL(62)
20
21 /*
22 * With the above fields in use 62 bits remain in MSR_IA32_QM_CTR for
23 * data to be returned. The counter width is discovered from the hardware
24 * as an offset from MBM_CNTR_WIDTH_BASE.
25 */
26 #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE)
27
28 /**
29 * struct arch_mbm_state - values used to compute resctrl_arch_rmid_read()s
30 * return value.
31 * @chunks: Total data moved (multiply by rdt_group.mon_scale to get bytes)
32 * @prev_msr: Value of IA32_QM_CTR last time it was read for the RMID used to
33 * find this struct.
34 */
35 struct arch_mbm_state {
36 u64 chunks;
37 u64 prev_msr;
38 };
39
40 /* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */
41 #define ABMC_ENABLE_BIT 0
42
43 /*
44 * Qos Event Identifiers.
45 */
46 #define ABMC_EXTENDED_EVT_ID BIT(31)
47 #define ABMC_EVT_ID BIT(0)
48
49 /**
50 * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs that share
51 * a resource for a control function
52 * @d_resctrl: Properties exposed to the resctrl file system
53 * @ctrl_val: array of cache or mem ctrl values (indexed by CLOSID)
54 *
55 * Members of this structure are accessed via helpers that provide abstraction.
56 */
57 struct rdt_hw_ctrl_domain {
58 struct rdt_ctrl_domain d_resctrl;
59 u32 *ctrl_val;
60 };
61
62 /**
63 * struct rdt_hw_mon_domain - Arch private attributes of a set of CPUs that share
64 * a resource for a monitor function
65 * @d_resctrl: Properties exposed to the resctrl file system
66 * @arch_mbm_states: Per-event pointer to the MBM event's saved state.
67 * An MBM event's state is an array of struct arch_mbm_state
68 * indexed by RMID on x86.
69 *
70 * Members of this structure are accessed via helpers that provide abstraction.
71 */
72 struct rdt_hw_mon_domain {
73 struct rdt_mon_domain d_resctrl;
74 struct arch_mbm_state *arch_mbm_states[QOS_NUM_L3_MBM_EVENTS];
75 };
76
resctrl_to_arch_ctrl_dom(struct rdt_ctrl_domain * r)77 static inline struct rdt_hw_ctrl_domain *resctrl_to_arch_ctrl_dom(struct rdt_ctrl_domain *r)
78 {
79 return container_of(r, struct rdt_hw_ctrl_domain, d_resctrl);
80 }
81
resctrl_to_arch_mon_dom(struct rdt_mon_domain * r)82 static inline struct rdt_hw_mon_domain *resctrl_to_arch_mon_dom(struct rdt_mon_domain *r)
83 {
84 return container_of(r, struct rdt_hw_mon_domain, d_resctrl);
85 }
86
87 /**
88 * struct msr_param - set a range of MSRs from a domain
89 * @res: The resource to use
90 * @dom: The domain to update
91 * @low: Beginning index from base MSR
92 * @high: End index
93 */
94 struct msr_param {
95 struct rdt_resource *res;
96 struct rdt_ctrl_domain *dom;
97 u32 low;
98 u32 high;
99 };
100
101 /**
102 * struct rdt_hw_resource - arch private attributes of a resctrl resource
103 * @r_resctrl: Attributes of the resource used directly by resctrl.
104 * @num_closid: Maximum number of closid this hardware can support,
105 * regardless of CDP. This is exposed via
106 * resctrl_arch_get_num_closid() to avoid confusion
107 * with struct resctrl_schema's property of the same name,
108 * which has been corrected for features like CDP.
109 * @msr_base: Base MSR address for CBMs
110 * @msr_update: Function pointer to update QOS MSRs
111 * @mon_scale: cqm counter * mon_scale = occupancy in bytes
112 * @mbm_width: Monitor width, to detect and correct for overflow.
113 * @cdp_enabled: CDP state of this resource
114 * @mbm_cntr_assign_enabled: ABMC feature is enabled
115 *
116 * Members of this structure are either private to the architecture
117 * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g.
118 * msr_update and msr_base.
119 */
120 struct rdt_hw_resource {
121 struct rdt_resource r_resctrl;
122 u32 num_closid;
123 unsigned int msr_base;
124 void (*msr_update)(struct msr_param *m);
125 unsigned int mon_scale;
126 unsigned int mbm_width;
127 bool cdp_enabled;
128 bool mbm_cntr_assign_enabled;
129 };
130
resctrl_to_arch_res(struct rdt_resource * r)131 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r)
132 {
133 return container_of(r, struct rdt_hw_resource, r_resctrl);
134 }
135
136 extern struct rdt_hw_resource rdt_resources_all[];
137
138 void arch_mon_domain_online(struct rdt_resource *r, struct rdt_mon_domain *d);
139
140 /* CPUID.(EAX=10H, ECX=ResID=1).EAX */
141 union cpuid_0x10_1_eax {
142 struct {
143 unsigned int cbm_len:5;
144 } split;
145 unsigned int full;
146 };
147
148 /* CPUID.(EAX=10H, ECX=ResID=3).EAX */
149 union cpuid_0x10_3_eax {
150 struct {
151 unsigned int max_delay:12;
152 } split;
153 unsigned int full;
154 };
155
156 /* CPUID.(EAX=10H, ECX=ResID).ECX */
157 union cpuid_0x10_x_ecx {
158 struct {
159 unsigned int reserved:3;
160 unsigned int noncont:1;
161 } split;
162 unsigned int full;
163 };
164
165 /* CPUID.(EAX=10H, ECX=ResID).EDX */
166 union cpuid_0x10_x_edx {
167 struct {
168 unsigned int cos_max:16;
169 } split;
170 unsigned int full;
171 };
172
173 /*
174 * ABMC counters are configured by writing to MSR_IA32_L3_QOS_ABMC_CFG.
175 *
176 * @bw_type : Event configuration that represents the memory
177 * transactions being tracked by the @cntr_id.
178 * @bw_src : Bandwidth source (RMID or CLOSID).
179 * @reserved1 : Reserved.
180 * @is_clos : @bw_src field is a CLOSID (not an RMID).
181 * @cntr_id : Counter identifier.
182 * @reserved : Reserved.
183 * @cntr_en : Counting enable bit.
184 * @cfg_en : Configuration enable bit.
185 *
186 * Configuration and counting:
187 * Counter can be configured across multiple writes to MSR. Configuration
188 * is applied only when @cfg_en = 1. Counter @cntr_id is reset when the
189 * configuration is applied.
190 * @cfg_en = 1, @cntr_en = 0 : Apply @cntr_id configuration but do not
191 * count events.
192 * @cfg_en = 1, @cntr_en = 1 : Apply @cntr_id configuration and start
193 * counting events.
194 */
195 union l3_qos_abmc_cfg {
196 struct {
197 unsigned long bw_type :32,
198 bw_src :12,
199 reserved1: 3,
200 is_clos : 1,
201 cntr_id : 5,
202 reserved : 9,
203 cntr_en : 1,
204 cfg_en : 1;
205 } split;
206 unsigned long full;
207 };
208
209 void rdt_ctrl_update(void *arg);
210
211 int rdt_get_mon_l3_config(struct rdt_resource *r);
212
213 bool rdt_cpu_has(int flag);
214
215 void __init intel_rdt_mbm_apply_quirk(void);
216
217 void rdt_domain_reconfigure_cdp(struct rdt_resource *r);
218 void resctrl_arch_mbm_cntr_assign_set_one(struct rdt_resource *r);
219
220 #endif /* _ASM_X86_RESCTRL_INTERNAL_H */
221