xref: /linux/include/linux/mfd/abx500/ab8500.h (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) ST-Ericsson SA 2010
4  *
5  * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6  */
7 #ifndef MFD_AB8500_H
8 #define MFD_AB8500_H
9 
10 #include <linux/atomic.h>
11 #include <linux/mutex.h>
12 #include <linux/irqdomain.h>
13 
14 struct device;
15 
16 /*
17  * AB IC versions
18  *
19  * AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
20  * non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
21  * print of version string.
22  */
23 enum ab8500_version {
24 	AB8500_VERSION_AB8500 = 0x0,
25 	AB8500_VERSION_AB8505 = 0x1,
26 	AB8500_VERSION_AB9540 = 0x2,
27 	AB8500_VERSION_AB8540 = 0x4,
28 	AB8500_VERSION_UNDEFINED,
29 };
30 
31 /* AB8500 CIDs*/
32 #define AB8500_CUTEARLY	0x00
33 #define AB8500_CUT1P0	0x10
34 #define AB8500_CUT1P1	0x11
35 #define AB8500_CUT1P2	0x12 /* Only valid for AB8540 */
36 #define AB8500_CUT2P0	0x20
37 #define AB8500_CUT3P0	0x30
38 #define AB8500_CUT3P3	0x33
39 
40 /*
41  * AB8500 bank addresses
42  */
43 #define AB8500_M_FSM_RANK	0x0
44 #define AB8500_SYS_CTRL1_BLOCK	0x1
45 #define AB8500_SYS_CTRL2_BLOCK	0x2
46 #define AB8500_REGU_CTRL1	0x3
47 #define AB8500_REGU_CTRL2	0x4
48 #define AB8500_USB		0x5
49 #define AB8500_TVOUT		0x6
50 #define AB8500_DBI		0x7
51 #define AB8500_ECI_AV_ACC	0x8
52 #define AB8500_RESERVED		0x9
53 #define AB8500_GPADC		0xA
54 #define AB8500_CHARGER		0xB
55 #define AB8500_GAS_GAUGE	0xC
56 #define AB8500_AUDIO		0xD
57 #define AB8500_INTERRUPT	0xE
58 #define AB8500_RTC		0xF
59 #define AB8500_MISC		0x10
60 #define AB8500_DEVELOPMENT	0x11
61 #define AB8500_DEBUG		0x12
62 #define AB8500_PROD_TEST	0x13
63 #define AB8500_STE_TEST		0x14
64 #define AB8500_OTP_EMUL		0x15
65 
66 #define AB8500_DEBUG_FIELD_LAST	0x16
67 
68 /*
69  * Interrupts
70  * Values used to index into array ab8500_irq_regoffset[] defined in
71  * drivers/mdf/ab8500-core.c
72  */
73 /* Definitions for AB8500, AB9540 and AB8540 */
74 /* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
75 #define AB8500_INT_MAIN_EXT_CH_NOT_OK	0 /* not 8505/9540 */
76 #define AB8500_INT_UN_PLUG_TV_DET	1 /* not 8505/9540/8540 */
77 #define AB8500_INT_PLUG_TV_DET		2 /* not 8505/9540/8540 */
78 #define AB8500_INT_TEMP_WARM		3
79 #define AB8500_INT_PON_KEY2DB_F		4
80 #define AB8500_INT_PON_KEY2DB_R		5
81 #define AB8500_INT_PON_KEY1DB_F		6
82 #define AB8500_INT_PON_KEY1DB_R		7
83 /* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
84 #define AB8500_INT_BATT_OVV		8
85 #define AB8500_INT_MAIN_CH_UNPLUG_DET	10 /* not 8505/8540 */
86 #define AB8500_INT_MAIN_CH_PLUG_DET	11 /* not 8505/8540 */
87 #define AB8500_INT_VBUS_DET_F		14
88 #define AB8500_INT_VBUS_DET_R		15
89 /* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
90 #define AB8500_INT_VBUS_CH_DROP_END	16
91 #define AB8500_INT_RTC_60S		17
92 #define AB8500_INT_RTC_ALARM		18
93 #define AB8540_INT_BIF_INT		19
94 #define AB8500_INT_BAT_CTRL_INDB	20
95 #define AB8500_INT_CH_WD_EXP		21
96 #define AB8500_INT_VBUS_OVV		22
97 #define AB8500_INT_MAIN_CH_DROP_END	23 /* not 8505/9540/8540 */
98 /* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
99 #define AB8500_INT_CCN_CONV_ACC		24
100 #define AB8500_INT_INT_AUD		25
101 #define AB8500_INT_CCEOC		26
102 #define AB8500_INT_CC_INT_CALIB		27
103 #define AB8500_INT_LOW_BAT_F		28
104 #define AB8500_INT_LOW_BAT_R		29
105 #define AB8500_INT_BUP_CHG_NOT_OK	30
106 #define AB8500_INT_BUP_CHG_OK		31
107 /* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
108 #define AB8500_INT_GP_HW_ADC_CONV_END	32 /* not 8505/8540 */
109 #define AB8500_INT_ACC_DETECT_1DB_F	33
110 #define AB8500_INT_ACC_DETECT_1DB_R	34
111 #define AB8500_INT_ACC_DETECT_22DB_F	35
112 #define AB8500_INT_ACC_DETECT_22DB_R	36
113 #define AB8500_INT_ACC_DETECT_21DB_F	37
114 #define AB8500_INT_ACC_DETECT_21DB_R	38
115 #define AB8500_INT_GP_SW_ADC_CONV_END	39
116 /* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
117 #define AB8500_INT_GPIO6R		40 /* not 8505/9540/8540 */
118 #define AB8500_INT_GPIO7R		41 /* not 8505/9540/8540 */
119 #define AB8500_INT_GPIO8R		42 /* not 8505/9540/8540 */
120 #define AB8500_INT_GPIO9R		43 /* not 8505/9540/8540 */
121 #define AB8500_INT_GPIO10R		44 /* not 8540 */
122 #define AB8500_INT_GPIO11R		45 /* not 8540 */
123 #define AB8500_INT_GPIO12R		46 /* not 8505/8540 */
124 #define AB8500_INT_GPIO13R		47 /* not 8540 */
125 /* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
126 #define AB8500_INT_GPIO24R		48 /* not 8505/8540 */
127 #define AB8500_INT_GPIO25R		49 /* not 8505/8540 */
128 #define AB8500_INT_GPIO36R		50 /* not 8505/9540/8540 */
129 #define AB8500_INT_GPIO37R		51 /* not 8505/9540/8540 */
130 #define AB8500_INT_GPIO38R		52 /* not 8505/9540/8540 */
131 #define AB8500_INT_GPIO39R		53 /* not 8505/9540/8540 */
132 #define AB8500_INT_GPIO40R		54 /* not 8540 */
133 #define AB8500_INT_GPIO41R		55 /* not 8540 */
134 /* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
135 #define AB8500_INT_GPIO6F		56 /* not 8505/9540 */
136 #define AB8500_INT_GPIO7F		57 /* not 8505/9540 */
137 #define AB8500_INT_GPIO8F		58 /* not 8505/9540 */
138 #define AB8500_INT_GPIO9F		59 /* not 8505/9540 */
139 #define AB8500_INT_GPIO10F		60
140 #define AB8500_INT_GPIO11F		61
141 #define AB8500_INT_GPIO12F		62 /* not 8505 */
142 #define AB8500_INT_GPIO13F		63
143 /* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
144 #define AB8500_INT_GPIO24F		64 /* not 8505/8540 */
145 #define AB8500_INT_GPIO25F		65 /* not 8505/8540 */
146 #define AB8500_INT_GPIO36F		66 /* not 8505/9540/8540 */
147 #define AB8500_INT_GPIO37F		67 /* not 8505/9540/8540 */
148 #define AB8500_INT_GPIO38F		68 /* not 8505/9540/8540 */
149 #define AB8500_INT_GPIO39F		69 /* not 8505/9540/8540 */
150 #define AB8500_INT_GPIO40F		70 /* not 8540 */
151 #define AB8500_INT_GPIO41F		71 /* not 8540 */
152 /* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
153 #define AB8500_INT_ADP_SOURCE_ERROR	72
154 #define AB8500_INT_ADP_SINK_ERROR	73
155 #define AB8500_INT_ADP_PROBE_PLUG	74
156 #define AB8500_INT_ADP_PROBE_UNPLUG	75
157 #define AB8500_INT_ADP_SENSE_OFF	76
158 #define AB8500_INT_USB_PHY_POWER_ERR	78
159 #define AB8500_INT_USB_LINK_STATUS	79
160 /* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
161 #define AB8500_INT_BTEMP_LOW		80
162 #define AB8500_INT_BTEMP_LOW_MEDIUM	81
163 #define AB8500_INT_BTEMP_MEDIUM_HIGH	82
164 #define AB8500_INT_BTEMP_HIGH		83
165 /* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
166 #define AB8500_INT_SRP_DETECT		88
167 #define AB8500_INT_USB_CHARGER_NOT_OKR	89
168 #define AB8500_INT_ID_WAKEUP_R		90
169 #define AB8500_INT_ID_DET_PLUGR         91 /* 8505/9540 cut2.0 */
170 #define AB8500_INT_ID_DET_R1R		92
171 #define AB8500_INT_ID_DET_R2R		93
172 #define AB8500_INT_ID_DET_R3R		94
173 #define AB8500_INT_ID_DET_R4R		95
174 /* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
175 #define AB8500_INT_ID_WAKEUP_F		96 /* not 8505/9540 */
176 #define AB8500_INT_ID_DET_PLUGF		97 /* 8505/9540 cut2.0 */
177 #define AB8500_INT_ID_DET_R1F		98 /* not 8505/9540 */
178 #define AB8500_INT_ID_DET_R2F		99 /* not 8505/9540 */
179 #define AB8500_INT_ID_DET_R3F		100 /* not 8505/9540 */
180 #define AB8500_INT_ID_DET_R4F		101 /* not 8505/9540 */
181 #define AB8500_INT_CHAUTORESTARTAFTSEC	102 /* not 8505/9540 */
182 #define AB8500_INT_CHSTOPBYSEC		103
183 /* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
184 #define AB8500_INT_USB_CH_TH_PROT_F	104
185 #define AB8500_INT_USB_CH_TH_PROT_R	105
186 #define AB8500_INT_MAIN_CH_TH_PROT_F	106 /* not 8505/9540 */
187 #define AB8500_INT_MAIN_CH_TH_PROT_R	107 /* not 8505/9540 */
188 #define AB8500_INT_CHCURLIMNOHSCHIRP	109
189 #define AB8500_INT_CHCURLIMHSCHIRP	110
190 #define AB8500_INT_XTAL32K_KO		111
191 
192 /* Definitions for AB9540 / AB8505 */
193 /* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
194 #define AB9540_INT_GPIO50R		113 /* not 8540 */
195 #define AB9540_INT_GPIO51R		114 /* not 8505/8540 */
196 #define AB9540_INT_GPIO52R		115 /* not 8540 */
197 #define AB9540_INT_GPIO53R		116 /* not 8540 */
198 #define AB9540_INT_GPIO54R		117 /* not 8505/8540 */
199 #define AB9540_INT_IEXT_CH_RF_BFN_R	118
200 /* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
201 #define AB9540_INT_GPIO50F		121 /* not 8540 */
202 #define AB9540_INT_GPIO51F		122 /* not 8505/8540 */
203 #define AB9540_INT_GPIO52F		123 /* not 8540 */
204 #define AB9540_INT_GPIO53F		124 /* not 8540 */
205 #define AB9540_INT_GPIO54F		125 /* not 8505/8540 */
206 #define AB9540_INT_IEXT_CH_RF_BFN_F	126
207 /* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */
208 #define AB8505_INT_KEYSTUCK		128
209 #define AB8505_INT_IKR			129
210 #define AB8505_INT_IKP			130
211 #define AB8505_INT_KP			131
212 #define AB8505_INT_KEYDEGLITCH		132
213 #define AB8505_INT_MODPWRSTATUSF	134
214 #define AB8505_INT_MODPWRSTATUSR	135
215 /* ab8500_irq_regoffset[17] -> IT[Source|Latch|Mask]6 */
216 #define AB8500_INT_HOOK_DET_NEG_F	138
217 #define AB8500_INT_HOOK_DET_NEG_R	139
218 #define AB8500_INT_HOOK_DET_POS_F	140
219 #define AB8500_INT_HOOK_DET_POS_R	141
220 #define AB8500_INT_PLUG_DET_COMP_F	142
221 #define AB8500_INT_PLUG_DET_COMP_R	143
222 /* ab8500_irq_regoffset[18] -> IT[Source|Latch|Mask]23 */
223 #define AB8505_INT_COLL			144
224 #define AB8505_INT_RESERR		145
225 #define AB8505_INT_FRAERR		146
226 #define AB8505_INT_COMERR		147
227 #define AB8505_INT_SPDSET		148
228 #define AB8505_INT_DSENT		149
229 #define AB8505_INT_DREC			150
230 #define AB8505_INT_ACC_INT		151
231 /* ab8500_irq_regoffset[19] -> IT[Source|Latch|Mask]24 */
232 #define AB8505_INT_NOPINT		152
233 /* ab8540_irq_regoffset[20] -> IT[Source|Latch|Mask]26 */
234 #define AB8540_INT_IDPLUGDETCOMPF	160
235 #define AB8540_INT_IDPLUGDETCOMPR	161
236 #define AB8540_INT_FMDETCOMPLOF		162
237 #define AB8540_INT_FMDETCOMPLOR		163
238 #define AB8540_INT_FMDETCOMPHIF		164
239 #define AB8540_INT_FMDETCOMPHIR		165
240 #define AB8540_INT_ID5VDETCOMPF		166
241 #define AB8540_INT_ID5VDETCOMPR		167
242 /* ab8540_irq_regoffset[21] -> IT[Source|Latch|Mask]27 */
243 #define AB8540_INT_GPIO43F		168
244 #define AB8540_INT_GPIO43R		169
245 #define AB8540_INT_GPIO44F		170
246 #define AB8540_INT_GPIO44R		171
247 #define AB8540_INT_KEYPOSDETCOMPF	172
248 #define AB8540_INT_KEYPOSDETCOMPR	173
249 #define AB8540_INT_KEYNEGDETCOMPF	174
250 #define AB8540_INT_KEYNEGDETCOMPR	175
251 /* ab8540_irq_regoffset[22] -> IT[Source|Latch|Mask]28 */
252 #define AB8540_INT_GPIO1VBATF		176
253 #define AB8540_INT_GPIO1VBATR		177
254 #define AB8540_INT_GPIO2VBATF		178
255 #define AB8540_INT_GPIO2VBATR		179
256 #define AB8540_INT_GPIO3VBATF		180
257 #define AB8540_INT_GPIO3VBATR		181
258 #define AB8540_INT_GPIO4VBATF		182
259 #define AB8540_INT_GPIO4VBATR		183
260 /* ab8540_irq_regoffset[23] -> IT[Source|Latch|Mask]29 */
261 #define AB8540_INT_SYSCLKREQ2F		184
262 #define AB8540_INT_SYSCLKREQ2R		185
263 #define AB8540_INT_SYSCLKREQ3F		186
264 #define AB8540_INT_SYSCLKREQ3R		187
265 #define AB8540_INT_SYSCLKREQ4F		188
266 #define AB8540_INT_SYSCLKREQ4R		189
267 #define AB8540_INT_SYSCLKREQ5F		190
268 #define AB8540_INT_SYSCLKREQ5R		191
269 /* ab8540_irq_regoffset[24] -> IT[Source|Latch|Mask]30 */
270 #define AB8540_INT_PWMOUT1F		192
271 #define AB8540_INT_PWMOUT1R		193
272 #define AB8540_INT_PWMCTRL0F		194
273 #define AB8540_INT_PWMCTRL0R		195
274 #define AB8540_INT_PWMCTRL1F		196
275 #define AB8540_INT_PWMCTRL1R		197
276 #define AB8540_INT_SYSCLKREQ6F		198
277 #define AB8540_INT_SYSCLKREQ6R		199
278 /* ab8540_irq_regoffset[25] -> IT[Source|Latch|Mask]31 */
279 #define AB8540_INT_PWMEXTVIBRA1F	200
280 #define AB8540_INT_PWMEXTVIBRA1R	201
281 #define AB8540_INT_PWMEXTVIBRA2F	202
282 #define AB8540_INT_PWMEXTVIBRA2R	203
283 #define AB8540_INT_PWMOUT2F		204
284 #define AB8540_INT_PWMOUT2R		205
285 #define AB8540_INT_PWMOUT3F		206
286 #define AB8540_INT_PWMOUT3R		207
287 /* ab8540_irq_regoffset[26] -> IT[Source|Latch|Mask]32 */
288 #define AB8540_INT_ADDATA2F		208
289 #define AB8540_INT_ADDATA2R		209
290 #define AB8540_INT_DADATA2F		210
291 #define AB8540_INT_DADATA2R		211
292 #define AB8540_INT_FSYNC2F		212
293 #define AB8540_INT_FSYNC2R		213
294 #define AB8540_INT_BITCLK2F		214
295 #define AB8540_INT_BITCLK2R		215
296 /* ab8540_irq_regoffset[27] -> IT[Source|Latch|Mask]33 */
297 #define AB8540_INT_RTC_1S		216
298 
299 /*
300  * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
301  * entire platform. This is a "compile time" constant so this must be set to
302  * the largest possible value that may be encountered with different AB SOCs.
303  * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
304  * which is larger.
305  */
306 #define AB8500_NR_IRQS			112
307 #define AB8505_NR_IRQS			153
308 #define AB9540_NR_IRQS			153
309 #define AB8540_NR_IRQS			216
310 /* This is set to the roof of any AB8500 chip variant IRQ counts */
311 #define AB8500_MAX_NR_IRQS		AB8540_NR_IRQS
312 
313 #define AB8500_NUM_IRQ_REGS		14
314 #define AB9540_NUM_IRQ_REGS		20
315 #define AB8540_NUM_IRQ_REGS		27
316 
317 /* Turn On Status Event */
318 #define AB8500_POR_ON_VBAT		0x01
319 #define AB8500_POW_KEY_1_ON		0x02
320 #define AB8500_POW_KEY_2_ON		0x04
321 #define AB8500_RTC_ALARM		0x08
322 #define AB8500_MAIN_CH_DET		0x10
323 #define AB8500_VBUS_DET			0x20
324 #define AB8500_USB_ID_DET		0x40
325 
326 /**
327  * struct ab8500 - ab8500 internal structure
328  * @dev: parent device
329  * @lock: read/write operations lock
330  * @irq_lock: genirq bus lock
331  * @transfer_ongoing: 0 if no transfer ongoing
332  * @irq: irq line
333  * @irq_domain: irq domain
334  * @version: chip version id (e.g. ab8500 or ab9540)
335  * @chip_id: chip revision id
336  * @write: register write
337  * @write_masked: masked register write
338  * @read: register read
339  * @rx_buf: rx buf for SPI
340  * @tx_buf: tx buf for SPI
341  * @mask: cache of IRQ regs for bus lock
342  * @oldmask: cache of previous IRQ regs for bus lock
343  * @mask_size: Actual number of valid entries in mask[], oldmask[] and
344  * irq_reg_offset
345  * @irq_reg_offset: Array of offsets into IRQ registers
346  */
347 struct ab8500 {
348 	struct device	*dev;
349 	struct mutex	lock;
350 	struct mutex	irq_lock;
351 	atomic_t	transfer_ongoing;
352 	int		irq;
353 	struct irq_domain  *domain;
354 	enum ab8500_version version;
355 	u8		chip_id;
356 
357 	int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
358 	int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
359 	int (*read)(struct ab8500 *ab8500, u16 addr);
360 
361 	unsigned long	tx_buf[4];
362 	unsigned long	rx_buf[4];
363 
364 	u8 *mask;
365 	u8 *oldmask;
366 	int mask_size;
367 	const int *irq_reg_offset;
368 	int it_latchhier_num;
369 };
370 
371 struct ab8500_codec_platform_data;
372 struct ab8500_sysctrl_platform_data;
373 
374 /**
375  * struct ab8500_platform_data - AB8500 platform data
376  * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
377  * @init: board-specific initialization after detection of ab8500
378  */
379 struct ab8500_platform_data {
380 	void (*init) (struct ab8500 *);
381 	struct ab8500_codec_platform_data *codec;
382 	struct ab8500_sysctrl_platform_data *sysctrl;
383 };
384 
385 extern int ab8500_suspend(struct ab8500 *ab8500);
386 
is_ab8500(struct ab8500 * ab)387 static inline int is_ab8500(struct ab8500 *ab)
388 {
389 	return ab->version == AB8500_VERSION_AB8500;
390 }
391 
is_ab8505(struct ab8500 * ab)392 static inline int is_ab8505(struct ab8500 *ab)
393 {
394 	return ab->version == AB8500_VERSION_AB8505;
395 }
396 
is_ab9540(struct ab8500 * ab)397 static inline int is_ab9540(struct ab8500 *ab)
398 {
399 	return ab->version == AB8500_VERSION_AB9540;
400 }
401 
is_ab8540(struct ab8500 * ab)402 static inline int is_ab8540(struct ab8500 *ab)
403 {
404 	return ab->version == AB8500_VERSION_AB8540;
405 }
406 
407 /* exclude also ab8505, ab9540... */
is_ab8500_1p0_or_earlier(struct ab8500 * ab)408 static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
409 {
410 	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
411 }
412 
413 /* exclude also ab8505, ab9540... */
is_ab8500_1p1_or_earlier(struct ab8500 * ab)414 static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
415 {
416 	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
417 }
418 
419 /* exclude also ab8505, ab9540... */
is_ab8500_2p0_or_earlier(struct ab8500 * ab)420 static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
421 {
422 	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
423 }
424 
is_ab8500_3p3_or_earlier(struct ab8500 * ab)425 static inline int is_ab8500_3p3_or_earlier(struct ab8500 *ab)
426 {
427 	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT3P3));
428 }
429 
430 /* exclude also ab8505, ab9540... */
is_ab8500_2p0(struct ab8500 * ab)431 static inline int is_ab8500_2p0(struct ab8500 *ab)
432 {
433 	return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
434 }
435 
is_ab8505_1p0_or_earlier(struct ab8500 * ab)436 static inline int is_ab8505_1p0_or_earlier(struct ab8500 *ab)
437 {
438 	return (is_ab8505(ab) && (ab->chip_id <= AB8500_CUT1P0));
439 }
440 
is_ab8505_2p0(struct ab8500 * ab)441 static inline int is_ab8505_2p0(struct ab8500 *ab)
442 {
443 	return (is_ab8505(ab) && (ab->chip_id == AB8500_CUT2P0));
444 }
445 
is_ab9540_1p0_or_earlier(struct ab8500 * ab)446 static inline int is_ab9540_1p0_or_earlier(struct ab8500 *ab)
447 {
448 	return (is_ab9540(ab) && (ab->chip_id <= AB8500_CUT1P0));
449 }
450 
is_ab9540_2p0(struct ab8500 * ab)451 static inline int is_ab9540_2p0(struct ab8500 *ab)
452 {
453 	return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT2P0));
454 }
455 
456 /*
457  * Be careful, the marketing name for this chip is 2.1
458  * but the value read from the chip is 3.0 (0x30)
459  */
is_ab9540_3p0(struct ab8500 * ab)460 static inline int is_ab9540_3p0(struct ab8500 *ab)
461 {
462 	return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT3P0));
463 }
464 
is_ab8540_1p0_or_earlier(struct ab8500 * ab)465 static inline int is_ab8540_1p0_or_earlier(struct ab8500 *ab)
466 {
467 	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P0);
468 }
469 
is_ab8540_1p1_or_earlier(struct ab8500 * ab)470 static inline int is_ab8540_1p1_or_earlier(struct ab8500 *ab)
471 {
472 	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P1);
473 }
474 
is_ab8540_1p2_or_earlier(struct ab8500 * ab)475 static inline int is_ab8540_1p2_or_earlier(struct ab8500 *ab)
476 {
477 	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P2);
478 }
479 
is_ab8540_2p0_or_earlier(struct ab8500 * ab)480 static inline int is_ab8540_2p0_or_earlier(struct ab8500 *ab)
481 {
482 	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT2P0);
483 }
484 
is_ab8540_2p0(struct ab8500 * ab)485 static inline int is_ab8540_2p0(struct ab8500 *ab)
486 {
487 	return is_ab8540(ab) && (ab->chip_id == AB8500_CUT2P0);
488 }
489 
is_ab8505_2p0_earlier(struct ab8500 * ab)490 static inline int is_ab8505_2p0_earlier(struct ab8500 *ab)
491 {
492 	return (is_ab8505(ab) && (ab->chip_id < AB8500_CUT2P0));
493 }
494 
is_ab9540_2p0_or_earlier(struct ab8500 * ab)495 static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab)
496 {
497 	return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0));
498 }
499 
500 void ab8500_override_turn_on_stat(u8 mask, u8 set);
501 
ab8500_dump_all_banks(struct device * dev)502 static inline void ab8500_dump_all_banks(struct device *dev) {}
ab8500_debug_register_interrupt(int line)503 static inline void ab8500_debug_register_interrupt(int line) {}
504 
505 #endif /* MFD_AB8500_H */
506