Lines Matching refs:msr
37 static bool is_write_only_msr(uint32_t msr) in is_write_only_msr() argument
39 return msr == HV_X64_MSR_EOI; in is_write_only_msr()
42 static void guest_msr(struct msr_data *msr) in guest_msr() argument
47 GUEST_ASSERT(msr->idx); in guest_msr()
49 if (msr->write) in guest_msr()
50 vector = wrmsr_safe(msr->idx, msr->write_val); in guest_msr()
52 if (!vector && (!msr->write || !is_write_only_msr(msr->idx))) in guest_msr()
53 vector = rdmsr_safe(msr->idx, &msr_val); in guest_msr()
55 if (msr->fault_expected) in guest_msr()
58 msr->write ? "WR" : "RD", msr->idx, vector); in guest_msr()
62 msr->write ? "WR" : "RD", msr->idx, vector); in guest_msr()
64 if (vector || is_write_only_msr(msr->idx)) in guest_msr()
67 if (msr->write) in guest_msr()
70 msr->idx, msr->write_val, msr_val); in guest_msr()
73 if (msr->idx == HV_X64_MSR_TSC_INVARIANT_CONTROL) { in guest_msr()
138 struct msr_data *msr; in guest_test_msrs_access() local
146 msr = addr_gva2hva(vm, msr_gva); in guest_test_msrs_access()
168 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
169 msr->write = false; in guest_test_msrs_access()
170 msr->fault_expected = true; in guest_test_msrs_access()
173 msr->idx = HV_X64_MSR_HYPERCALL; in guest_test_msrs_access()
174 msr->write = false; in guest_test_msrs_access()
175 msr->fault_expected = true; in guest_test_msrs_access()
183 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
184 msr->write = true; in guest_test_msrs_access()
185 msr->write_val = HYPERV_LINUX_OS_ID; in guest_test_msrs_access()
186 msr->fault_expected = false; in guest_test_msrs_access()
189 msr->idx = HV_X64_MSR_GUEST_OS_ID; in guest_test_msrs_access()
190 msr->write = false; in guest_test_msrs_access()
191 msr->fault_expected = false; in guest_test_msrs_access()
194 msr->idx = HV_X64_MSR_HYPERCALL; in guest_test_msrs_access()
195 msr->write = false; in guest_test_msrs_access()
196 msr->fault_expected = false; in guest_test_msrs_access()
200 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
201 msr->write = false; in guest_test_msrs_access()
202 msr->fault_expected = true; in guest_test_msrs_access()
206 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
207 msr->write = false; in guest_test_msrs_access()
208 msr->fault_expected = false; in guest_test_msrs_access()
212 msr->idx = HV_X64_MSR_VP_RUNTIME; in guest_test_msrs_access()
213 msr->write = true; in guest_test_msrs_access()
214 msr->write_val = 1; in guest_test_msrs_access()
215 msr->fault_expected = true; in guest_test_msrs_access()
219 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
220 msr->write = false; in guest_test_msrs_access()
221 msr->fault_expected = true; in guest_test_msrs_access()
225 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
226 msr->write = false; in guest_test_msrs_access()
227 msr->fault_expected = false; in guest_test_msrs_access()
231 msr->idx = HV_X64_MSR_TIME_REF_COUNT; in guest_test_msrs_access()
232 msr->write = true; in guest_test_msrs_access()
233 msr->write_val = 1; in guest_test_msrs_access()
234 msr->fault_expected = true; in guest_test_msrs_access()
238 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
239 msr->write = false; in guest_test_msrs_access()
240 msr->fault_expected = true; in guest_test_msrs_access()
244 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
245 msr->write = false; in guest_test_msrs_access()
246 msr->fault_expected = false; in guest_test_msrs_access()
250 msr->idx = HV_X64_MSR_VP_INDEX; in guest_test_msrs_access()
251 msr->write = true; in guest_test_msrs_access()
252 msr->write_val = 1; in guest_test_msrs_access()
253 msr->fault_expected = true; in guest_test_msrs_access()
257 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
258 msr->write = false; in guest_test_msrs_access()
259 msr->fault_expected = true; in guest_test_msrs_access()
263 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
264 msr->write = false; in guest_test_msrs_access()
265 msr->fault_expected = false; in guest_test_msrs_access()
268 msr->idx = HV_X64_MSR_RESET; in guest_test_msrs_access()
269 msr->write = true; in guest_test_msrs_access()
276 msr->write_val = 0; in guest_test_msrs_access()
277 msr->fault_expected = false; in guest_test_msrs_access()
281 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
282 msr->write = false; in guest_test_msrs_access()
283 msr->fault_expected = true; in guest_test_msrs_access()
287 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
288 msr->write = false; in guest_test_msrs_access()
289 msr->fault_expected = false; in guest_test_msrs_access()
292 msr->idx = HV_X64_MSR_REFERENCE_TSC; in guest_test_msrs_access()
293 msr->write = true; in guest_test_msrs_access()
294 msr->write_val = 0; in guest_test_msrs_access()
295 msr->fault_expected = false; in guest_test_msrs_access()
299 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
300 msr->write = false; in guest_test_msrs_access()
301 msr->fault_expected = true; in guest_test_msrs_access()
308 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
309 msr->write = false; in guest_test_msrs_access()
310 msr->fault_expected = true; in guest_test_msrs_access()
314 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
315 msr->write = false; in guest_test_msrs_access()
316 msr->fault_expected = false; in guest_test_msrs_access()
319 msr->idx = HV_X64_MSR_EOM; in guest_test_msrs_access()
320 msr->write = true; in guest_test_msrs_access()
321 msr->write_val = 0; in guest_test_msrs_access()
322 msr->fault_expected = false; in guest_test_msrs_access()
326 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
327 msr->write = false; in guest_test_msrs_access()
328 msr->fault_expected = true; in guest_test_msrs_access()
332 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
333 msr->write = false; in guest_test_msrs_access()
334 msr->fault_expected = false; in guest_test_msrs_access()
337 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
338 msr->write = true; in guest_test_msrs_access()
339 msr->write_val = 0; in guest_test_msrs_access()
340 msr->fault_expected = false; in guest_test_msrs_access()
344 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
345 msr->write = true; in guest_test_msrs_access()
346 msr->write_val = 1 << 12; in guest_test_msrs_access()
347 msr->fault_expected = true; in guest_test_msrs_access()
351 msr->idx = HV_X64_MSR_STIMER0_CONFIG; in guest_test_msrs_access()
352 msr->write = true; in guest_test_msrs_access()
353 msr->write_val = 1 << 12; in guest_test_msrs_access()
354 msr->fault_expected = false; in guest_test_msrs_access()
358 msr->idx = HV_X64_MSR_EOI; in guest_test_msrs_access()
359 msr->write = false; in guest_test_msrs_access()
360 msr->fault_expected = true; in guest_test_msrs_access()
364 msr->idx = HV_X64_MSR_EOI; in guest_test_msrs_access()
365 msr->write = true; in guest_test_msrs_access()
366 msr->write_val = 1; in guest_test_msrs_access()
367 msr->fault_expected = false; in guest_test_msrs_access()
371 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
372 msr->write = false; in guest_test_msrs_access()
373 msr->fault_expected = true; in guest_test_msrs_access()
377 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
378 msr->write = false; in guest_test_msrs_access()
379 msr->fault_expected = false; in guest_test_msrs_access()
383 msr->idx = HV_X64_MSR_TSC_FREQUENCY; in guest_test_msrs_access()
384 msr->write = true; in guest_test_msrs_access()
385 msr->write_val = 1; in guest_test_msrs_access()
386 msr->fault_expected = true; in guest_test_msrs_access()
390 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
391 msr->write = false; in guest_test_msrs_access()
392 msr->fault_expected = true; in guest_test_msrs_access()
396 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
397 msr->write = false; in guest_test_msrs_access()
398 msr->fault_expected = false; in guest_test_msrs_access()
401 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; in guest_test_msrs_access()
402 msr->write = true; in guest_test_msrs_access()
403 msr->write_val = 1; in guest_test_msrs_access()
404 msr->fault_expected = false; in guest_test_msrs_access()
408 msr->idx = HV_X64_MSR_TSC_EMULATION_STATUS; in guest_test_msrs_access()
409 msr->write = true; in guest_test_msrs_access()
410 msr->write_val = 1; in guest_test_msrs_access()
411 msr->fault_expected = true; in guest_test_msrs_access()
415 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
416 msr->write = false; in guest_test_msrs_access()
417 msr->fault_expected = true; in guest_test_msrs_access()
421 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
422 msr->write = false; in guest_test_msrs_access()
423 msr->fault_expected = false; in guest_test_msrs_access()
426 msr->idx = HV_X64_MSR_CRASH_P0; in guest_test_msrs_access()
427 msr->write = true; in guest_test_msrs_access()
428 msr->write_val = 1; in guest_test_msrs_access()
429 msr->fault_expected = false; in guest_test_msrs_access()
433 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
434 msr->write = false; in guest_test_msrs_access()
435 msr->fault_expected = true; in guest_test_msrs_access()
440 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
441 msr->write = false; in guest_test_msrs_access()
442 msr->fault_expected = false; in guest_test_msrs_access()
445 msr->idx = HV_X64_MSR_SYNDBG_STATUS; in guest_test_msrs_access()
446 msr->write = true; in guest_test_msrs_access()
447 msr->write_val = 0; in guest_test_msrs_access()
448 msr->fault_expected = false; in guest_test_msrs_access()
455 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
456 msr->write = false; in guest_test_msrs_access()
457 msr->fault_expected = true; in guest_test_msrs_access()
464 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
465 msr->write = false; in guest_test_msrs_access()
466 msr->fault_expected = false; in guest_test_msrs_access()
472 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
473 msr->write = true; in guest_test_msrs_access()
474 msr->write_val = 0xdeadbeef; in guest_test_msrs_access()
475 msr->fault_expected = true; in guest_test_msrs_access()
481 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; in guest_test_msrs_access()
482 msr->write = true; in guest_test_msrs_access()
483 msr->write_val = 1; in guest_test_msrs_access()
484 msr->fault_expected = false; in guest_test_msrs_access()
497 msr->idx, msr->write ? "write" : "read"); in guest_test_msrs_access()