Lines Matching +full:0 +full:xc2
19 * in '0' is a nop and won't clobber the CMASK.
21 #define RAW_EVENT(eventsel, umask) (((eventsel & 0xf00UL) << 24) | \
22 ((eventsel) & 0xff) | \
23 ((umask) & 0xff) << 8)
29 #define ARCH_PERFMON_EVENTSEL_EVENT GENMASK_ULL(7, 0)
49 #define FIXED_PMC_KERNEL BIT_ULL(0)
57 #define PMU_CAP_LBR_FMT 0x3f
59 #define INTEL_ARCH_CPU_CYCLES RAW_EVENT(0x3c, 0x00)
60 #define INTEL_ARCH_INSTRUCTIONS_RETIRED RAW_EVENT(0xc0, 0x00)
61 #define INTEL_ARCH_REFERENCE_CYCLES RAW_EVENT(0x3c, 0x01)
62 #define INTEL_ARCH_LLC_REFERENCES RAW_EVENT(0x2e, 0x4f)
63 #define INTEL_ARCH_LLC_MISSES RAW_EVENT(0x2e, 0x41)
64 #define INTEL_ARCH_BRANCHES_RETIRED RAW_EVENT(0xc4, 0x00)
65 #define INTEL_ARCH_BRANCHES_MISPREDICTED RAW_EVENT(0xc5, 0x00)
66 #define INTEL_ARCH_TOPDOWN_SLOTS RAW_EVENT(0xa4, 0x01)
67 #define INTEL_ARCH_TOPDOWN_BE_BOUND RAW_EVENT(0xa4, 0x02)
68 #define INTEL_ARCH_TOPDOWN_BAD_SPEC RAW_EVENT(0x73, 0x00)
69 #define INTEL_ARCH_TOPDOWN_FE_BOUND RAW_EVENT(0x9c, 0x01)
70 #define INTEL_ARCH_TOPDOWN_RETIRING RAW_EVENT(0xc2, 0x02)
71 #define INTEL_ARCH_LBR_INSERTS RAW_EVENT(0xe4, 0x01)
73 #define AMD_ZEN_CORE_CYCLES RAW_EVENT(0x76, 0x00)
74 #define AMD_ZEN_INSTRUCTIONS_RETIRED RAW_EVENT(0xc0, 0x00)
75 #define AMD_ZEN_BRANCHES_RETIRED RAW_EVENT(0xc2, 0x00)
76 #define AMD_ZEN_BRANCHES_MISPREDICTED RAW_EVENT(0xc3, 0x00)