Lines Matching +full:32 +full:-

1 // SPDX-License-Identifier: GPL-2.0
8 /* This file contains sub-register zero extension checks for insns defining
9 * sub-registers, meaning:
10 * - All insns under BPF_ALU class. Their BPF_ALU32 variants or narrow width
11 * forms (BPF_END) could define sub-registers.
12 * - Narrow direct loads, BPF_B/H/W | BPF_LDX.
13 * - BPF_LD is not exposed to JIT back-ends, so no need for testing.
15 * "get_prandom_u32" is used to initialize low 32-bit of some registers to
16 * prevent potential optimizations done by verifier or JIT back-ends which could
31 r0 >>= 32; \ in add32_reg_zero_extend_check()
47 /* An insn could have no effect on the low 32-bit, for example:\ in add32_imm_zero_extend_check()
50 * a = a & -1 \ in add32_imm_zero_extend_check()
51 * But, they should still zero high 32-bit. \ in add32_imm_zero_extend_check()
54 r0 >>= 32; \ in add32_imm_zero_extend_check()
59 w0 += -2; \ in add32_imm_zero_extend_check()
60 r0 >>= 32; \ in add32_imm_zero_extend_check()
77 w0 -= w1; \ in sub32_reg_zero_extend_check()
78 r0 >>= 32; \ in sub32_reg_zero_extend_check()
94 w0 -= 0; \ in sub32_imm_zero_extend_check()
95 r0 >>= 32; \ in sub32_imm_zero_extend_check()
100 w0 -= 1; \ in sub32_imm_zero_extend_check()
101 r0 >>= 32; \ in sub32_imm_zero_extend_check()
119 r0 >>= 32; \ in mul32_reg_zero_extend_check()
136 r0 >>= 32; \ in mul32_imm_zero_extend_check()
141 w0 *= -1; \ in mul32_imm_zero_extend_check()
142 r0 >>= 32; \ in mul32_imm_zero_extend_check()
158 r0 = -1; \ in div32_reg_zero_extend_check()
160 r0 >>= 32; \ in div32_reg_zero_extend_check()
177 r0 >>= 32; \ in div32_imm_zero_extend_check()
183 r0 >>= 32; \ in div32_imm_zero_extend_check()
201 r0 >>= 32; \ in or32_reg_zero_extend_check()
218 r0 >>= 32; \ in or32_imm_zero_extend_check()
224 r0 >>= 32; \ in or32_imm_zero_extend_check()
243 r0 >>= 32; \ in and32_reg_zero_extend_check()
259 w0 &= -1; \ in and32_imm_zero_extend_check()
260 r0 >>= 32; \ in and32_imm_zero_extend_check()
265 w0 &= -2; \ in and32_imm_zero_extend_check()
266 r0 >>= 32; \ in and32_imm_zero_extend_check()
285 r0 >>= 32; \ in lsh32_reg_zero_extend_check()
302 r0 >>= 32; \ in lsh32_imm_zero_extend_check()
308 r0 >>= 32; \ in lsh32_imm_zero_extend_check()
327 r0 >>= 32; \ in rsh32_reg_zero_extend_check()
344 r0 >>= 32; \ in rsh32_imm_zero_extend_check()
350 r0 >>= 32; \ in rsh32_imm_zero_extend_check()
367 w0 = -w0; \ in neg32_reg_zero_extend_check()
368 r0 >>= 32; \ in neg32_reg_zero_extend_check()
383 r0 = -1; \ in mod32_reg_zero_extend_check()
385 r0 >>= 32; \ in mod32_reg_zero_extend_check()
402 r0 >>= 32; \ in mod32_imm_zero_extend_check()
408 r0 >>= 32; \ in mod32_imm_zero_extend_check()
426 r0 >>= 32; \ in xor32_reg_zero_extend_check()
443 r0 >>= 32; \ in xor32_imm_zero_extend_check()
461 r0 >>= 32; \ in mov32_reg_zero_extend_check()
478 r0 >>= 32; \ in mov32_imm_zero_extend_check()
484 r0 >>= 32; \ in mov32_imm_zero_extend_check()
503 r0 >>= 32; \ in arsh32_reg_zero_extend_check()
520 r0 >>= 32; \ in arsh32_imm_zero_extend_check()
526 r0 >>= 32; \ in arsh32_imm_zero_extend_check()
542 r6 <<= 32; \ in le_reg_zero_extend_check_1()
546 r0 >>= 32; \ in le_reg_zero_extend_check_1()
561 r6 <<= 32; \ in le_reg_zero_extend_check_2()
565 r0 >>= 32; \ in le_reg_zero_extend_check_2()
580 r6 <<= 32; \ in be_reg_zero_extend_check_1()
584 r0 >>= 32; \ in be_reg_zero_extend_check_1()
599 r6 <<= 32; \ in be_reg_zero_extend_check_2()
603 r0 >>= 32; \ in be_reg_zero_extend_check_2()
617 r6 += -4; \ in ldx_b_zero_extend_check()
624 r0 >>= 32; \ in ldx_b_zero_extend_check()
638 r6 += -4; \ in ldx_h_zero_extend_check()
645 r0 >>= 32; \ in ldx_h_zero_extend_check()
659 r6 += -4; \ in ldx_w_zero_extend_check()
666 r0 >>= 32; \ in ldx_w_zero_extend_check()