Lines Matching +full:7 +full:- +full:3
4 "Counter": "0,1,2,3,4,5,6,7",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
14 "Counter": "0,1,2,3,4,5,6,7",
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
82 "Counter": "0,1,2,3,4,5,6,7",
92 "Counter": "0,1,2,3,4,5,6,7",
102 "Counter": "0,1,2,3,4,5,6,7",
112 "Counter": "0,1,2,3,4,5,6,7",
121 "Counter": "0,1,2,3,4,5,6,7",
130 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
131 "Counter": "0,1,2,3,4,5,6,7",
141 "Counter": "0,1,2,3,4,5,6,7",
150 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
151 "Counter": "0,1,2,3,4,5,6,7",
155 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
161 "Counter": "0,1,2,3,4,5,6,7",
171 "Counter": "0,1,2,3,4,5,6,7",
181 "Counter": "0,1,2,3,4,5,6,7",
185 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
191 "Counter": "0,1,2,3,4,5,6,7",
200 "Counter": "0,1,2,3,4,5,6,7",
209 "Counter": "0,1,2,3,4,5,6,7",
212 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
226 "Counter": "0,1,2,3,4,5,6,7",
243 "Counter": "0,1,2,3,4,5,6,7",
251 "Counter": "0,1,2,3",
260 "Counter": "0,1,2,3",
269 "Counter": "0,1,2,3,4,5,6,7",
278 "Counter": "0,1,2,3",
287 "Counter": "0,1,2,3",
296 "Counter": "0,1,2,3,4,5,6,7",
305 "Counter": "0,1,2,3,4,5,6,7",
314 "Counter": "0,1,2,3,4,5,6,7",
323 "Counter": "0,1,2,3,4,5,6,7",
331 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
332 "Counter": "0,1,2,3,4,5,6,7",
334 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
335 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
341 "Counter": "0,1,2,3,4,5,6,7",
350 "Counter": "0,1,2,3,4,5,6,7",
360 "Counter": "0,1,2,3,4,5,6,7",
370 "Counter": "0,1,2,3,4,5,6,7",
379 "Counter": "0,1,2,3",
382 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
388 "Counter": "0,1,2,3",
396 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
400 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
405 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
406 "Counter": "0,1,2,3,4,5,6,7",
410 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
415 "Counter": "0,1,2,3,4,5,6,7",
433 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
434 "Counter": "0,1,2,3,4,5,6,7",
438 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
444 "Counter": "0,1,2,3,4,5,6,7",
455 "Counter": "0,1,2,3,4,5,6,7",
464 "Counter": "0,1,2,3,4,5,6,7",
473 "Counter": "0,1,2,3,4,5,6,7",
476 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
482 "Counter": "0,1,2,3",
491 "Counter": "0,1,2,3",
500 "Counter": "0,1,2,3",
509 "Counter": "0,1,2,3",
512 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
518 "Counter": "0,1,2,3",
522 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
528 "Counter": "0,1,2,3",
532 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
538 "Counter": "0,1,2,3",
541 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
547 "Counter": "0,1,2,3,4,5,6,7",
557 "BriefDescription": "Self-modifying code (SMC) detected.",
558 "Counter": "0,1,2,3,4,5,6,7",
561 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
567 "Counter": "0,1,2,3,4,5,6,7",
576 "Counter": "0,1,2,3,4,5,6,7",
585 "Counter": "0,1,2,3,4,5,6,7",
588 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
594 "Counter": "0,1,2,3,4,5,6,7",
602 "Counter": "0,1,2,3,4,5,6,7",
605 … This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch misp…
611 "Counter": "0,1,2,3,4,5,6,7",
617 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
622 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
623 "Counter": "0,1,2,3,4,5,6,7",
626 …-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued…
631 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
632 "Counter": "Fixed counter 3",
634 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
639 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
640 "Counter": "0,1,2,3,4,5,6,7",
643 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
649 "Counter": "0,1,2,3",
658 "Counter": "0,1,2,3,4,5,6,7",
661 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
667 "Counter": "0,1,2,3,4,5,6,7",
670 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
675 "BriefDescription": "Number of uops executed on port 2 and 3",
676 "Counter": "0,1,2,3,4,5,6,7",
679 …Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reser…
685 "Counter": "0,1,2,3,4,5,6,7",
688 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
694 "Counter": "0,1,2,3,4,5,6,7",
697 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
703 "Counter": "0,1,2,3,4,5,6,7",
706 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
711 "BriefDescription": "Number of uops executed on port 7 and 8",
712 "Counter": "0,1,2,3,4,5,6,7",
715 …: "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Re…
721 "Counter": "0,1,2,3,4,5,6,7",
729 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
730 "Counter": "0,1,2,3,4,5,6,7",
734 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
739 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
740 "Counter": "0,1,2,3,4,5,6,7",
744 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
749 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
750 "Counter": "0,1,2,3,4,5,6,7",
751 "CounterMask": "3",
754 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
759 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
760 "Counter": "0,1,2,3,4,5,6,7",
764 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
769 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
770 "Counter": "0,1,2,3,4,5,6,7",
774 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
779 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
780 "Counter": "0,1,2,3,4,5,6,7",
784 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
789 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
790 "Counter": "0,1,2,3,4,5,6,7",
791 "CounterMask": "3",
794 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
799 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
800 "Counter": "0,1,2,3,4,5,6,7",
804 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
810 "Counter": "0,1,2,3,4,5,6,7",
820 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
821 "Counter": "0,1,2,3,4,5,6,7",
829 "Counter": "0,1,2,3,4,5,6,7",
838 "Counter": "0,1,2,3,4,5,6,7",
847 "Counter": "0,1,2,3,4,5,6,7",
857 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
858 "Counter": "0,1,2,3,4,5,6,7",
861 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
867 "Counter": "0,1,2,3,4,5,6,7",
876 "Counter": "0,1,2,3,4,5,6,7",
887 "Counter": "0,1,2,3,4,5,6,7",