Lines Matching +full:3 +full:- +full:6
4 "Counter": "0,1,2,3,4,5,6,7",
8 "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
14 "Counter": "0,1,2,3,4,5,6,7",
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,6,7",
76 "Counter": "0,1,2,3,4,5,6,7",
85 "Counter": "0,1,2,3,4,5,6,7",
94 "Counter": "0,1,2,3,4,5,6,7",
103 "Counter": "0,1,2,3,4,5,6,7",
112 "Counter": "0,1,2,3,4,5,6,7",
120 "Counter": "0,1,2,3,4,5,6,7",
128 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
129 "Counter": "0,1,2,3,4,5,6,7",
138 "Counter": "0,1,2,3,4,5,6,7",
146 "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
147 "Counter": "0,1,2,3,4,5,6,7",
150 "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
156 "Counter": "0,1,2,3,4,5,6,7",
165 "Counter": "0,1,2,3,4,5,6,7",
174 "Counter": "0,1,2,3,4,5,6,7",
177 "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
183 "Counter": "0,1,2,3,4,5,6,7",
192 "Counter": "0,1,2,3,4,5,6,7",
201 "Counter": "0,1,2,3,4,5,6,7",
204 "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
218 "Counter": "0,1,2,3,4,5,6,7",
235 "Counter": "0,1,2,3,4,5,6,7",
243 "Counter": "0,1,2,3",
252 "Counter": "0,1,2,3",
261 "Counter": "0,1,2,3,4,5,6,7",
270 "Counter": "0,1,2,3",
279 "Counter": "0,1,2,3",
288 "Counter": "0,1,2,3,4,5,6,7",
297 "Counter": "0,1,2,3,4,5,6,7",
306 "Counter": "0,1,2,3,4,5,6,7",
315 "Counter": "0,1,2,3,4,5,6,7",
323 "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
324 "Counter": "0,1,2,3,4,5,6,7",
326 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
327 "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
333 "Counter": "0,1,2,3,4,5,6,7",
342 "Counter": "0,1,2,3,4,5,6,7",
352 "Counter": "0,1,2,3,4,5,6,7",
362 "Counter": "0,1,2,3,4,5,6,7",
371 "Counter": "0,1,2,3",
374 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]",
380 "Counter": "0,1,2,3",
388 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
391 "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
396 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
397 "Counter": "0,1,2,3,4,5,6,7",
400 "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
405 "Counter": "0,1,2,3,4,5,6,7",
421 "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
422 "Counter": "0,1,2,3,4,5,6,7",
426 "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
432 "Counter": "0,1,2,3,4,5,6,7",
443 "Counter": "0,1,2,3,4,5,6,7",
452 "Counter": "0,1,2,3,4,5,6,7",
461 "Counter": "0,1,2,3,4,5,6,7",
464 "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
470 "Counter": "0,1,2,3",
479 "Counter": "0,1,2,3",
488 "Counter": "0,1,2,3",
497 "Counter": "0,1,2,3",
500 "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
506 "Counter": "0,1,2,3",
510 "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
516 "Counter": "0,1,2,3",
520 "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
526 "Counter": "0,1,2,3",
529 "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
535 "Counter": "0,1,2,3,4,5,6,7",
545 "BriefDescription": "Self-modifying code (SMC) detected.",
546 "Counter": "0,1,2,3,4,5,6,7",
549 "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
555 "Counter": "0,1,2,3,4,5,6,7",
564 "Counter": "0,1,2,3,4,5,6,7",
573 "Counter": "0,1,2,3,4,5,6,7",
576 "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
582 "Counter": "0,1,2,3,4,5,6,7",
590 "Counter": "0,1,2,3,4,5,6,7",
593 "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)",
599 "Counter": "0,1,2,3,4,5,6,7",
605 "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
610 "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
611 "Counter": "0,1,2,3,4,5,6,7",
614 "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
619 "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
620 "Counter": "Fixed counter 3",
622 "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
627 "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
628 "Counter": "0,1,2,3,4,5,6,7",
631 "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
637 "Counter": "0,1,2,3",
646 "Counter": "0,1,2,3,4,5,6,7",
649 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
655 "Counter": "0,1,2,3,4,5,6,7",
658 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
663 "BriefDescription": "Number of uops executed on port 2 and 3",
664 "Counter": "0,1,2,3,4,5,6,7",
667 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
673 "Counter": "0,1,2,3,4,5,6,7",
676 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
682 "Counter": "0,1,2,3,4,5,6,7",
685 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
690 "BriefDescription": "Number of uops executed on port 6",
691 "Counter": "0,1,2,3,4,5,6,7",
694 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
700 "Counter": "0,1,2,3,4,5,6,7",
703 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
709 "Counter": "0,1,2,3,4,5,6,7",
717 "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
718 "Counter": "0,1,2,3,4,5,6,7",
722 "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
727 "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
728 "Counter": "0,1,2,3,4,5,6,7",
732 "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
737 "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
738 "Counter": "0,1,2,3,4,5,6,7",
739 "CounterMask": "3",
742 "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
747 "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
748 "Counter": "0,1,2,3,4,5,6,7",
752 "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
757 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
758 "Counter": "0,1,2,3,4,5,6,7",
762 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
767 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
768 "Counter": "0,1,2,3,4,5,6,7",
772 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
777 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
778 "Counter": "0,1,2,3,4,5,6,7",
779 "CounterMask": "3",
782 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
787 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
788 "Counter": "0,1,2,3,4,5,6,7",
792 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
798 "Counter": "0,1,2,3,4,5,6,7",
808 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
809 "Counter": "0,1,2,3,4,5,6,7",
817 "Counter": "0,1,2,3,4,5,6,7",
826 "Counter": "0,1,2,3,4,5,6,7",
835 "Counter": "0,1,2,3,4,5,6,7",
845 "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
846 "Counter": "0,1,2,3,4,5,6,7",
849 "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
855 "Counter": "0,1,2,3,4,5,6,7",
864 "Counter": "0,1,2,3,4,5,6,7",
875 "Counter": "0,1,2,3,4,5,6,7",