Lines Matching full:instructions

123         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
127         "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
132         "BriefDescription": "L2 cache misses when fetching instructions",
136         "PublicDescription": "Counts L2 cache misses when fetching instructions.",
145         "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
199         "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
208         "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
240         "BriefDescription": "Retired load instructions.",
245         "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
250         "BriefDescription": "Retired store instructions.",
255         "PublicDescription": "Counts all retired store instructions.",
260         "BriefDescription": "All retired memory instructions.",
265         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
270         "BriefDescription": "Retired load instructions with locked access.",
275         "PublicDescription": "Counts retired load instructions with locked access.",
280         "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
285         "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
290         "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
295         "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
300         "BriefDescription": "Retired load instructions that miss the STLB.",
305         "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
310         "BriefDescription": "Retired store instructions that miss the STLB.",
315         "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
325         "PublicDescription": "Counts retired load instructions where a cross-core snoop hit in another cores caches on this socket, the data was forwarded back to the requesting core as the data was modified (SNOOP_HITM) or the L3 did not have the data(SNOOP_HIT_WITH_FWD).",
330         "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
335         "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
340         "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
345         "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
355         "PublicDescription": "Counts retired load instructions in which the L3 supplied the data and a cross-core snoop hit in another cores caches on this socket but that other core did not forward the data back (SNOOP_HIT_NO_FWD).",
360         "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
365         "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access",
375         "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
380         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
385         "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
390         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
395         "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
400         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
405         "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
410         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
415         "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
420         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
425         "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
430         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
435         "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
600         "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
608         "BriefDescription": "Number of PREFETCHNTA instructions executed.",
612         "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
617         "BriefDescription": "Number of PREFETCHW instructions executed.",
621         "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
626         "BriefDescription": "Number of PREFETCHT0 instructions executed.",
630         "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
635         "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
639         "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",