Lines Matching +full:os +full:- +full:initiated
4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
97 …"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are r…
103 …"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are …
261 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
274 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
299 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
316 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
321 …"MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 i…
326 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
331 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / …
336 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
347 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
356 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
361 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
365 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
370 …"MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.…
388 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
390 "MetricExpr": "tma_backend_bound - tma_memory_bound",
395 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
399 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
401 … (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RESPONSE.DEM…
405 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
409 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
410 …"MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) /…
414 …"PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only activ…
429 …o_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread…
438 "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2",
451 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
457 …mask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLE…
461 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
465 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
470 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
480 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
495 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
510 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
516 "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
520 …t are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the n…
524 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
530 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
539 …ts. FP Assist may apply when working with very small floating point values (so-called Denormals).",
543 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
548 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
552 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
558 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
562 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
567 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
571 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
576 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
580 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
585 … approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May…
595 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
599 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
604 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
608 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
609 …"MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / tma_inf…
614 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
627 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
631 …"PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative …
641 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
654 … "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
656 …"MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_ut…
662 …"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch…
667 …"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetc…
670 …"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fet…
676 …"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fe…
679 …"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bott…
684 …"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bot…
687 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
695 …"BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset …
700 …"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset…
703 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottleneck…
708 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenec…
711 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
716 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks…
719 … "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
724 …ine cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as w…
727 …tch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the…
729 …- (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_…
740 …"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait tim…
743 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
749 …"Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related m…
753 …alse_sharing + tma_split_stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (…
762 …"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispre…
769 "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
770 …"MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tm…
774 …aining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) a…
777 …"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring catego…
778 … "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIR…
790 "BriefDescription": "Fraction of branches that are non-taken conditionals",
797 …"MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRA…
804 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.COND - BR_INST_RETIRED.NOT_TAKEN) - …
815 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
834 …BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardles…
838 …-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width…
841 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
855 …tion": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_…
861 "BriefDescription": "Average number of Uops issued by front-end when it issued something",
873 …"BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurren…
920 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
925 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
928 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
933 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
936 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
941 …"PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means h…
944 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
949 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
952 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
957 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
1011 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
1017 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
1035 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
1041 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
1047 … instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
1053 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
1071 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
1078 "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
1113 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
1119 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
1149 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
1155 "BriefDescription": "Un-cacheable retired load per kilo instruction",
1161 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
1165 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
1168 … level TLB) code speculative misses per kilo instruction (misses of any page-size that complete th…
1174 …l TLB) data load speculative misses per kilo instruction (misses of any page-size that complete th…
1188 … TLB) data store speculative misses per kilo instruction (misses of any page-size that complete th…
1194 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
1256 …egate across all supported options of: FP precisions, scalar and vector instructions, vector-width"
1263 …isk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device co…
1270 …k) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device co…
1275 "MetricGroup": "Branches;OS",
1280 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
1282 "MetricGroup": "OS",
1286 "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
1288 "MetricGroup": "OS",
1297 …to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches"
1311 …y (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)"
1314 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for ba…
1318 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX…
1321 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1326 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct…
1329 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1334 …e the core was running with power-delivery for license level 2 (introduced in SKX). This includes…
1338 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #S…
1361 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
1373 "BriefDescription": "The ratio of Executed- by Issued-Uops",
1377 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
1386 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
1416 …"MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thr…
1420 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
1425 …EM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CY…
1429 …e L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access…
1435 … cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALL…
1444 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_c…
1470 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
1471 "MetricExpr": "tma_retiring - tma_heavy_operations",
1476 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
1481 …HED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT…
1489 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
1491 "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
1498 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
1516 …"MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOC…
1526 "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
1531 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
1535 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
1540 …- DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic i…
1544 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1545 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1549 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1560 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
1564 … represents fraction of slots where the CPU was retiring memory operations -- uops for memory load…
1592 …"MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_cl…
1596 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
1600 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1605 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1614 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
1619 …"MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / …
1623 …lots where the CPU was retiring branch instructions that were not fused. Non-conditional branches …
1632 …o op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address o…
1636 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1637 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_ins…
1641 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1645 …action of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches …
1646 …"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_C…
1654 …"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT…
1679 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
1684 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
1688 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
1693 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
1697 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
1702 …sents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: U…
1724 …ents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
1729 …action of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with…
1733 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
1734 … tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALL…
1738 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
1747 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
1752 …"MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on e…
1756 …-dependency among software instructions; or over oversubscribing a particular hardware resource. I…
1761 …"MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on e…
1765 …cal Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options…
1783 …r sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocati…
1792 …ystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocati…
1802 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
1806 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
1811 …ycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; W…
1815 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1821 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1830 …resents rate of split store accesses. Consider aligning your data to the 64-byte cache line granu…
1834 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1839 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1843 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
1848 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
1857 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
1863 …"MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_ST…
1867 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
1879 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
1880 "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
1914 "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)",
1921 "MetricExpr": "(cycles\\-t / el\\-start if has_event(el\\-start) else 0)",
1928 "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)",
1935 "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)",