Lines Matching +full:3 +full:- +full:line
3 "BriefDescription": "L1D data line replacements",
4 "Counter": "0,1,2,3",
7 … "Counts L1D data line replacements including opportunistic replacements, and replacements that re…
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
25 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
31 "Counter": "0,1,2,3",
42 "Counter": "0,1,2,3",
51 "Counter": "0,1,2,3",
60 "Counter": "0,1,2,3",
68 …n triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
69 "Counter": "0,1,2,3",
77 "Counter": "0,1,2,3",
85 "Counter": "0,1,2,3",
94 "Counter": "0,1,2,3",
103 "Counter": "0,1,2,3",
112 "Counter": "0,1,2,3",
121 "Counter": "0,1,2,3",
130 "Counter": "0,1,2,3",
139 "Counter": "0,1,2,3",
148 "Counter": "0,1,2,3",
157 "Counter": "0,1,2,3",
166 "Counter": "0,1,2,3",
175 "Counter": "0,1,2,3",
184 "Counter": "0,1,2,3",
193 "Counter": "0,1,2,3",
202 "Counter": "0,1,2,3",
211 "Counter": "0,1,2,3",
220 "Counter": "0,1,2,3",
223 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
229 "Counter": "0,1,2,3",
232 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
238 "Counter": "0,1,2,3",
246 "BriefDescription": "Core-originated cacheable demand requests missed L3",
247 "Counter": "0,1,2,3",
251 … "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Reques…
256 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
257 "Counter": "0,1,2,3",
261 …n": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests …
267 "Counter": "0,1,2,3",
278 "Counter": "0,1,2,3",
289 "Counter": "0,1,2,3",
294 "PublicDescription": "Counts all retired memory instructions - loads and stores.",
300 "Counter": "0,1,2,3",
310 "Counter": "0,1,2,3",
321 "Counter": "0,1,2,3",
332 "Counter": "0,1,2,3",
337 …"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB…
343 "Counter": "0,1,2,3",
348 …"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TL…
353 …: "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core c…
354 "Counter": "0,1,2,3",
359 …: "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core c…
365 "Counter": "0,1,2,3",
375 …tired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core …
376 "Counter": "0,1,2,3",
386 "Counter": "0,1,2,3",
397 "Counter": "0,1,2,3",
408 "Counter": "0,1,2,3",
418 "Counter": "0,1,2,3",
429 "Counter": "0,1,2,3",
440 "Counter": "0,1,2,3",
449 …es were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready…
450 "Counter": "0,1,2,3",
455 …d in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready…
461 "Counter": "0,1,2,3",
472 "Counter": "0,1,2,3",
483 "Counter": "0,1,2,3",
494 "Counter": "0,1,2,3",
505 "Counter": "0,1,2,3",
516 "Counter": "0,1,2,3",
527 "Counter": "0,1,2,3",
536 "Counter": "0,1,2,3",
544 "BriefDescription": "Cacheable and non-cacheable code read requests",
545 "Counter": "0,1,2,3",
548 "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
554 "Counter": "0,1,2,3",
563 "Counter": "0,1,2,3",
572 "Counter": "0,1,2,3",
581 "Counter": "0,1,2,3",
584 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
590 "Counter": "0,1,2,3",
594 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
600 "Counter": "0,1,2,3",
610 "Counter": "0,1,2,3",
614 …utstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
620 "Counter": "0,1,2,3",
630 "Counter": "0,1,2,3",
639 "Counter": "0,1,2,3",
648 "Counter": "0,1,2,3",
657 "Counter": "0,1,2,3",
660 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
666 "Counter": "0,1,2,3",
675 "Counter": "0,1,2,3",
685 "Counter": "0,1,2,3",
694 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
695 "Counter": "0,1,2,3",
704 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
705 "Counter": "0,1,2,3",
714 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
715 "Counter": "0,1,2,3",
725 "Counter": "0,1,2,3",
735 "Counter": "0,1,2,3",
745 "Counter": "0,1,2,3",
754 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
755 "Counter": "0,1,2,3",
764 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
765 "Counter": "0,1,2,3",
774 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
775 "Counter": "0,1,2,3",
785 "Counter": "0,1,2,3",
795 "Counter": "0,1,2,3",
805 "Counter": "0,1,2,3",
814 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
815 "Counter": "0,1,2,3",
824 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
825 "Counter": "0,1,2,3",
834 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
835 "Counter": "0,1,2,3",
845 "Counter": "0,1,2,3",
854 …n the L3 and the snoop to one of the sibling cores hits the line in E/S/F state and the line is fo…
855 "Counter": "0,1,2,3",
865 "Counter": "0,1,2,3",
875 "Counter": "0,1,2,3",
884 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
885 "Counter": "0,1,2,3",
894 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
895 "Counter": "0,1,2,3",
904 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
905 "Counter": "0,1,2,3",
915 "Counter": "0,1,2,3",
925 "Counter": "0,1,2,3",
935 "Counter": "0,1,2,3",
944 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
945 "Counter": "0,1,2,3",
954 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
955 "Counter": "0,1,2,3",
964 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
965 "Counter": "0,1,2,3",
975 "Counter": "0,1,2,3",
985 "Counter": "0,1,2,3",
995 "Counter": "0,1,2,3",
1004 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1005 "Counter": "0,1,2,3",
1014 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1015 "Counter": "0,1,2,3",
1024 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1025 "Counter": "0,1,2,3",
1035 "Counter": "0,1,2,3",
1045 "Counter": "0,1,2,3",
1055 "Counter": "0,1,2,3",
1064 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1065 "Counter": "0,1,2,3",
1074 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1075 "Counter": "0,1,2,3",
1084 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1085 "Counter": "0,1,2,3",
1095 "Counter": "0,1,2,3",
1105 "Counter": "0,1,2,3",
1115 "Counter": "0,1,2,3",
1124 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1125 "Counter": "0,1,2,3",
1134 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1135 "Counter": "0,1,2,3",
1144 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1145 "Counter": "0,1,2,3",
1155 "Counter": "0,1,2,3",
1165 "Counter": "0,1,2,3",
1175 "Counter": "0,1,2,3",
1184 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1185 "Counter": "0,1,2,3",
1194 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1195 "Counter": "0,1,2,3",
1204 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1205 "Counter": "0,1,2,3",
1215 "Counter": "0,1,2,3",
1225 "Counter": "0,1,2,3",
1235 "Counter": "0,1,2,3",
1244 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1245 "Counter": "0,1,2,3",
1254 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1255 "Counter": "0,1,2,3",
1264 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1265 "Counter": "0,1,2,3",
1275 "Counter": "0,1,2,3",
1285 "Counter": "0,1,2,3",
1295 "Counter": "0,1,2,3",
1304 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1305 "Counter": "0,1,2,3",
1314 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1315 "Counter": "0,1,2,3",
1324 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1325 "Counter": "0,1,2,3",
1335 "Counter": "0,1,2,3",
1345 "Counter": "0,1,2,3",
1355 "Counter": "0,1,2,3",
1364 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1365 "Counter": "0,1,2,3",
1374 … in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1375 "Counter": "0,1,2,3",
1384 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1385 "Counter": "0,1,2,3",
1395 "Counter": "0,1,2,3",
1404 "BriefDescription": "Number of cache line split locks sent to uncore.",
1405 "Counter": "0,1,2,3",
1408 "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
1414 "Counter": "0,1,2,3",
1422 "Counter": "0,1,2,3",
1430 "Counter": "0,1,2,3",
1438 "Counter": "0,1,2,3",
1446 "Counter": "0,1,2,3",