Lines Matching full:either

151 … (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the …
201 … (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the …
241 … "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the …
291 … (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the …
351 …nstruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the …
411 …U prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the …
461 …nd DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the …
541 …prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the …
571 …ed by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the …
611 …ed by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the …
651 …ed by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the …
732 …s the number of retired memory operations with lock semantics. These are either implicit locked in…