Lines Matching +full:per +full:- +full:rate
3 "BriefDescription": "C1 residency percent per core",
4 "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
10 "BriefDescription": "C2 residency percent per package",
11 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
17 "BriefDescription": "C6 residency percent per core",
18 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
24 "BriefDescription": "C6 residency percent per package",
25 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
31 "BriefDescription": "Uncore frequency per die [GHZ]",
37 …"BriefDescription": "Cycles per instruction retired; indicating how much time each executed instru…
312 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
343 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
384 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
398 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
403 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
409 "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
414 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
418 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
425 …"BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset …
430 …"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset…
433 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottleneck…
438 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenec…
441 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
446 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks…
449 … "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
454 …ine cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as w…
457 …tch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the…
458 …- (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_…
465 …"MetricExpr": "100 * ((1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=1@) * (tma_f…
469 …"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait tim…
472 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
477 …"Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related m…
481 …t_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (…
489 …"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispre…
496 "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
497 …"MetricExpr": "100 - (tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottlene…
501 …aining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) a…
504 …"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring catego…
505 … "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIR…
513 …"MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\…
518 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
527 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
531 … represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized…
539 … represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized…
548 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
552 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
557 …"MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES …
566 "MetricExpr": "max(0, tma_icache_misses - tma_code_l2_miss)",
581 …irst level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)",
582 "MetricExpr": "max(0, tma_itlb_misses - tma_code_stlb_miss)",
589 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
623 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
625 "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
630 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
634 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
636 …MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L…
640 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
644 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
645 …"MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) /…
649 …"PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only activ…
672 "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2",
685 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
690 …mask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCL…
694 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
698 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
703 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
712 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
727 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
738 …MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
743 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
748 "MetricExpr": "max(0, tma_heavy_operations - tma_microcode_sequencer)",
752 …tiring instructions that that are decoder into two or more uops. This highly-correlates with the n…
756 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
761 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
770 …ts. FP Assist may apply when working with very small floating point values (so-called Denormals).",
774 …"BriefDescription": "This metric represents fraction of cycles where the Floating-Point Divider un…
782 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
787 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
791 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
796 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
800 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
805 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
809 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
814 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
818 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
823 … approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May…
829 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
834 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
838 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
843 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
847 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
849 …"MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
854 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
867 …ch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch…
871 …ch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch…
874 …scription": "Instructions per retired Mispredicts for conditional non-taken branches (lower number…
881 …Description": "Instructions per retired Mispredicts for conditional taken branches (lower number m…
888 …scription": "Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number …
895 …BriefDescription": "Instructions per retired Mispredicts for return branches (lower number means h…
902 …ion": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number mea…
915 … "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
916 …"MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_ut…
922 …"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch…
927 …"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetc…
930 …"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fet…
935 …"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fe…
938 …"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bott…
943 …"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bot…
952 "BriefDescription": "Fraction of branches that are non-taken conditionals",
965 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR…
971 …"MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_call…
982 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
988 "BriefDescription": "uops Executed per Cycle",
994 "BriefDescription": "Floating Point Operations Per Cycle",
1000 …"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardle…
1004 …per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-wi…
1007 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
1021 …tion": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_…
1027 "BriefDescription": "Average number of Uops issued by front-end when it issued something",
1039 …"BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurren…
1046 …Description": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number m…
1052 "BriefDescription": "L2 cache true code cacheline misses per kilo instruction",
1058 "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction",
1064 "BriefDescription": "Taken Branches retired Per Cycle",
1070 …"BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch d…
1074 …"PublicDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch …
1077 "BriefDescription": "Branch instructions per taken branch.",
1090 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
1095 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
1098 …riefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means …
1103 …blicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means …
1106 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
1111 …PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
1114 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
1119 …PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
1122 …Description": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number me…
1127 …Description": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number me…
1130 …fDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number mea…
1135 …cDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number mea…
1138 …Description": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number me…
1143 …Description": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number me…
1146 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
1153 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
1160 …"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occ…
1167 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
1174 "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)",
1180 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
1187 …ion": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower …
1194 "BriefDescription": "Instructions per taken branch",
1199 …"PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_…
1202 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
1208 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
1214 "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
1220 …"BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evi…
1226 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
1232 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
1238 …iption": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that me…
1244 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
1250 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
1256 …"BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including spe…
1262 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
1268 …"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculati…
1269 "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
1274 …"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculati…
1280 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
1286 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (inc…
1292 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (inc…
1298 "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
1304 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
1310 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
1316 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
1346 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
1352 "BriefDescription": "\"Bus lock\" per kilo instruction",
1358 "BriefDescription": "Off-core accesses per kilo instruction for modified write requests",
1364 …"BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculativ…
1370 …"BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative;…
1376 "BriefDescription": "Un-cacheable retired load per kilo instruction",
1382 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
1386 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
1389 "BriefDescription": "Rate of L2 HW prefetched lines that were not used by demand accesses",
1396 …riefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- …
1400 …blicDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- …
1403 "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C)",
1407 …"PublicDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRA…
1410 "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C)",
1414 …"PublicDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand o…
1417 …ription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-s…
1423 …on": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-s…
1436 …n": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-s…
1448 "BriefDescription": "Average number of uops fetched from DSB per cycle",
1454 "BriefDescription": "Average number of uops fetched from MITE per cycle",
1460 "BriefDescription": "Instructions per a microcode Assist invocation",
1465 …tion": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower n…
1474 … "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
1481 …et unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized…
1513 "BriefDescription": "Giga Floating Point Operations Per Second",
1517 …ting Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar…
1534 …per Far Branch ( Far Branches apply upon transition from application to operating system, handling…
1541 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
1558 …to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches"
1580 …y (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)"
1591 … "MetricExpr": "(power@energy\\-pkg@ * 61 + 15.6 * power@energy\\-ram@) / (duration_time * 1e6)",
1597 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_…
1627 …"BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data o…
1633 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
1639 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
1645 "BriefDescription": "The ratio of Executed- by Issued-Uops",
1649 …ion": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. R…
1652 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
1658 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
1664 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
1670 "BriefDescription": "Uops Per Instruction",
1677 "BriefDescription": "Uops per taken branch",
1685 "MetricExpr": "tma_divider - tma_fp_divider",
1701 …"BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neu…
1706 …"PublicDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Ne…
1710 …"BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector…
1715 …"PublicDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vecto…
1729 …"MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / tma_info_thre…
1733 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
1738 …EM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CY…
1742 … the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access…
1747 …"MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / tma_info_threa…
1766 …"MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / tma_info_thread…
1793 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
1795 "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
1800 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
1813 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
1814 "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
1821 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
1863 …"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOC…
1873 "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
1878 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
1890 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
1895 …- DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic i…
1899 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1900 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1904 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1910 …"MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
1915 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
1928 … represents fraction of slots where the CPU was retiring memory operations -- uops for memory load…
1955 "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2",
1959 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
1963 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1968 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1972 …es in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequen…
1985 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
1990 …"MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / …
1994 …lots where the CPU was retiring branch instructions that were not fused. Non-conditional branches …
2003 …o op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address o…
2007 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
2008 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_opera…
2012 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
2016 …action of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches …
2017 …"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_C…
2025 …"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT…
2068 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
2069 …)) / tma_info_thread_clks if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_O…
2073 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
2078 …0_PORTS + max(RS.EMPTY_RESOURCE - RESOURCE_STALLS.SCOREBOARD, 0)) / tma_info_thread_clks * (CYCLE_…
2082 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
2086 …metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execut…
2091 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
2095 …": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execut…
2101 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
2105 … metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execut…
2111 … metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execut…
2120 …r sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocati…
2129 …ystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocati…
2135 …"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retir…
2140 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
2144 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
2149 …ycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; W…
2153 …sents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP o…
2158 …sents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP o…
2172 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
2177 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
2181 "BriefDescription": "This metric represents rate of split store accesses",
2186 …blicDescription": "This metric represents rate of split store accesses. Consider aligning your da…
2190 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
2195 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
2199 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
2204 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
2213 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
2218 …xpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_ST…
2222 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
2235 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
2236 "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
2280 …uired by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there ar…
2303 "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)",
2310 "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)",
2317 "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)",