Lines Matching +full:3 +full:- +full:6
4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3,4,5,6,7",
81 "Counter": "0,1,2,3,4,5,6,7",
91 "Counter": "0,1,2,3,4,5,6,7",
101 "Counter": "0,1,2,3,4,5,6,7",
111 "Counter": "0,1,2,3,4,5,6,7",
121 "Counter": "0,1,2,3,4,5,6,7",
131 "Counter": "0,1,2,3,4,5,6,7",
141 "Counter": "0,1,2,3,4,5,6,7",
151 "Counter": "0,1,2,3,4,5,6,7",
160 "Counter": "0,1,2,3,4,5,6,7",
169 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
170 "Counter": "0,1,2,3,4,5,6,7",
180 "Counter": "0,1,2,3,4,5,6,7",
189 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
190 "Counter": "0,1,2,3,4,5,6,7",
194 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
200 "Counter": "0,1,2,3,4,5,6,7",
210 "Counter": "0,1,2,3,4,5,6,7",
220 "Counter": "0,1,2,3,4,5,6,7",
224 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
229 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
230 "Counter": "0,1,2,3,4,5,6,7",
233 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
238 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
239 "Counter": "0,1,2,3,4,5,6,7",
242 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
248 "Counter": "0,1,2,3,4,5,6,7",
257 "Counter": "0,1,2,3,4,5,6,7",
266 "Counter": "0,1,2,3,4,5,6,7",
275 "Counter": "0,1,2,3,4,5,6,7",
283 "Counter": "0,1,2,3,4,5,6,7",
293 "Counter": "0,1,2,3,4,5,6,7",
296 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
310 "Counter": "0,1,2,3,4,5,6,7",
327 "Counter": "0,1,2,3,4,5,6,7",
335 "Counter": "0,1,2,3",
344 "Counter": "0,1,2,3",
353 "Counter": "0,1,2,3,4,5,6,7",
362 "Counter": "0,1,2,3",
371 "Counter": "0,1,2,3",
380 "Counter": "0,1,2,3,4,5,6,7",
389 "Counter": "0,1,2,3,4,5,6,7",
397 …"BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station…
398 "Counter": "0,1,2,3,4,5,6,7",
406 "Counter": "0,1,2,3,4,5,6,7",
414 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
415 "Counter": "0,1,2,3,4,5,6,7",
417 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
418 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
424 "Counter": "0,1,2,3,4,5,6,7",
433 "Counter": "0,1,2,3,4,5,6,7",
442 "Counter": "0,1,2,3,4,5,6,7",
452 "Counter": "0,1,2,3,4,5,6,7",
461 "Counter": "0,1,2,3",
469 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
473 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
478 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
479 "Counter": "0,1,2,3,4,5,6,7",
483 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
488 "Counter": "0,1,2,3,4,5,6,7",
497 "Counter": "0,1,2,3,4,5,6,7",
506 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
516 "Counter": "0,1,2,3,4,5,6,7",
520 …imes as specified by the RCX register. Note the number of iterations is implementation-dependent.",
526 "Counter": "0,1,2,3,4,5,6,7",
537 "Counter": "0,1,2,3,4,5,6,7",
546 "Counter": "0,1,2,3,4,5,6,7",
554 "Counter": "0,1,2,3,4,5,6,7",
563 "Counter": "0,1,2,3,4,5,6,7",
573 "Counter": "0,1,2,3,4,5,6,7",
576 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
582 "Counter": "0,1,2,3,4,5,6,7",
590 "Counter": "0,1,2,3,4,5,6,7",
597 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
598 "Counter": "0,1,2,3,4,5,6,7",
601 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
606 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
607 "Counter": "0,1,2,3,4,5,6,7",
610 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
616 "Counter": "0,1,2,3,4,5,6,7",
624 "Counter": "0,1,2,3,4,5,6,7",
632 "Counter": "0,1,2,3,4,5,6,7",
640 "Counter": "0,1,2,3,4,5,6,7",
648 "Counter": "0,1,2,3",
657 "Counter": "0,1,2,3",
666 "Counter": "0,1,2,3",
675 "Counter": "0,1,2,3",
678 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
684 "Counter": "0,1,2,3,4,5,6,7",
688 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
694 "Counter": "0,1,2,3,4,5,6,7",
695 "CounterMask": "6",
698 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
704 "Counter": "0,1,2,3,4,5,6,7",
707 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
713 "Counter": "0,1,2,3,4,5,6,7",
723 "BriefDescription": "Self-modifying code (SMC) detected.",
724 "Counter": "0,1,2,3,4,5,6,7",
727 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
733 "Counter": "0,1,2,3,4,5,6,7",
742 "Counter": "0,1,2,3,4,5,6,7",
751 "Counter": "0,1,2,3,4,5,6,7",
754 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
760 "Counter": "0,1,2,3,4,5,6,7",
767 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
768 "Counter": "0,1,2,3,4,5,6,7",
771 …s in TMA method where no micro-operations were being issued from front-end to back-end of the mach…
780 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
789 …speculative operations that were issued but not retired as well as the out-of-order engine recover…
795 "Counter": "0,1,2,3,4,5,6,7",
802 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
803 "Counter": "Fixed counter 3",
805 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
810 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
811 "Counter": "0,1,2,3,4,5,6,7",
814 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
820 "Counter": "0,1,2,3",
828 "Counter": "0,1,2,3,4,5,6,7",
837 "Counter": "0,1,2,3,4,5,6,7",
845 "BriefDescription": "Uops executed on ports 2, 3 and 10",
846 "Counter": "0,1,2,3,4,5,6,7",
849 "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10",
855 "Counter": "0,1,2,3,4,5,6,7",
864 "Counter": "0,1,2,3,4,5,6,7",
872 "BriefDescription": "Uops executed on port 6",
873 "Counter": "0,1,2,3,4,5,6,7",
876 "PublicDescription": "Number of uops dispatch to execution port 6.",
882 "Counter": "0,1,2,3,4,5,6,7",
891 "Counter": "0,1,2,3,4,5,6,7",
899 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
900 "Counter": "0,1,2,3,4,5,6,7",
904 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
909 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
910 "Counter": "0,1,2,3,4,5,6,7",
914 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
919 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
920 "Counter": "0,1,2,3,4,5,6,7",
921 "CounterMask": "3",
924 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
929 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
930 "Counter": "0,1,2,3,4,5,6,7",
934 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
939 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
940 "Counter": "0,1,2,3,4,5,6,7",
944 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
949 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
950 "Counter": "0,1,2,3,4,5,6,7",
954 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
959 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
960 "Counter": "0,1,2,3,4,5,6,7",
961 "CounterMask": "3",
964 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
969 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
970 "Counter": "0,1,2,3,4,5,6,7",
974 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
980 "Counter": "0,1,2,3,4,5,6,7",
991 "Counter": "0,1,2,3,4,5,6,7",
1001 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1002 "Counter": "0,1,2,3,4,5,6,7",
1010 "Counter": "0,1,2,3,4,5,6,7",
1019 "Counter": "0,1,2,3,4,5,6,7",
1028 "Counter": "0,1,2,3,4,5,6,7",
1037 "Counter": "0,1,2,3,4,5,6,7",
1047 "Counter": "0,1,2,3,4,5,6,7",
1050 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1056 "Counter": "0,1,2,3,4,5,6,7",
1066 "Counter": "0,1,2,3,4,5,6,7",
1075 "Counter": "0,1,2,3,4,5,6,7",
1086 "Counter": "0,1,2,3,4,5,6,7",