Lines Matching +full:3 +full:- +full:line
4 "Counter": "0,1,2,3",
11 …ription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
12 "Counter": "0,1,2,3",
20 "Counter": "0,1,2,3",
27 "BriefDescription": "L1D data line replacements.",
28 "Counter": "0,1,2,3",
31 …event counts L1D data line replacements. Replacements occur when a new line is brought into the c…
37 "Counter": "0,1,2,3",
46 "Counter": "0,1,2,3",
82 "Counter": "0,1,2,3",
90 "Counter": "0,1,2,3",
98 "Counter": "0,1,2,3",
106 "Counter": "0,1,2,3",
113 …on": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the…
114 "Counter": "0,1,2,3",
122 "Counter": "0,1,2,3",
131 "Counter": "0,1,2,3",
139 "Counter": "0,1,2,3",
147 "Counter": "0,1,2,3",
155 "Counter": "0,1,2,3",
163 "Counter": "0,1,2,3",
171 "Counter": "0,1,2,3",
179 "Counter": "0,1,2,3",
187 "Counter": "0,1,2,3",
195 "Counter": "0,1,2,3",
203 "Counter": "0,1,2,3",
211 "Counter": "0,1,2,3",
219 "Counter": "0,1,2,3",
227 "Counter": "0,1,2,3",
235 "Counter": "0,1,2,3",
243 "Counter": "0,1,2,3",
251 "Counter": "0,1,2,3",
259 "Counter": "0,1,2,3",
267 "Counter": "0,1,2,3",
275 "Counter": "0,1,2,3",
283 "Counter": "0,1,2,3",
291 "Counter": "0,1,2,3",
299 "Counter": "0,1,2,3",
307 "Counter": "0,1,2,3",
315 "Counter": "0,1,2,3",
323 "Counter": "0,1,2,3",
331 "Counter": "0,1,2,3",
339 "Counter": "0,1,2,3",
347 "Counter": "0,1,2,3",
355 "Counter": "0,1,2,3",
363 "Counter": "0,1,2,3",
371 "Counter": "0,1,2,3",
379 "Counter": "0,1,2,3",
386 "BriefDescription": "Core-originated cacheable demand requests missed LLC.",
387 "Counter": "0,1,2,3",
394 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.",
395 "Counter": "0,1,2,3",
402 …d load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise E…
403 "Counter": "0,1,2,3",
407 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa…
412 …Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).",
413 "Counter": "0,1,2,3",
417 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa…
422 …d uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise …
423 "Counter": "0,1,2,3",
431 …ed load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).",
432 "Counter": "0,1,2,3",
440 … uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS).",
441 "Counter": "0,1,2,3",
445 …-level (L3) cache. This means that the load is usually satisfied from memory in a client system or…
450 … L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - …
451 "Counter": "0,1,2,3",
459 …"BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS).…
460 "Counter": "0,1,2,3",
468 …"BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS).…
469 "Counter": "0,1,2,3",
477 …ad uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS).",
478 "Counter": "0,1,2,3",
482 …t counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise…
487 "BriefDescription": "All retired load uops. (Precise Event - PEBS).",
488 "Counter": "0,1,2,3",
497 "BriefDescription": "All retired store uops. (Precise Event - PEBS).",
498 "Counter": "0,1,2,3",
502 … "PublicDescription": "This event counts the number of store uops retired. (Precise Event - PEBS)",
507 "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS).",
508 "Counter": "0,1,2,3",
516 …fDescription": "Retired load uops that split across a cacheline boundary. (Precise Event - PEBS).",
517 "Counter": "0,1,2,3",
521 …nts line-splitted load uops retired to the architected path. A line split is across 64B cache-line…
526 …Description": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS).",
527 "Counter": "0,1,2,3",
531 …ts line-splitted store uops retired to the architected path. A line split is across 64B cache-line…
536 "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS).",
537 "Counter": "0,1,2,3",
545 "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS).",
546 "Counter": "0,1,2,3",
555 "Counter": "0,1,2,3",
563 "Counter": "0,1,2,3",
571 "Counter": "0,1,2,3",
579 "Counter": "0,1,2,3",
587 "Counter": "0,1,2,3",
595 "Counter": "0,1,2,3",
603 "Counter": "0,1,2,3",
612 "Counter": "0,1,2,3",
621 "Counter": "0,1,2,3",
630 "Counter": "0,1,2,3",
638 "Counter": "0,1,2,3",
647 "Counter": "0,1,2,3",
654 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
655 "Counter": "0,1,2,3",
664 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
665 "Counter": "0,1,2,3",
675 "Counter": "0,1,2,3",
685 "Counter": "0,1,2,3",
695 "Counter": "0,1,2,3",
704 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
705 "Counter": "0,1,2,3",
714 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
715 "Counter": "0,1,2,3",
724 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
725 "Counter": "0,1,2,3",
735 "Counter": "0,1,2,3",
745 "Counter": "0,1,2,3",
754 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
755 "Counter": "0,1,2,3",
764 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
765 "Counter": "0,1,2,3",
774 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
775 "Counter": "0,1,2,3",
785 "Counter": "0,1,2,3",
795 "Counter": "0,1,2,3",
804 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
805 "Counter": "0,1,2,3",
814 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
815 "Counter": "0,1,2,3",
824 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
825 "Counter": "0,1,2,3",
835 "Counter": "0,1,2,3",
845 "Counter": "0,1,2,3",
854 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
855 "Counter": "0,1,2,3",
864 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
865 "Counter": "0,1,2,3",
874 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
875 "Counter": "0,1,2,3",
885 "Counter": "0,1,2,3",
895 "Counter": "0,1,2,3",
905 "Counter": "0,1,2,3",
914 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
915 "Counter": "0,1,2,3",
924 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
925 "Counter": "0,1,2,3",
934 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
935 "Counter": "0,1,2,3",
945 "Counter": "0,1,2,3",
955 "Counter": "0,1,2,3",
965 "Counter": "0,1,2,3",
974 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
975 "Counter": "0,1,2,3",
984 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
985 "Counter": "0,1,2,3",
994 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
995 "Counter": "0,1,2,3",
1005 "Counter": "0,1,2,3",
1015 "Counter": "0,1,2,3",
1025 "Counter": "0,1,2,3",
1035 "Counter": "0,1,2,3",
1045 "Counter": "0,1,2,3",
1054 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1055 "Counter": "0,1,2,3",
1064 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1065 "Counter": "0,1,2,3",
1074 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1075 "Counter": "0,1,2,3",
1085 "Counter": "0,1,2,3",
1095 "Counter": "0,1,2,3",
1105 "Counter": "0,1,2,3",
1114 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1115 "Counter": "0,1,2,3",
1124 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1125 "Counter": "0,1,2,3",
1134 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1135 "Counter": "0,1,2,3",
1145 "Counter": "0,1,2,3",
1155 "Counter": "0,1,2,3",
1165 "Counter": "0,1,2,3",
1174 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1175 "Counter": "0,1,2,3",
1184 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1185 "Counter": "0,1,2,3",
1194 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1195 "Counter": "0,1,2,3",
1205 "Counter": "0,1,2,3",
1215 "Counter": "0,1,2,3",
1224 …acheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted …
1225 "Counter": "0,1,2,3",
1234 …"BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core…
1235 "Counter": "0,1,2,3",
1245 "Counter": "0,1,2,3",
1255 "Counter": "0,1,2,3",
1265 "Counter": "0,1,2,3",
1274 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1275 "Counter": "0,1,2,3",
1284 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1285 "Counter": "0,1,2,3",
1294 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1295 "Counter": "0,1,2,3",
1305 "Counter": "0,1,2,3",
1315 "Counter": "0,1,2,3",
1324 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1325 "Counter": "0,1,2,3",
1334 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1335 "Counter": "0,1,2,3",
1344 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1345 "Counter": "0,1,2,3",
1355 "Counter": "0,1,2,3",
1365 "Counter": "0,1,2,3",
1374 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1375 "Counter": "0,1,2,3",
1384 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1385 "Counter": "0,1,2,3",
1394 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1395 "Counter": "0,1,2,3",
1405 "Counter": "0,1,2,3",
1415 "Counter": "0,1,2,3",
1424 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1425 "Counter": "0,1,2,3",
1434 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1435 "Counter": "0,1,2,3",
1444 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1445 "Counter": "0,1,2,3",
1455 "Counter": "0,1,2,3",
1465 "Counter": "0,1,2,3",
1474 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1475 "Counter": "0,1,2,3",
1484 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1485 "Counter": "0,1,2,3",
1494 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1495 "Counter": "0,1,2,3",
1505 "Counter": "0,1,2,3",
1515 "Counter": "0,1,2,3",
1524 …in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forw…
1525 "Counter": "0,1,2,3",
1534 …in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
1535 "Counter": "0,1,2,3",
1544 …nd sibling core snoops are not needed as either the core-valid bit is not set or the shared line i…
1545 "Counter": "0,1,2,3",
1555 "Counter": "0,1,2,3",
1565 "Counter": "0,1,2,3",
1575 "Counter": "0,1,2,3",
1584 …ts requests where the address of an atomic lock instruction spans a cache line boundary or the loc…
1585 "Counter": "0,1,2,3",
1594 "BriefDescription": "Counts non-temporal stores.",
1595 "Counter": "0,1,2,3",
1605 "Counter": "0,1,2,3",