Lines Matching full:average

707         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)",
721         "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details",
727         "BriefDescription": "Average number of Uops issued by front-end when it issued something",
733         "BriefDescription": "Average Latency for L1 instruction cache misses",
893         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
899         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
905         "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
911         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
923         "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
941         "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
983         "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
989         "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
1001         "BriefDescription": "Average Parallel L2 cache miss data reads",
1007         "BriefDescription": "Average Latency for L2 cache miss demand Loads",
1013         "BriefDescription": "Average Parallel L2 cache miss demand Loads",
1019         "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
1037         "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss",
1041         "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)"
1076         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per core",
1082         "BriefDescription": "Average number of uops fetched from DSB per cycle",
1088         "BriefDescription": "Average number of uops fetched from LSD per cycle",
1094         "BriefDescription": "Average number of uops fetched from MITE per cycle",
1108         "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired",
1114         "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]",
1120         "BriefDescription": "Average CPU Utilization (percentage)",
1126         "BriefDescription": "Average number of utilized CPUs",
1132         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
1136         "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_bottleneck_cache_memory_bandwidth, tma_fb_full, tma_mem_bandwidth, tma_sq_full"
1167         "BriefDescription": "Average number of parallel data read requests to external memory",
1171         "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches"
1174         "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)",
1178         "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)"
1236         "BriefDescription": "Average Frequency Utilization relative nominal frequency",