Lines Matching full:counters
18 … root operations. Accounts for integer and floating-point operations. Available PDIST counters: 0",
29 …cription": "This event counts the cycles the integer divider is busy. Available PDIST counters: 0",
39 … Examples include AD (page Access Dirty), FP and AVX related assists. Available PDIST counters: 0",
58 "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0",
76 …"PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0",
86 … "PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0",
105 …cDescription": "Counts taken conditional branch instructions retired. Available PDIST counters: 0",
124 "PublicDescription": "Counts far branch instructions retired. Available PDIST counters: 0",
143 …tructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: 0",
190 …on": "Counts both direct and indirect near call instructions retired. Available PDIST counters: 0",
209 "PublicDescription": "Counts return instructions retired. Available PDIST counters: 0",
228 … "PublicDescription": "Counts taken branch instructions retired. Available PDIST counters: 0",
265 …scarded, and the processor must start fetching from the correct path. Available PDIST counters: 0",
274 … on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
293 …ption": "Counts mispredicted conditional branch instructions retired. Available PDIST counters: 0",
303 … on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
313 …etired that were mispredicted and the branch direction was not taken. Available PDIST counters: 0",
323 … on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
342 …: "Counts taken conditional mispredicted branch instructions retired. Available PDIST counters: 0",
352 … on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
371 …tructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: 0",
390 …aken) CALL instructions, including both register and memory indirect. Available PDIST counters: 0",
400 … on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
410 … on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
438 …of near branch instructions retired that were mispredicted and taken. Available PDIST counters: 0",
448 … on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
458 …S) of the event that counts mispredicted return instructions retired. Available PDIST counters: 0",
477 … on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
487 …te. This state can be entered via the TPAUSE or UMWAIT instructions. Available PDIST counters: 0",
497 …te. This state can be entered via the TPAUSE or UMWAIT instructions. Available PDIST counters: 0",
507 …tes (TPAUSE or UMWAIT instructions) or running the PAUSE instruction. Available PDIST counters: 0",
533 … count when the Core is active, sum the counts from each hyperthread. Available PDIST counters: 0",
543 …ycles when current thread is unhalted and the other thread is halted. Available PDIST counters: 0",
553 "PublicDescription": "CPU_CLK_UNHALTED.PAUSE Available PDIST counters: 0",
565 "PublicDescription": "CPU_CLK_UNHALTED.PAUSE_INST Available PDIST counters: 0",
575 … count when the Core is active, sum the counts from each hyperthread. Available PDIST counters: 0",
592 …counters available for other events. Note: On all current platforms this event stops counting duri…
612 …counters available for other events. Note: On all current platforms this event stops counting duri…
629 …fixed counter, leaving the eight programmable counters available for other events. Available PDIST…
647 …this event may have a changing ratio with regards to wall clock time. Available PDIST counters: 0",
657 …Description": "Cycles while L1 cache miss demand load is outstanding. Available PDIST counters: 0",
668 …Description": "Cycles while L2 cache miss demand load is outstanding. Available PDIST counters: 0",
679 …Description": "Cycles while memory subsystem has an outstanding load. Available PDIST counters: 0",
690 …n": "Execution stalls while L1 cache miss demand load is outstanding. Available PDIST counters: 0",
701 …n": "Execution stalls while L2 cache miss demand load is outstanding. Available PDIST counters: 0",
712 "PublicDescription": "Total execution stalls. Available PDIST counters: 0",
722 …was executed on all ports and Reservation Station (RS) was not empty. Available PDIST counters: 0",
732 …are executed on all ports and Reservation Station (RS) was not empty. Available PDIST counters: 0",
742 …ere executed on all ports and Reservation Station (RS) was not empty. Available PDIST counters: 0",
752 …are executed on all ports and Reservation Station (RS) was not empty. Available PDIST counters: 0",
762 …are executed on all ports and Reservation Station (RS) was not empty. Available PDIST counters: 0",
773 …n": "Execution stalls while memory subsystem has an outstanding load. Available PDIST counters: 0",
784 …ere the Store Buffer was full and no loads caused an execution stall. Available PDIST counters: 0",
794 …the Store Buffer (SB) was not full and there was no outstanding load. Available PDIST counters: 0",
804 … a cycle when the MITE (legacy decode pipeline) fetches instructions. Available PDIST counters: 0",
813 …cription": "Fixed Counter: Counts the number of instructions retired Available PDIST counters: 32",
822 …ing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmabl…
840 …ED.ANY is counted by a designated fixed counter freeing up programmable counters to count other ev…
849 "PublicDescription": "INST_RETIRED.MACRO_FUSED Available PDIST counters: 0",
859 …: "Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions Available PDIST counters: 0",
868 …ias in how retired instructions get sampled. Use on Fixed Counter 0. Available PDIST counters: 32",
878 … register. Note the number of iterations is implementation-dependent. Available PDIST counters: 0",
890 …tive clears due to any type of branch misprediction or machine clears Available PDIST counters: 0",
900 …r machine clear till the first uop is issued from the resteered path. Available PDIST counters: 0",
910 …recovery from an earlier branch misprediction or machine clear event. Available PDIST counters: 0",
922 … "PublicDescription": "Bubble cycles of BAClear (Unknown Branch). Available PDIST counters: 0",
932 …itecture Analysis slots that got dropped due to non front-end reasons Available PDIST counters: 0",
942 "PublicDescription": "INT_VEC_RETIRED.128BIT Available PDIST counters: 0",
952 "PublicDescription": "INT_VEC_RETIRED.256BIT Available PDIST counters: 0",
962 …ger ADD/SUB (regular or horizontal), SAD 128-bit vector instructions. Available PDIST counters: 0",
972 …ger ADD/SUB (regular or horizontal), SAD 256-bit vector instructions. Available PDIST counters: 0",
982 "PublicDescription": "INT_VEC_RETIRED.MUL_256 Available PDIST counters: 0",
992 "PublicDescription": "INT_VEC_RETIRED.SHUFFLES Available PDIST counters: 0",
1002 "PublicDescription": "INT_VEC_RETIRED.VNNI_128 Available PDIST counters: 0",
1012 "PublicDescription": "INT_VEC_RETIRED.VNNI_256 Available PDIST counters: 0",
1031 …d due to false dependencies in MOB due to partial compare on address. Available PDIST counters: 0",
1050 …ked because all resources for handling the split accesses are in use. Available PDIST counters: 0",
1069 … the table of not supported store forwards in the Optimization Guide. Available PDIST counters: 0",
1079 …xcluded by ASM (Assembly File) inspection of the nearby instructions. Available PDIST counters: 0",
1090 …when at least one uop is delivered by the LSD (Loop-stream detector). Available PDIST counters: 0",
1101 …ptimal number of uops is delivered by the LSD (Loop-stream detector). Available PDIST counters: 0",
1111 …r of uops delivered to the back-end by the LSD(Loop Stream Detector). Available PDIST counters: 0",
1131 …scription": "Counts the number of machine clears (nukes) of any type. Available PDIST counters: 0",
1187 …nts self-modifying code (SMC) detected, which causes a machine clear. Available PDIST counters: 0",
1197 "PublicDescription": "number of LFENCE retired instructions Available PDIST counters: 0",
1216 …e via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT. Available PDIST counters: 0",
1226 …s that the pipeline back-end blocked uop delivery from the front-end. Available PDIST counters: 0",
1236 …s cycles where the pipeline is stalled due to serializing operations. Available PDIST counters: 0",
1246 …nto starvation periods (e.g. branch mispredictions or i-cache misses) Available PDIST counters: 0",
1259 … issues (see the FRONTEND_RETIRED event of designated precise events) Available PDIST counters: 0",
1269 …"Cycles when RS was empty and a resource allocation stall is asserted Available PDIST counters: 0",
1288 …op-level category) of the Top-down Microarchitecture Analysis method. Available PDIST counters: 0",
1298 …It covers all types of control-flow or data-related mis-speculations. Available PDIST counters: 0",
1308 …well as the out-of-order engine recovery past a branch misprediction. Available PDIST counters: 0",
1318 "PublicDescription": "TOPDOWN.MEMORY_BOUND_SLOTS Available PDIST counters: 0",
1327 …ral event is counted on a designated fixed counter (Fixed Counter 3). Available PDIST counters: 0",
1337 … logical processors (hyper-threads) who share the same physical core. Available PDIST counters: 0",
1594 … event counts the number of not dec-by-all uops decoded by decoder 0. Available PDIST counters: 0",
1604 … "PublicDescription": "Number of uops dispatch to execution port 0. Available PDIST counters: 0",
1614 … "PublicDescription": "Number of uops dispatch to execution port 1. Available PDIST counters: 0",
1624 …Description": "Number of uops dispatch to execution ports 2, 3 and 10 Available PDIST counters: 0",
1634 …blicDescription": "Number of uops dispatch to execution ports 4 and 9 Available PDIST counters: 0",
1644 …licDescription": "Number of uops dispatch to execution ports 5 and 11 Available PDIST counters: 0",
1654 … "PublicDescription": "Number of uops dispatch to execution port 6. Available PDIST counters: 0",
1664 …icDescription": "Number of uops dispatch to execution ports 7 and 8. Available PDIST counters: 0",
1674 …licDescription": "Counts the number of uops executed from any thread. Available PDIST counters: 0",
1685 …hen at least 1 micro-op is executed from any thread on physical core. Available PDIST counters: 0",
1696 …n at least 2 micro-ops are executed from any thread on physical core. Available PDIST counters: 0",
1707 …n at least 3 micro-ops are executed from any thread on physical core. Available PDIST counters: 0",
1718 …n at least 4 micro-ops are executed from any thread on physical core. Available PDIST counters: 0",
1729 …icDescription": "Cycles where at least 1 uop was executed per-thread. Available PDIST counters: 0",
1740 …Description": "Cycles where at least 2 uops were executed per-thread. Available PDIST counters: 0",
1751 …Description": "Cycles where at least 3 uops were executed per-thread. Available PDIST counters: 0",
1762 …Description": "Cycles where at least 4 uops were executed per-thread. Available PDIST counters: 0",
1774 …no uops were dispatched from the Reservation Station (RS) per thread. Available PDIST counters: 0",
1784 …on": "Counts the number of uops to be executed per-thread each cycle. Available PDIST counters: 0",
1794 "PublicDescription": "Counts the number of x87 uops executed. Available PDIST counters: 0",
1813 …source Allocation Table (RAT) issues to the Reservation Station (RS). Available PDIST counters: 0",
1824 "PublicDescription": "UOPS_ISSUED.CYCLES Available PDIST counters: 0",
1843 …ublicDescription": "Counts cycles where at least one uop has retired. Available PDIST counters: 0",
1853 … is decoded into less than two uops does not contribute to the count. Available PDIST counters: 0",
1883 "PublicDescription": "UOPS_RETIRED.MS Available PDIST counters: 0",
1893 …op-level category) of the Top-down Microarchitecture Analysis method. Available PDIST counters: 0",
1905 …escription": "This event counts cycles without actually retired uops. Available PDIST counters: 0",