Lines Matching +full:6 +full:a
4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
27 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
46 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
53 "Counter": "0,1,2,3,4,5,6,7",
66 "Counter": "0,1,2,3,4,5,6,7",
78 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
79 "Counter": "0,1,2,3,4,5,6,7",
85 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
92 "Counter": "0,1,2,3,4,5,6,7",
101 "Counter": "0,1,2,3,4,5,6,7",
114 "Counter": "0,1,2,3,4,5,6,7",
127 "Counter": "0,1,2,3,4,5,6,7",
140 "Counter": "0,1,2,3,4,5,6,7",
146 …rval where the front-end delivered no uops for a period of at least 1 cycle which was not interrup…
152 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
153 "Counter": "0,1,2,3,4,5,6,7",
159 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
165 …nterval where the front-end delivered no uops for a period of 16 cycles which was not interrupted …
166 "Counter": "0,1,2,3,4,5,6,7",
172 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
179 "Counter": "0,1,2,3,4,5,6,7",
185 …val where the front-end delivered no uops for a period of at least 2 cycles which was not interrup…
191 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
192 "Counter": "0,1,2,3,4,5,6,7",
198 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
204 …where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted …
205 "Counter": "0,1,2,3,4,5,6,7",
211 … the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-sl…
217 …nterval where the front-end delivered no uops for a period of 32 cycles which was not interrupted …
218 "Counter": "0,1,2,3,4,5,6,7",
224 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
230 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
231 "Counter": "0,1,2,3,4,5,6,7",
237 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
243 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
244 "Counter": "0,1,2,3,4,5,6,7",
250 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
256 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
257 "Counter": "0,1,2,3,4,5,6,7",
263 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
269 …interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted …
270 "Counter": "0,1,2,3,4,5,6,7",
276 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
283 "Counter": "0,1,2,3,4,5,6,7",
296 "Counter": "0,1,2,3,4,5,6,7",
308 "Counter": "0,1,2,3,4,5,6,7",
321 "Counter": "0,1,2,3,4,5,6,7",
332 …time the code stream enters into a new cache line by walking sequential from the previous line or …
333 "Counter": "0,1,2,3,4,5,6,7",
341 …time the code stream enters into a new cache line by walking sequential from the previous line or …
342 "Counter": "0,1,2,3,4,5,6,7",
350 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
354 …tion": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The …
371 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
375 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
394 "CounterMask": "6",
426 "CounterMask": "6",
478 …"BriefDescription": "This event counts a subset of the Topdown Slots event that when no operation …
479 "Counter": "0,1,2,3,4,5,6,7",
482 …"PublicDescription": "This event counts a subset of the Topdown Slots event that when no operation…
489 "Counter": "0,1,2,3,4,5,6,7",
490 "CounterMask": "6",
493 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…
500 "Counter": "0,1,2,3,4,5,6,7",
505 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…
512 "Counter": "0,1,2,3,4,5,6,7",
515 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
522 "Counter": "0,1,2,3,4,5,6,7",
523 "CounterMask": "6",
526 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…
533 "Counter": "0,1,2,3,4,5,6,7",
538 … when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This e…