Lines Matching +full:os +full:- +full:initiated
4 "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
11 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
18 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
25 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
76 …"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are r…
82 …"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are r…
88 …"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are …
94 …"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are …
100 …"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are …
264 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
295 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
321 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
338 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
344 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
349 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
355 "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
360 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
378 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
387 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
392 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
396 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
401 …"MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.…
419 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
420 "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
425 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
429 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
431 … (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L…
435 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
439 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
440 …"MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) /…
444 …"PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only activ…
459 …- CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound - tma_pmm_bound if #has_pme…
468 "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2",
481 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
486 …mask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLE…
490 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
494 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
499 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
508 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
522 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
532 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / tma…
537 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
542 "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
546 …t are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the n…
550 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
555 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
564 …ts. FP Assist may apply when working with very small floating point values (so-called Denormals).",
568 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
573 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
577 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
582 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
586 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
591 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
595 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
600 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
604 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
609 … approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May…
615 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
620 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
624 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
625 …"MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0…
630 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
643 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
648 …"PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative …
651 …"BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lowe…
679 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
692 … "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
694 …"MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_ut…
700 …"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch…
705 …"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetc…
708 …"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fet…
714 …"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fe…
717 …"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bott…
723 …"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bot…
726 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
734 …"BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset …
739 …"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset…
742 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottleneck…
747 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenec…
750 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
755 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks…
758 … "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
763 …ine cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as w…
766 …tch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the…
768 …- (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_…
779 …"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait tim…
782 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
788 …"Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related m…
792 …t_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (…
801 …"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispre…
808 "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
809 …"MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tm…
813 …aining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) a…
816 …"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring catego…
817 … "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIR…
829 "BriefDescription": "Fraction of branches that are non-taken conditionals",
842 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR…
848 …"MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_call…
859 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
877 …BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardles…
881 …-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width…
884 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
898 …tion": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_…
904 "BriefDescription": "Average number of Uops issued by front-end when it issued something",
916 …"BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurren…
962 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
967 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
970 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
975 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
978 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
983 …"PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means h…
986 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
991 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
994 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
999 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
1058 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
1064 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
1082 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
1088 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
1094 … instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
1100 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
1118 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
1137 …"MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.AL…
1154 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
1160 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
1196 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
1208 "BriefDescription": "Un-cacheable retired load per kilo instruction",
1214 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
1218 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
1221 … level TLB) code speculative misses per kilo instruction (misses of any page-size that complete th…
1227 …l TLB) data load speculative misses per kilo instruction (misses of any page-size that complete th…
1240 … TLB) data store speculative misses per kilo instruction (misses of any page-size that complete th…
1246 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
1307 …egate across all supported options of: FP precisions, scalar and vector instructions, vector-width"
1314 …isk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device co…
1321 …k) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device co…
1326 "MetricGroup": "Branches;OS",
1331 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
1333 "MetricGroup": "OS",
1337 "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
1339 "MetricGroup": "OS",
1348 …to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches"
1358 …"BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanose…
1362 …cy of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads …
1369 …y (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)"
1384 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for ba…
1388 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX…
1391 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1396 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct…
1399 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1404 …e the core was running with power-delivery for license level 2 (introduced in SKX). This includes…
1408 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_…
1431 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
1443 "BriefDescription": "The ratio of Executed- by Issued-Uops",
1447 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
1456 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
1462 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
1492 …"MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thr…
1496 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
1501 …EM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CY…
1505 …e L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access…
1511 …1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALL…
1521 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_c…
1547 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
1548 "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
1553 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
1566 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
1567 "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
1574 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
1593 …"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOC…
1602 "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
1607 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
1611 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
1616 …- DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic i…
1620 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1621 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1625 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1635 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
1639 … represents fraction of slots where the CPU was retiring memory operations -- uops for memory load…
1667 "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2",
1671 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
1676 …"MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / tma_info_thread…
1683 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1688 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1697 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
1706 …o op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address o…
1710 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1712 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_in…
1716 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1720 …action of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches …
1721 …"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_C…
1729 …"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT…
1736 … on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge…
1737 …- (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1…
1741 … on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge…
1781 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
1782 … tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALL…
1786 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
1795 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
1804 …-dependency among software instructions; or over oversubscribing a particular hardware resource. I…
1813 …cal Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options…
1831 …r sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocati…
1840 …ystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocati…
1846 …"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retir…
1851 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
1855 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
1860 …ycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; W…
1873 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1878 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1888 …resents rate of split store accesses. Consider aligning your data to the 64-byte cache line granu…
1892 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1897 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1901 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
1906 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
1916 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
1921 …"MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_ST…
1925 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
1938 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
1939 "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
1959 …uired by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there ar…
1982 "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)",
1989 "MetricExpr": "(cycles\\-t / el\\-start if has_event(el\\-start) else 0)",
1996 "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)",
2003 "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)",