Lines Matching +full:6 +full:- +full:3
4 "Counter": "0,1,2,3,4,5,6,7",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
14 "Counter": "0,1,2,3,4,5,6,7",
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
82 "Counter": "0,1,2,3,4,5,6,7",
92 "Counter": "0,1,2,3,4,5,6,7",
102 "Counter": "0,1,2,3,4,5,6,7",
112 "Counter": "0,1,2,3,4,5,6,7",
121 "Counter": "0,1,2,3,4,5,6,7",
130 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
131 "Counter": "0,1,2,3,4,5,6,7",
141 "Counter": "0,1,2,3,4,5,6,7",
150 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
151 "Counter": "0,1,2,3,4,5,6,7",
155 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
161 "Counter": "0,1,2,3,4,5,6,7",
171 "Counter": "0,1,2,3,4,5,6,7",
181 "Counter": "0,1,2,3,4,5,6,7",
185 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
191 "Counter": "0,1,2,3,4,5,6,7",
200 "Counter": "0,1,2,3,4,5,6,7",
209 "Counter": "0,1,2,3,4,5,6,7",
212 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
226 "Counter": "0,1,2,3,4,5,6,7",
243 "Counter": "0,1,2,3,4,5,6,7",
251 "Counter": "0,1,2,3",
260 "Counter": "0,1,2,3",
269 "Counter": "0,1,2,3,4,5,6,7",
278 "Counter": "0,1,2,3",
287 "Counter": "0,1,2,3",
296 "Counter": "0,1,2,3,4,5,6,7",
305 "Counter": "0,1,2,3,4,5,6,7",
314 "Counter": "0,1,2,3,4,5,6,7",
323 "Counter": "0,1,2,3,4,5,6,7",
331 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
332 "Counter": "0,1,2,3,4,5,6,7",
334 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
335 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
341 "Counter": "0,1,2,3,4,5,6,7",
350 "Counter": "0,1,2,3,4,5,6,7",
360 "Counter": "0,1,2,3",
363 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
369 "Counter": "0,1,2,3",
377 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
381 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
386 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
387 "Counter": "0,1,2,3,4,5,6,7",
391 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
396 "Counter": "0,1,2,3,4,5,6,7",
414 "Counter": "0,1,2,3,4,5,6,7",
424 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
425 "Counter": "0,1,2,3,4,5,6,7",
429 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
435 "Counter": "0,1,2,3,4,5,6,7",
446 "Counter": "0,1,2,3,4,5,6,7",
455 "Counter": "0,1,2,3,4,5,6,7",
464 "Counter": "0,1,2,3,4,5,6,7",
467 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
473 "Counter": "0,1,2,3",
482 "Counter": "0,1,2,3",
491 "Counter": "0,1,2,3",
500 "Counter": "0,1,2,3",
503 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
509 "Counter": "0,1,2,3",
513 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
519 "Counter": "0,1,2,3",
523 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
529 "Counter": "0,1,2,3",
532 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
538 "Counter": "0,1,2,3,4,5,6,7",
548 "BriefDescription": "Self-modifying code (SMC) detected.",
549 "Counter": "0,1,2,3,4,5,6,7",
552 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
558 "Counter": "0,1,2,3,4,5,6,7",
567 "Counter": "0,1,2,3,4,5,6,7",
576 "Counter": "0,1,2,3,4,5,6,7",
579 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
585 "Counter": "0,1,2,3,4,5,6,7",
593 "Counter": "0,1,2,3,4,5,6,7",
596 … This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch misp…
602 "Counter": "0,1,2,3,4,5,6,7",
608 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
613 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
614 "Counter": "0,1,2,3,4,5,6,7",
617 …-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued…
622 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
623 "Counter": "Fixed counter 3",
625 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
630 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
631 "Counter": "0,1,2,3,4,5,6,7",
634 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
640 "Counter": "0,1,2,3",
649 "Counter": "0,1,2,3,4,5,6,7",
652 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
658 "Counter": "0,1,2,3,4,5,6,7",
661 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
666 "BriefDescription": "Number of uops executed on port 2 and 3",
667 "Counter": "0,1,2,3,4,5,6,7",
670 …Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reser…
676 "Counter": "0,1,2,3,4,5,6,7",
679 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
685 "Counter": "0,1,2,3,4,5,6,7",
688 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
693 "BriefDescription": "Number of uops executed on port 6",
694 "Counter": "0,1,2,3,4,5,6,7",
697 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
703 "Counter": "0,1,2,3,4,5,6,7",
706 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
712 "Counter": "0,1,2,3,4,5,6,7",
720 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
721 "Counter": "0,1,2,3,4,5,6,7",
725 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
730 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
731 "Counter": "0,1,2,3,4,5,6,7",
735 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
740 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
741 "Counter": "0,1,2,3,4,5,6,7",
742 "CounterMask": "3",
745 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
750 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
751 "Counter": "0,1,2,3,4,5,6,7",
755 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
760 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
761 "Counter": "0,1,2,3,4,5,6,7",
765 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
770 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
771 "Counter": "0,1,2,3,4,5,6,7",
775 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
780 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
781 "Counter": "0,1,2,3,4,5,6,7",
782 "CounterMask": "3",
785 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
790 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
791 "Counter": "0,1,2,3,4,5,6,7",
795 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
801 "Counter": "0,1,2,3,4,5,6,7",
811 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
812 "Counter": "0,1,2,3,4,5,6,7",
820 "Counter": "0,1,2,3,4,5,6,7",
829 "Counter": "0,1,2,3,4,5,6,7",
838 "Counter": "0,1,2,3,4,5,6,7",
848 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
849 "Counter": "0,1,2,3,4,5,6,7",
852 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
858 "Counter": "0,1,2,3,4,5,6,7",
867 "Counter": "0,1,2,3,4,5,6,7",
878 "Counter": "0,1,2,3,4,5,6,7",