Lines Matching +full:per +full:- +full:rate
3 "BriefDescription": "C10 residency percent per package",
4 "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
10 "BriefDescription": "C2 residency percent per package",
11 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
17 "BriefDescription": "C3 residency percent per package",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
24 "BriefDescription": "C6 residency percent per core",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
31 "BriefDescription": "C6 residency percent per package",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
38 "BriefDescription": "C7 residency percent per core",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
45 "BriefDescription": "C7 residency percent per package",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
52 "BriefDescription": "C8 residency percent per package",
53 "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
59 "BriefDescription": "C9 residency percent per package",
60 "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
66 "BriefDescription": "Uncore frequency per die [GHZ]",
73 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
93 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
110 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
116 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
121 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
127 "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
132 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
136 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
143 …"BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset …
148 …"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset…
151 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottleneck…
156 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenec…
159 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
164 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks…
167 … "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
172 …ine cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as w…
175 …tch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the…
176 …- (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_…
187 …"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait tim…
190 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
195 …"Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related m…
199 …t_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (…
207 …"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispre…
214 "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
215 …"MetricExpr": "100 - (tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottlene…
219 …aining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) a…
222 …"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring catego…
223 … "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIR…
243 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
252 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
257 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
261 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
266 …"MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.…
275 "MetricExpr": "max(0, tma_icache_misses - tma_code_l2_miss)",
290 …irst level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)",
291 "MetricExpr": "max(0, tma_itlb_misses - tma_code_stlb_miss)",
298 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
332 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
333 "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
338 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
342 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
348 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
352 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
353 …"MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) /…
357 …"PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only activ…
372 …o_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread…
381 "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2",
394 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
399 …mask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLE…
403 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
407 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
412 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
421 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
435 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
445 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / tma…
450 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
455 "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
459 …tiring instructions that that are decoder into two or more uops. This highly-correlates with the n…
463 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
468 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
477 …ts. FP Assist may apply when working with very small floating point values (so-called Denormals).",
481 …"BriefDescription": "This metric represents fraction of cycles where the Floating-Point Divider un…
489 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
494 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
498 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
503 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
507 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
512 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
516 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
521 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
525 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
530 … approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May…
536 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
541 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
545 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
546 …"MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0…
551 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
564 …ch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch…
569 …ch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch…
572 …scription": "Instructions per retired Mispredicts for conditional non-taken branches (lower number…
579 …Description": "Instructions per retired Mispredicts for conditional taken branches (lower number m…
586 …scription": "Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number …
593 …BriefDescription": "Instructions per retired Mispredicts for return branches (lower number means h…
600 …ion": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number mea…
613 … "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
615 …"MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_ut…
621 …"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch…
626 …"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetc…
629 …"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fet…
635 …"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fe…
638 …"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bott…
644 …"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bot…
653 "BriefDescription": "Fraction of branches that are non-taken conditionals",
666 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR…
672 …"MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_call…
683 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
689 "BriefDescription": "uops Executed per Cycle",
695 "BriefDescription": "Floating Point Operations Per Cycle",
701 …"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardle…
705 …per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-wi…
708 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
722 …tion": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_…
728 "BriefDescription": "Average number of Uops issued by front-end when it issued something",
740 …"BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurren…
747 …Description": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number m…
753 "BriefDescription": "L2 cache true code cacheline misses per kilo instruction",
759 "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction",
771 "BriefDescription": "Taken Branches retired Per Cycle",
777 "BriefDescription": "Branch instructions per taken branch.",
790 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
795 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
798 …riefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means …
803 …blicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means …
806 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
811 …PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
814 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
819 …PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
822 …Description": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number me…
827 …Description": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number me…
830 …Description": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number me…
835 …Description": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number me…
838 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
845 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
852 …"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occ…
859 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
866 "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)",
872 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
879 …ion": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower …
886 "BriefDescription": "Instructions per taken branch",
891 …"PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_…
894 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
900 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
906 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
912 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
918 …iption": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that me…
924 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
930 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
936 …"BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including spe…
942 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
948 …"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculati…
954 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
960 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (inc…
961 …"MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.AL…
966 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (inc…
972 "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
978 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
984 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
990 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
1014 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
1020 "BriefDescription": "\"Bus lock\" per kilo instruction",
1026 "BriefDescription": "Un-cacheable retired load per kilo instruction",
1032 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
1036 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
1039 "BriefDescription": "Rate of L2 HW prefetched lines that were not used by demand accesses",
1046 …ription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-s…
1052 …on": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-s…
1065 …n": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-s…
1077 "BriefDescription": "Average number of uops fetched from DSB per cycle",
1083 "BriefDescription": "Average number of uops fetched from LSD per cycle",
1089 "BriefDescription": "Average number of uops fetched from MITE per cycle",
1095 "BriefDescription": "Instructions per a microcode Assist invocation",
1100 …tion": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower n…
1134 "BriefDescription": "Giga Floating Point Operations Per Second",
1138 …ting Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar…
1141 …per Far Branch ( Far Branches apply upon transition from application to operating system, handling…
1148 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
1169 "MetricExpr": "power@energy\\-pkg@ * 61 / (tma_info_system_time * 1e6)",
1174 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for ba…
1178 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX…
1181 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1186 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct…
1189 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1194 …e the core was running with power-delivery for license level 2 (introduced in SKX). This includes…
1198 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_…
1222 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
1228 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
1234 "BriefDescription": "The ratio of Executed- by Issued-Uops",
1238 …ion": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. R…
1241 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
1247 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
1253 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
1259 "BriefDescription": "Uops Per Instruction",
1266 "BriefDescription": "Uops per taken branch",
1274 "MetricExpr": "tma_divider - tma_fp_divider",
1291 …"MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thr…
1295 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
1300 …EM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CY…
1304 … the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access…
1310 …1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALL…
1329 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_c…
1355 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
1356 "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
1361 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
1374 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
1375 "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
1382 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
1416 …"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOC…
1425 "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core_core_clks / 2",
1429 …ly does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be…
1434 "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
1439 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
1443 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
1448 …- DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic i…
1452 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1453 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1457 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1467 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
1471 … represents fraction of slots where the CPU was retiring memory operations -- uops for memory load…
1499 "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2",
1503 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
1508 …"MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / tma_info_thread…
1515 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1520 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1524 …es in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequen…
1537 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
1546 …o op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address o…
1550 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1552 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_in…
1556 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1560 …action of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches …
1561 …"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_C…
1569 …"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT…
1612 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
1613 … tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALL…
1617 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
1626 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
1630 …metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execut…
1635 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
1639 …": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execut…
1644 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
1648 … metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execut…
1653 … metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execut…
1659 …"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retir…
1664 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
1668 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
1673 …ycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; W…
1686 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1691 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1695 "BriefDescription": "This metric represents rate of split store accesses",
1701 …blicDescription": "This metric represents rate of split store accesses. Consider aligning your da…
1705 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1710 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1714 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
1719 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
1729 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
1734 …"MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_ST…
1738 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
1751 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
1752 "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
1796 …uired by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there ar…
1819 "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)",
1826 "MetricExpr": "(cycles\\-t / el\\-start if has_event(el\\-start) else 0)",
1833 "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)",
1840 "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)",