Lines Matching +full:7 +full:- +full:3
4 "Counter": "0,1,2,3,4,5,6,7",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
14 "Counter": "0,1,2,3,4,5,6,7",
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3,4,5,6,7",
81 "Counter": "0,1,2,3,4,5,6,7",
91 "Counter": "0,1,2,3,4,5,6,7",
101 "Counter": "0,1,2,3,4,5,6,7",
111 "Counter": "0,1,2,3,4,5,6,7",
121 "Counter": "0,1,2,3,4,5,6,7",
130 "Counter": "0,1,2,3,4,5,6,7",
139 "Counter": "0,1,2,3,4,5,6,7",
149 "Counter": "0,1,2,3,4,5,6,7",
157 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
158 "Counter": "0,1,2,3,4,5,6,7",
167 …"BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise …
168 "Counter": "0,1,2,3,4,5,6,7",
177 "Counter": "0,1,2,3,4,5,6,7",
187 "Counter": "0,1,2,3,4,5,6,7",
195 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
196 "Counter": "0,1,2,3,4,5,6,7",
200 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
206 "Counter": "0,1,2,3,4,5,6,7",
216 "Counter": "0,1,2,3,4,5,6,7",
225 "Counter": "0,1,2,3,4,5,6,7",
234 "Counter": "0,1,2,3,4,5,6,7",
244 "Counter": "0,1,2,3,4,5,6,7",
253 "Counter": "0,1,2,3,4,5,6,7",
257 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
263 "Counter": "0,1,2,3,4,5,6,7",
271 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
272 "Counter": "0,1,2,3,4,5,6,7",
275 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
280 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
281 "Counter": "0,1,2,3,4,5,6,7",
284 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
290 "Counter": "0,1,2,3,4,5,6,7",
299 "Counter": "0,1,2,3,4,5,6,7",
308 "Counter": "0,1,2,3,4,5,6,7",
317 "Counter": "0,1,2,3,4,5,6,7",
325 "Counter": "0,1,2,3,4,5,6,7",
335 "Counter": "0,1,2,3,4,5,6,7",
338 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
352 "Counter": "0,1,2,3,4,5,6,7",
369 "Counter": "0,1,2,3,4,5,6,7",
377 "Counter": "0,1,2,3",
386 "Counter": "0,1,2,3",
395 "Counter": "0,1,2,3,4,5,6,7",
404 "Counter": "0,1,2,3",
413 "Counter": "0,1,2,3",
422 "Counter": "0,1,2,3,4,5,6,7",
431 "Counter": "0,1,2,3,4,5,6,7",
439 …"BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station…
440 "Counter": "0,1,2,3,4,5,6,7",
448 "Counter": "0,1,2,3,4,5,6,7",
456 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
457 "Counter": "0,1,2,3,4,5,6,7",
459 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
460 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
466 "Counter": "0,1,2,3,4,5,6,7",
475 "Counter": "0,1,2,3,4,5,6,7",
484 "Counter": "0,1,2,3,4,5,6,7",
494 "Counter": "0,1,2,3,4,5,6,7",
503 "Counter": "0,1,2,3",
511 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
515 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
520 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
521 "Counter": "0,1,2,3,4,5,6,7",
525 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
530 "Counter": "0,1,2,3,4,5,6,7",
539 "Counter": "0,1,2,3,4,5,6,7",
548 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
558 "Counter": "0,1,2,3,4,5,6,7",
562 …imes as specified by the RCX register. Note the number of iterations is implementation-dependent.",
568 "Counter": "0,1,2,3,4,5,6,7",
579 "Counter": "0,1,2,3,4,5,6,7",
588 "Counter": "0,1,2,3,4,5,6,7",
596 "Counter": "0,1,2,3,4,5,6,7",
605 "Counter": "0,1,2,3,4,5,6,7",
615 "Counter": "0,1,2,3,4,5,6,7",
618 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
624 "Counter": "0,1,2,3,4,5,6,7",
632 "Counter": "0,1,2,3,4,5,6,7",
639 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
640 "Counter": "0,1,2,3,4,5,6,7",
643 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
648 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
649 "Counter": "0,1,2,3,4,5,6,7",
652 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
658 "Counter": "0,1,2,3,4,5,6,7",
666 "Counter": "0,1,2,3,4,5,6,7",
674 "Counter": "0,1,2,3,4,5,6,7",
682 "Counter": "0,1,2,3,4,5,6,7",
690 "Counter": "0,1,2,3",
699 "Counter": "0,1,2,3",
708 "Counter": "0,1,2,3",
717 "Counter": "0,1,2,3",
720 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
726 "Counter": "0,1,2,3,4,5,6,7",
730 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
736 "Counter": "0,1,2,3,4,5,6,7",
740 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
746 "Counter": "0,1,2,3,4,5,6,7",
749 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
755 "Counter": "0,1,2,3,4,5,6,7",
765 "BriefDescription": "Self-modifying code (SMC) detected.",
766 "Counter": "0,1,2,3,4,5,6,7",
769 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
775 "Counter": "0,1,2,3,4,5,6,7",
784 "Counter": "0,1,2,3,4,5,6,7",
793 "Counter": "0,1,2,3,4,5,6,7",
800 … the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end r…
801 "Counter": "0,1,2,3,4,5,6,7",
804 …-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution…
813 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
822 …speculative operations that were issued but not retired as well as the out-of-order engine recover…
828 "Counter": "0,1,2,3,4,5,6,7",
835 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
836 "Counter": "Fixed counter 3",
838 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
843 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
844 "Counter": "0,1,2,3,4,5,6,7",
847 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
852 "BriefDescription": "Number of non dec-by-all uops decoded by decoder",
853 "Counter": "0,1,2,3",
856 … "PublicDescription": "This event counts the number of not dec-by-all uops decoded by decoder 0.",
862 "Counter": "0,1,2,3,4,5,6,7",
871 "Counter": "0,1,2,3,4,5,6,7",
879 "BriefDescription": "Uops executed on ports 2, 3 and 10",
880 "Counter": "0,1,2,3,4,5,6,7",
883 "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10",
889 "Counter": "0,1,2,3,4,5,6,7",
898 "Counter": "0,1,2,3,4,5,6,7",
907 "Counter": "0,1,2,3,4,5,6,7",
915 "BriefDescription": "Uops executed on ports 7 and 8",
916 "Counter": "0,1,2,3,4,5,6,7",
919 "PublicDescription": "Number of uops dispatch to execution ports 7 and 8.",
925 "Counter": "0,1,2,3,4,5,6,7",
933 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
934 "Counter": "0,1,2,3,4,5,6,7",
938 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
943 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
944 "Counter": "0,1,2,3,4,5,6,7",
948 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
953 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
954 "Counter": "0,1,2,3,4,5,6,7",
955 "CounterMask": "3",
958 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
963 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
964 "Counter": "0,1,2,3,4,5,6,7",
968 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
973 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
974 "Counter": "0,1,2,3,4,5,6,7",
978 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
983 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
984 "Counter": "0,1,2,3,4,5,6,7",
988 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
993 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
994 "Counter": "0,1,2,3,4,5,6,7",
995 "CounterMask": "3",
998 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1003 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1004 "Counter": "0,1,2,3,4,5,6,7",
1008 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1014 "Counter": "0,1,2,3,4,5,6,7",
1024 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1025 "Counter": "0,1,2,3,4,5,6,7",
1033 "Counter": "0,1,2,3,4,5,6,7",
1042 "Counter": "0,1,2,3,4,5,6,7",
1051 "Counter": "0,1,2,3,4,5,6,7",
1060 "Counter": "0,1,2,3,4,5,6,7",
1070 "Counter": "0,1,2,3,4,5,6,7",
1073 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1079 "Counter": "0,1,2,3,4,5,6,7",
1088 …orrelates with higher performance for example, as measured by the instructions-per-cycle metric.",
1089 "Counter": "0,1,2,3,4,5,6,7",
1092 …he instructions-per-cycle metric. Software can use this event as the numerator for the Retiring me…
1098 "Counter": "0,1,2,3,4,5,6,7",