Lines Matching +full:3 +full:- +full:7
4 "Counter": "0,1,2,3,4,5,6,7",
8 …xecuting divide or square root operations. Accounts for integer and floating-point operations. Ava…
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
50 "Counter": "0,1,2,3,4,5,6,7",
59 "Counter": "0,1,2,3,4,5,6,7",
68 "Counter": "0,1,2,3,4,5,6,7",
77 "Counter": "0,1,2,3,4,5,6,7",
86 "Counter": "0,1,2,3,4,5,6,7",
95 "Counter": "0,1,2,3,4,5,6,7",
104 "Counter": "0,1,2,3,4,5,6,7",
113 "Counter": "0,1,2,3,4,5,6,7",
121 "Counter": "0,1,2,3,4,5,6,7",
130 "Counter": "0,1,2,3,4,5,6,7",
139 "Counter": "0,1,2,3,4,5,6,7",
147 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
148 "Counter": "0,1,2,3,4,5,6,7",
156 …"BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise …
157 "Counter": "0,1,2,3,4,5,6,7",
160 …"PublicDescription": "Mispredicted non-taken conditional branch instructions retired. This precise…
169 "Counter": "0,1,2,3,4,5,6,7",
178 "Counter": "0,1,2,3,4,5,6,7",
189 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
190 "Counter": "0,1,2,3,4,5,6,7",
193 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
199 "Counter": "0,1,2,3,4,5,6,7",
208 "Counter": "0,1,2,3,4,5,6,7",
220 "Counter": "0,1,2,3,4,5,6,7",
232 "Counter": "0,1,2,3,4,5,6,7",
241 "Counter": "0,1,2,3,4,5,6,7",
250 "Counter": "0,1,2,3,4,5,6,7",
253 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
259 "Counter": "0,1,2,3,4,5,6,7",
270 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
271 "Counter": "0,1,2,3,4,5,6,7",
274 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
279 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
280 "Counter": "0,1,2,3,4,5,6,7",
283 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
289 "Counter": "0,1,2,3,4,5,6,7",
298 "Counter": "0,1,2,3,4,5,6,7",
307 "Counter": "0,1,2,3,4,5,6,7",
316 "Counter": "0,1,2,3,4,5,6,7",
325 "Counter": "0,1,2,3,4,5,6,7",
336 "Counter": "0,1,2,3,4,5,6,7",
339 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
353 "Counter": "0,1,2,3,4,5,6,7",
370 "Counter": "0,1,2,3,4,5,6,7",
378 "Counter": "0,1,2,3",
388 "Counter": "0,1,2,3",
398 "Counter": "0,1,2,3,4,5,6,7",
408 "Counter": "0,1,2,3",
418 "Counter": "0,1,2,3",
428 "Counter": "0,1,2,3,4,5,6,7",
438 "Counter": "0,1,2,3,4,5,6,7",
447 "Counter": "0,1,2,3,4,5,6,7",
455 …"BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station…
456 "Counter": "0,1,2,3,4,5,6,7",
459 …"PublicDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Statio…
465 "Counter": "0,1,2,3,4,5,6,7",
473 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
474 "Counter": "0,1,2,3,4,5,6,7",
476 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
477 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
483 "Counter": "0,1,2,3,4,5,6,7",
492 "Counter": "0,1,2,3,4,5,6,7",
502 "Counter": "0,1,2,3,4,5,6,7",
512 "Counter": "0,1,2,3,4,5,6,7",
521 "Counter": "0,1,2,3",
529 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
532 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
537 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
538 "Counter": "0,1,2,3,4,5,6,7",
541 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
546 "Counter": "0,1,2,3,4,5,6,7",
555 "Counter": "0,1,2,3,4,5,6,7",
563 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
572 "Counter": "0,1,2,3,4,5,6,7",
575 …ecified by the RCX register. Note the number of iterations is implementation-dependent. Available …
581 "Counter": "0,1,2,3,4,5,6,7",
592 "Counter": "0,1,2,3,4,5,6,7",
601 "Counter": "0,1,2,3,4,5,6,7",
610 "Counter": "0,1,2,3,4,5,6,7",
619 "Counter": "0,1,2,3,4,5,6,7",
630 "Counter": "0,1,2,3,4,5,6,7",
633 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
639 "Counter": "0,1,2,3,4,5,6,7",
648 "Counter": "0,1,2,3,4,5,6,7",
656 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
657 "Counter": "0,1,2,3,4,5,6,7",
660 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
665 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
666 "Counter": "0,1,2,3,4,5,6,7",
669 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
675 "Counter": "0,1,2,3,4,5,6,7",
684 "Counter": "0,1,2,3,4,5,6,7",
693 "Counter": "0,1,2,3,4,5,6,7",
702 "Counter": "0,1,2,3,4,5,6,7",
711 "Counter": "0,1,2,3",
720 "Counter": "0,1,2,3",
729 "Counter": "0,1,2,3",
738 "Counter": "0,1,2,3",
741 …"PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) a…
747 "Counter": "0,1,2,3,4,5,6,7",
751 …ion": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector). Ava…
757 "Counter": "0,1,2,3,4,5,6,7",
761 …"Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector). Ava…
767 "Counter": "0,1,2,3,4,5,6,7",
770 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
776 "Counter": "0,1,2,3,4,5,6,7",
786 "BriefDescription": "Self-modifying code (SMC) detected.",
787 "Counter": "0,1,2,3,4,5,6,7",
790 …"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear. Ava…
796 "Counter": "0,1,2,3,4,5,6,7",
805 "Counter": "0,1,2,3,4,5,6,7",
814 "Counter": "0,1,2,3,4,5,6,7",
817 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
823 "Counter": "0,1,2,3,4,5,6,7",
832 "Counter": "0,1,2,3,4,5,6,7",
835 … This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch misp…
841 "Counter": "0,1,2,3,4,5,6,7",
847 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
853 "Counter": "0,1,2,3,4,5,6,7",
861 … the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end r…
862 "Counter": "0,1,2,3,4,5,6,7",
865 …-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution…
874 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
883 …speculative operations that were issued but not retired as well as the out-of-order engine recover…
889 "Counter": "0,1,2,3,4,5,6,7",
897 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
898 "Counter": "Fixed counter 3",
900 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
905 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
906 "Counter": "0,1,2,3,4,5,6,7",
909 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
914 "BriefDescription": "Number of non dec-by-all uops decoded by decoder",
915 "Counter": "0,1,2,3",
918 …"PublicDescription": "This event counts the number of not dec-by-all uops decoded by decoder 0. Av…
924 "Counter": "0,1,2,3,4,5,6,7",
933 "Counter": "0,1,2,3,4,5,6,7",
941 "BriefDescription": "Uops executed on ports 2, 3 and 10",
942 "Counter": "0,1,2,3,4,5,6,7",
945 …"PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10 Available PDIST count…
951 "Counter": "0,1,2,3,4,5,6,7",
960 "Counter": "0,1,2,3,4,5,6,7",
969 "Counter": "0,1,2,3,4,5,6,7",
977 "BriefDescription": "Uops executed on ports 7 and 8",
978 "Counter": "0,1,2,3,4,5,6,7",
981 …"PublicDescription": "Number of uops dispatch to execution ports 7 and 8. Available PDIST counter…
987 "Counter": "0,1,2,3,4,5,6,7",
995 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
996 "Counter": "0,1,2,3,4,5,6,7",
1000 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
1005 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1006 "Counter": "0,1,2,3,4,5,6,7",
1010 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
1015 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1016 "Counter": "0,1,2,3,4,5,6,7",
1017 "CounterMask": "3",
1020 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
1025 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1026 "Counter": "0,1,2,3,4,5,6,7",
1030 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
1035 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1036 "Counter": "0,1,2,3,4,5,6,7",
1040 …"PublicDescription": "Cycles where at least 1 uop was executed per-thread. Available PDIST counter…
1045 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1046 "Counter": "0,1,2,3,4,5,6,7",
1050 …"PublicDescription": "Cycles where at least 2 uops were executed per-thread. Available PDIST count…
1055 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1056 "Counter": "0,1,2,3,4,5,6,7",
1057 "CounterMask": "3",
1060 …"PublicDescription": "Cycles where at least 3 uops were executed per-thread. Available PDIST count…
1065 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1066 "Counter": "0,1,2,3,4,5,6,7",
1070 …"PublicDescription": "Cycles where at least 4 uops were executed per-thread. Available PDIST count…
1076 "Counter": "0,1,2,3,4,5,6,7",
1086 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1087 "Counter": "0,1,2,3,4,5,6,7",
1090 …"PublicDescription": "Counts the number of uops to be executed per-thread each cycle. Available PD…
1096 "Counter": "0,1,2,3,4,5,6,7",
1105 "Counter": "0,1,2,3,4,5,6,7",
1114 "Counter": "0,1,2,3,4,5,6,7",
1124 "Counter": "0,1,2,3,4,5,6,7",
1134 "Counter": "0,1,2,3,4,5,6,7",
1137 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1143 "Counter": "0,1,2,3,4,5,6,7",
1153 …orrelates with higher performance for example, as measured by the instructions-per-cycle metric.",
1154 "Counter": "0,1,2,3,4,5,6,7",
1157 …he instructions-per-cycle metric. Software can use this event as the numerator for the Retiring me…
1163 "Counter": "0,1,2,3,4,5,6,7",