Lines Matching +full:2 +full:- +full:6
4 "Counter": "0,1,2,3,4,5,6,7",
8 "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations. Available PDIST counters: 0",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
50 "Counter": "0,1,2,3,4,5,6,7",
59 "Counter": "0,1,2,3,4,5,6,7",
68 "Counter": "0,1,2,3,4,5,6,7",
77 "Counter": "0,1,2,3,4,5,6,7",
86 "Counter": "0,1,2,3,4,5,6,7",
95 "Counter": "0,1,2,3,4,5,6,7",
104 "Counter": "0,1,2,3,4,5,6,7",
113 "Counter": "0,1,2,3,4,5,6,7",
121 "Counter": "0,1,2,3,4,5,6,7",
130 "Counter": "0,1,2,3,4,5,6,7",
139 "Counter": "0,1,2,3,4,5,6,7",
147 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
148 "Counter": "0,1,2,3,4,5,6,7",
156 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
157 "Counter": "0,1,2,3,4,5,6,7",
160 "PublicDescription": "Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
169 "Counter": "0,1,2,3,4,5,6,7",
178 "Counter": "0,1,2,3,4,5,6,7",
189 "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
190 "Counter": "0,1,2,3,4,5,6,7",
193 "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: 0",
199 "Counter": "0,1,2,3,4,5,6,7",
208 "Counter": "0,1,2,3,4,5,6,7",
220 "Counter": "0,1,2,3,4,5,6,7",
232 "Counter": "0,1,2,3,4,5,6,7",
241 "Counter": "0,1,2,3,4,5,6,7",
250 "Counter": "0,1,2,3,4,5,6,7",
253 "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. Available PDIST counters: 0",
259 "Counter": "0,1,2,3,4,5,6,7",
270 "BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.",
271 "Counter": "0,1,2,3,4,5,6,7",
274 "PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions. Available PDIST counters: 0",
279 "BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.",
280 "Counter": "0,1,2,3,4,5,6,7",
283 "PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions. Available PDIST counters: 0",
288 "BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.",
289 "Counter": "0,1,2,3,4,5,6,7",
292 "PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction. Available PDIST counters: 0",
298 "Counter": "0,1,2,3,4,5,6,7",
307 "Counter": "0,1,2,3,4,5,6,7",
316 "Counter": "0,1,2,3,4,5,6,7",
325 "Counter": "0,1,2,3,4,5,6,7",
336 "Counter": "0,1,2,3,4,5,6,7",
339 "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread. Available PDIST counters: 0",
345 "Counter": "Fixed counter 2",
353 "Counter": "0,1,2,3,4,5,6,7",
370 "Counter": "0,1,2,3,4,5,6,7",
378 "Counter": "0,1,2,3",
388 "Counter": "0,1,2,3",
398 "Counter": "0,1,2,3,4,5,6,7",
408 "Counter": "0,1,2,3",
418 "Counter": "0,1,2,3",
428 "Counter": "0,1,2,3,4,5,6,7",
438 "Counter": "0,1,2,3,4,5,6,7",
447 "Counter": "0,1,2,3,4,5,6,7",
455 "BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
456 "Counter": "0,1,2,3,4,5,6,7",
458 "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL",
459 "PublicDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty. Available PDIST counters: 0",
464 "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
465 "Counter": "0,1,2,3,4,5,6,7",
467 "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
468 "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty. Available PDIST counters: 0",
474 "Counter": "0,1,2,3,4,5,6,7",
483 "Counter": "0,1,2,3,4,5,6,7",
492 "Counter": "0,1,2,3,4,5,6,7",
502 "Counter": "0,1,2,3,4,5,6,7",
503 "CounterMask": "2",
512 "Counter": "0,1,2,3,4,5,6,7",
521 "Counter": "0,1,2,3",
529 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
532 "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. Available PDIST counters: 32",
537 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
538 "Counter": "0,1,2,3,4,5,6,7",
541 "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
546 "Counter": "0,1,2,3,4,5,6,7",
555 "Counter": "0,1,2,3,4,5,6,7",
563 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
572 "Counter": "0,1,2,3,4,5,6,7",
575 "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent. Available PDIST counters: 0",
581 "Counter": "0,1,2,3,4,5,6,7",
592 "Counter": "0,1,2,3,4,5,6,7",
601 "Counter": "0,1,2,3,4,5,6,7",
610 "Counter": "0,1,2,3,4,5,6,7",
619 "Counter": "0,1,2,3,4,5,6,7",
630 "Counter": "0,1,2,3,4,5,6,7",
633 "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons Available PDIST counters: 0",
639 "Counter": "0,1,2,3,4,5,6,7",
648 "Counter": "0,1,2,3,4,5,6,7",
656 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
657 "Counter": "0,1,2,3,4,5,6,7",
660 "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions. Available PDIST counters: 0",
665 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
666 "Counter": "0,1,2,3,4,5,6,7",
669 "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions. Available PDIST counters: 0",
675 "Counter": "0,1,2,3,4,5,6,7",
684 "Counter": "0,1,2,3,4,5,6,7",
693 "Counter": "0,1,2,3,4,5,6,7",
702 "Counter": "0,1,2,3,4,5,6,7",
711 "Counter": "0,1,2,3",
720 "Counter": "0,1,2,3",
729 "Counter": "0,1,2,3",
738 "Counter": "0,1,2,3",
741 "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. Available PDIST counters: 0",
747 "Counter": "0,1,2,3,4,5,6,7",
751 "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector). Available PDIST counters: 0",
757 "Counter": "0,1,2,3,4,5,6,7",
758 "CounterMask": "6",
761 "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector). Available PDIST counters: 0",
767 "Counter": "0,1,2,3,4,5,6,7",
770 "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector). Available PDIST counters: 0",
776 "Counter": "0,1,2,3,4,5,6,7",
786 "BriefDescription": "Self-modifying code (SMC) detected.",
787 "Counter": "0,1,2,3,4,5,6,7",
790 "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear. Available PDIST counters: 0",
796 "Counter": "0,1,2,3,4,5,6,7",
805 "Counter": "0,1,2,3,4,5,6,7",
814 "Counter": "0,1,2,3,4,5,6,7",
817 "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end. Available PDIST counters: 0",
823 "Counter": "0,1,2,3,4,5,6,7",
832 "Counter": "0,1,2,3,4,5,6,7",
835 "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses) Available PDIST counters: 0",
841 "Counter": "0,1,2,3,4,5,6,7",
847 "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) Available PDIST counters: 0",
853 "Counter": "0,1,2,3,4,5,6,7",
861 "BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.",
862 "Counter": "0,1,2,3,4,5,6,7",
865 "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method. Available PDIST counters: 0",
874 "PublicDescription": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations. Available PDIST counters: 0",
883 "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction. Available PDIST counters: 0",
889 "Counter": "0,1,2,3,4,5,6,7",
897 "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
900 "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3). Available PDIST counters: 0",
905 "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
906 "Counter": "0,1,2,3,4,5,6,7",
909 "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Available PDIST counters: 0",
914 "BriefDescription": "Number of non dec-by-all uops decoded by decoder",
915 "Counter": "0,1,2,3",
918 "PublicDescription": "This event counts the number of not dec-by-all uops decoded by decoder 0. Available PDIST counters: 0",
924 "Counter": "0,1,2,3,4,5,6,7",
933 "Counter": "0,1,2,3,4,5,6,7",
941 "BriefDescription": "Uops executed on ports 2, 3 and 10",
942 "Counter": "0,1,2,3,4,5,6,7",
945 "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10 Available PDIST counters: 0",
951 "Counter": "0,1,2,3,4,5,6,7",
960 "Counter": "0,1,2,3,4,5,6,7",
968 "BriefDescription": "Uops executed on port 6",
969 "Counter": "0,1,2,3,4,5,6,7",
972 "PublicDescription": "Number of uops dispatch to execution port 6. Available PDIST counters: 0",
978 "Counter": "0,1,2,3,4,5,6,7",
987 "Counter": "0,1,2,3,4,5,6,7",
995 "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
996 "Counter": "0,1,2,3,4,5,6,7",
1000 "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core. Available PDIST counters: 0",
1005 "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1006 "Counter": "0,1,2,3,4,5,6,7",
1007 "CounterMask": "2",
1010 "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core. Available PDIST counters: 0",
1015 "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1016 "Counter": "0,1,2,3,4,5,6,7",
1020 "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core. Available PDIST counters: 0",
1025 "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1026 "Counter": "0,1,2,3,4,5,6,7",
1030 "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core. Available PDIST counters: 0",
1035 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1036 "Counter": "0,1,2,3,4,5,6,7",
1040 "PublicDescription": "Cycles where at least 1 uop was executed per-thread. Available PDIST counters: 0",
1045 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1046 "Counter": "0,1,2,3,4,5,6,7",
1047 "CounterMask": "2",
1050 "PublicDescription": "Cycles where at least 2 uops were executed per-thread. Available PDIST counters: 0",
1055 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1056 "Counter": "0,1,2,3,4,5,6,7",
1060 "PublicDescription": "Cycles where at least 3 uops were executed per-thread. Available PDIST counters: 0",
1065 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1066 "Counter": "0,1,2,3,4,5,6,7",
1070 "PublicDescription": "Cycles where at least 4 uops were executed per-thread. Available PDIST counters: 0",
1076 "Counter": "0,1,2,3,4,5,6,7",
1086 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1087 "Counter": "0,1,2,3,4,5,6,7",
1090 "PublicDescription": "Counts the number of uops to be executed per-thread each cycle. Available PDIST counters: 0",
1096 "Counter": "0,1,2,3,4,5,6,7",
1105 "Counter": "0,1,2,3,4,5,6,7",
1114 "Counter": "0,1,2,3,4,5,6,7",
1124 "Counter": "0,1,2,3,4,5,6,7",
1134 "Counter": "0,1,2,3,4,5,6,7",
1137 "PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count. Available PDIST counters: 0",
1143 "Counter": "0,1,2,3,4,5,6,7",
1153 "BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.",
1154 "Counter": "0,1,2,3,4,5,6,7",
1157 "PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method. Available PDIST counters: 0",
1163 "Counter": "0,1,2,3,4,5,6,7",