Lines Matching +full:average +full:- +full:on
4 "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
11 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
18 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
25 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
43 …"BriefDescription": "The average number of cores that are in cstate C0 as observed by the power co…
49 …"BriefDescription": "The average number of cores are in cstate C6 as observed by the power control…
226 …"BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memor…
232 …"BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memor…
238 …"BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memor…
244 …"BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memor…
316 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
329 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
349 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
370 …-cases for operations that cannot be handled natively by the execution pipeline. For example; when…
384 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
389 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
395 "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
400 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
404 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
411 …"BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset …
416 …"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset…
419 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottleneck…
424 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenec…
427 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
432 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks…
435 … "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
440 …ine cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as w…
443 …tch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the…
444 …- (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_…
451 …"MetricExpr": "100 * ((1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=1@) * (tma_f…
455 …"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait tim…
458 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
463 …"Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related m…
467 …t_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (…
475 …"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispre…
482 "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
483 …"MetricExpr": "100 - (tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottlene…
487 …aining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) a…
490 …"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring catego…
491 … "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIR…
499 …"MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\…
504 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
513 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
517 … represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized…
525 … represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized…
534 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
538 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
543 …"MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES …
552 …RONTEND_RETIRED.L1I_MISS * FRONTEND_RETIRED.L1I_MISS:R / tma_info_thread_clks - tma_code_l2_miss)",
567 …e (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (ST…
568 …END_RETIRED.ITLB_MISS * FRONTEND_RETIRED.ITLB_MISS:R / tma_info_thread_clks - tma_code_stlb_miss)",
575 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
599 …s fraction of cycles the CPU was stalled due to retired misprediction by non-taken conditional bra…
621 …ata written by one Logical Processor are read by another Logical Processor on a different Physical…
625 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
627 "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
632 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
636 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
638 …LOAD_L3_HIT_RETIRED.XSNP_FWD:R, 74.6 * tma_info_system_core_frequency) * (1 - OCR.DEMAND_DATA_RD.L…
642 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
646 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
647 …"MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) /…
651 …"PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only activ…
664 …"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external m…
669 …"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external …
674 "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2",
687 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
696 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
700 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
705 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
714 …a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapp…
723 …the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidt…
729 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
740 …MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
745 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
750 "MetricExpr": "max(0, tma_heavy_operations - tma_microcode_sequencer)",
754 …tiring instructions that that are decoder into two or more uops. This highly-correlates with the n…
758 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
763 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
772 …ts. FP Assist may apply when working with very small floating point values (so-called Denormals).",
776 …"BriefDescription": "This metric represents fraction of cycles where the Floating-Point Divider un…
784 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
789 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
793 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
798 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
802 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
807 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
811 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
816 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
820 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
825 … approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May…
831 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
836 …on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch…
840 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
845 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
849 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
851 …"MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
856 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
878 …"MetricExpr": "max((BR_MISP_RETIRED.INDIRECT_COST * BR_MISP_RETIRED.INDIRECT_COST:R - BR_MISP_RETI…
885 …Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch mi…
889 …Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch mi…
892 …"BriefDescription": "Instructions per retired Mispredicts for conditional non-taken branches (lowe…
920 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
933 … "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
934 …"MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_ut…
940 …"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch…
945 …"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetc…
948 …"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fet…
953 …"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fe…
956 …"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bott…
961 …"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bot…
970 "BriefDescription": "Fraction of branches that are non-taken conditionals",
983 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR…
989 …"MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_call…
994 …"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
1000 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
1018 …BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardles…
1022 …-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width…
1025 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
1039 …"BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch un…
1052 "BriefDescription": "Average number of Uops issued by front-end when it issued something",
1058 "BriefDescription": "Average Latency for L1 instruction cache misses",
1064 …"BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurren…
1102 …"BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch d…
1106 …"PublicDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch …
1136 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
1141 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
1144 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
1149 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
1152 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
1157 …"PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means h…
1160 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
1165 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
1168 …"BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower numbe…
1173 …"PublicDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower numb…
1176 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
1181 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
1240 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
1246 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
1264 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
1270 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
1276 … instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
1282 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
1300 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
1307 "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
1342 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
1348 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
1360 "BriefDescription": "Average Parallel L2 cache miss data reads",
1366 "BriefDescription": "Average Latency for L2 cache miss demand Loads",
1372 "BriefDescription": "Average Parallel L2 cache miss demand Loads",
1378 "BriefDescription": "Average Latency for L3 cache miss demand Loads",
1384 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
1396 "BriefDescription": "Off-core accesses per kilo instruction for modified write requests",
1402 …"BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculativ…
1408 …tion": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in…
1414 "BriefDescription": "Un-cacheable retired load per kilo instruction",
1420 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
1424 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
1434 …"BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local…
1438 …"PublicDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to loca…
1441 "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C)",
1445 …"PublicDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRA…
1448 "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C)",
1452 …"PublicDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand o…
1455 … level TLB) code speculative misses per kilo instruction (misses of any page-size that complete th…
1468 …l TLB) data load speculative misses per kilo instruction (misses of any page-size that complete th…
1488 … TLB) data store speculative misses per kilo instruction (misses of any page-size that complete th…
1500 "BriefDescription": "Average number of uops fetched from DSB per cycle",
1506 "BriefDescription": "Average number of uops fetched from MITE per cycle",
1520 …"BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
1526 … "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
1533 …et unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized…
1540 "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]",
1546 "BriefDescription": "Average CPU Utilization (percentage)",
1552 "BriefDescription": "Average number of utilized CPUs",
1558 "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
1562 …"PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Relat…
1569 …egate across all supported options of: FP precisions, scalar and vector instructions, vector-width"
1572 "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
1576 …"PublicDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth o…
1579 "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
1583 …"PublicDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth …
1606 …"BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]…
1610 …cDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Acc…
1613 "BriefDescription": "Average number of parallel data read requests to external memory",
1617 …"PublicDescription": "Average number of parallel data read requests to external memory. Accounts f…
1628 … "MetricExpr": "(power@energy\\-pkg@ * 61 + 15.6 * power@energy\\-ram@) / (duration_time * 1e6)",
1634 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_…
1639 "BriefDescription": "Socket actual clocks when any core is active on that socket",
1652 "BriefDescription": "Average Frequency Utilization relative nominal frequency",
1658 "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]",
1664 …"BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data o…
1670 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
1682 "BriefDescription": "The ratio of Executed- by Issued-Uops",
1686 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
1695 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
1701 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
1722 "MetricExpr": "tma_divider - tma_fp_divider",
1738 …"BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neu…
1743 …"PublicDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Ne…
1747 …"BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector…
1752 …"PublicDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vecto…
1766 …"MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / tma_info_thre…
1770 …on older stores; a load might suffer due to high latency even though it is being satisfied by the …
1775 …EM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CY…
1779 … the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access…
1784 …"MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / tma_info_threa…
1803 …"MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / tma_info_thread…
1830 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
1832 "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
1837 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
1841 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
1846 …"PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execut…
1850 …here the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (ST…
1851 "MetricExpr": "max(0, tma_dtlb_load - tma_load_stlb_miss)",
1858 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
1910 "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
1915 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
1927 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
1932 …- DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic i…
1936 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1937 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1941 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1947 …"MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
1952 …-completed in-flight memory demand loads which coincides with execution units starvation; in addit…
1965 … represents fraction of slots where the CPU was retiring memory operations -- uops for memory load…
1992 "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2",
1996 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
2000 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
2005 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
2009 …es in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequen…
2022 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
2027 …"MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / …
2031 …lots where the CPU was retiring branch instructions that were not fused. Non-conditional branches …
2040 …o op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address o…
2044 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
2045 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_opera…
2049 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
2053 …action of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches …
2054 …"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_C…
2062 …"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT…
2074 …PU retired uops as a result of handing Page Faults. A Page Fault may apply on first application ac…
2078 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
2083 …"PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execut…
2087 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
2092 …"PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execut…
2096 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
2101 …"PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execut…
2105 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
2106 …)) / tma_info_thread_clks if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_O…
2110 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
2114 …"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any executi…
2115 …"MetricExpr": "max(EXE_ACTIVITY.EXE_BOUND_0_PORTS - RESOURCE_STALLS.SCOREBOARD, 0) / tma_info_thre…
2119 …cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Co…
2123 …resents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports …
2128 …on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This …
2132 …etric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports …
2138 …on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop…
2142 …presents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports …
2148 …presents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports …
2157 …r sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocati…
2166 …ystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocati…
2180 …"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retir…
2185 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
2189 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
2194 …ycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; W…
2198 …sents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP o…
2203 …sents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP o…
2217 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
2222 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
2231 …resents rate of split store accesses. Consider aligning your data to the 64-byte cache line granu…
2235 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
2240 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
2244 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
2249 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
2258 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
2263 …xpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_ST…
2267 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
2271 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
2276 …"PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execut…
2280 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
2281 "MetricExpr": "max(0, tma_dtlb_store - tma_store_stlb_miss)",
2325 …uired by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there ar…