Lines Matching +full:0 +full:xc7

4         "Counter": "0,1,2,3,4,5,6,7",
6         "EventCode": "0xb0",
8 …n": "This event counts the cycles the floating point divider is busy. Available PDIST counters: 0",
10         "UMask": "0x1"
14         "Counter": "0,1,2,3,4,5,6,7",
15         "EventCode": "0xc1",
17 …   "PublicDescription": "Counts all microcode Floating Point assists. Available PDIST counters: 0",
19         "UMask": "0x2"
23         "Counter": "0,1,2,3,4,5,6,7",
24         "EventCode": "0xc1",
26         "PublicDescription": "ASSISTS.SSE_AVX_MIX Available PDIST counters: 0",
28         "UMask": "0x10"
32         "Counter": "0,1,2,3,4,5,6,7",
33         "EventCode": "0xb3",
35 …ITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0] Available PDIST counters: 0",
37         "UMask": "0x1"
41         "Counter": "0,1,2,3,4,5,6,7",
42         "EventCode": "0xb3",
44 …ITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1] Available PDIST counters: 0",
46         "UMask": "0x2"
50         "Counter": "0,1,2,3,4,5,6,7",
51         "EventCode": "0xb3",
53 …ITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2] Available PDIST counters: 0",
55         "UMask": "0x4"
59         "Counter": "0,1,2,3,4,5,6,7",
60         "EventCode": "0xb3",
62 …ITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0] Available PDIST counters: 0",
64         "UMask": "0x1"
68         "Counter": "0,1,2,3,4,5,6,7",
69         "EventCode": "0xb3",
71 …ITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1] Available PDIST counters: 0",
73         "UMask": "0x2"
77         "Counter": "0,1,2,3,4,5,6,7",
78         "EventCode": "0xb3",
80 …ITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5] Available PDIST counters: 0",
82         "UMask": "0x4"
86         "Counter": "0,1,2,3,4,5,6,7",
87         "EventCode": "0xc7",
89 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
91         "UMask": "0x4"
95         "Counter": "0,1,2,3,4,5,6,7",
96         "EventCode": "0xc7",
98 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
100         "UMask": "0x8"
104         "Counter": "0,1,2,3,4,5,6,7",
105         "EventCode": "0xc7",
107 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
109         "UMask": "0x10"
113         "Counter": "0,1,2,3,4,5,6,7",
114         "EventCode": "0xc7",
116 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
118         "UMask": "0x20"
122         "Counter": "0,1,2,3,4,5,6,7",
123         "EventCode": "0xc7",
125 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
127         "UMask": "0x18"
131         "Counter": "0,1,2,3,4,5,6,7",
132         "EventCode": "0xc7",
134 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
136         "UMask": "0x40"
140         "Counter": "0,1,2,3,4,5,6,7",
141         "EventCode": "0xc7",
143 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
145         "UMask": "0x80"
149         "Counter": "0,1,2,3,4,5,6,7",
150         "EventCode": "0xc7",
152 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
154         "UMask": "0x60"
158         "Counter": "0,1,2,3,4,5,6,7",
159         "EventCode": "0xc7",
161 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
163         "UMask": "0x3"
167         "Counter": "0,1,2,3,4,5,6,7",
168         "EventCode": "0xc7",
170 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
172         "UMask": "0x1"
176         "Counter": "0,1,2,3,4,5,6,7",
177         "EventCode": "0xc7",
179 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
181         "UMask": "0x2"
185         "Counter": "0,1,2,3,4,5,6,7",
186         "EventCode": "0xc7",
188 …Z flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
190         "UMask": "0xfc"
194         "Counter": "0,1,2,3,4,5,6,7",
195         "EventCode": "0xcf",
197         "PublicDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF Available PDIST counters: 0",
199         "UMask": "0x4"
203         "Counter": "0,1,2,3,4,5,6,7",
204         "EventCode": "0xcf",
206         "PublicDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF Available PDIST counters: 0",
208         "UMask": "0x8"
212         "Counter": "0,1,2,3,4,5,6,7",
213         "EventCode": "0xcf",
215         "PublicDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF Available PDIST counters: 0",
217         "UMask": "0x10"
221         "Counter": "0,1,2,3,4,5,6,7",
222         "EventCode": "0xcf",
224 …     "PublicDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF Available PDIST counters: 0",
226         "UMask": "0x2"
230         "Counter": "0,1,2,3,4,5,6,7",
231         "EventCode": "0xcf",
233         "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR Available PDIST counters: 0",
235         "UMask": "0x3"
239         "Counter": "0,1,2,3,4,5,6,7",
240         "EventCode": "0xcf",
242         "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF Available PDIST counters: 0",
244         "UMask": "0x1"
248         "Counter": "0,1,2,3,4,5,6,7",
249         "EventCode": "0xcf",
251         "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR Available PDIST counters: 0",
253         "UMask": "0x1c"