Lines Matching +full:3 +full:- +full:6
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
78 "Counter": "0,1,2,3,4,5,6,7",
86 "Counter": "0,1,2,3,4,5,6,7",
89 "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
94 "Counter": "0,1,2,3,4,5,6,7",
102 "Counter": "0,1,2,3,4,5,6,7",
110 "Counter": "0,1,2,3,4,5,6,7",
118 "Counter": "0,1,2,3,4,5,6,7",
126 "Counter": "0,1,2,3,4,5,6,7",
134 "Counter": "0,1,2,3,4,5,6,7",
149 "Counter": "0,1,2,3,4,5,6,7",
163 "Counter": "0,1,2,3,4,5,6,7",
179 "Counter": "0,1,2,3,4,5,6,7",
193 "Counter": "0,1,2,3,4,5,6,7",
200 "Counter": "0,1,2,3,4,5,6,7",
208 "Counter": "0,1,2,3,4,5,6,7",
216 "Counter": "0,1,2,3,4,5,6,7",
224 "Counter": "0,1,2,3,4,5,6,7",
231 "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
232 "Counter": "0,1,2,3,4,5,6,7",
240 "Counter": "0,1,2,3,4,5,6,7",
248 "Counter": "0,1,2,3,4,5,6,7",
256 "Counter": "0,1,2,3,4,5,6,7",
264 "Counter": "0,1,2,3,4,5,6,7",
272 "Counter": "0,1,2,3,4,5,6,7",
280 "Counter": "0,1,2,3,4,5,6,7",
288 "Counter": "0,1,2,3,4,5,6,7",
296 "Counter": "0,1,2,3,4,5,6,7",
304 "Counter": "0,1,2,3,4,5,6,7",
312 "Counter": "0,1,2,3,4,5,6,7",
319 "Counter": "0,1,2,3,4,5,6,7",
327 "Counter": "0,1,2,3,4,5,6,7",
334 "Counter": "0,1,2,3,4,5,6,7",
341 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. )",
342 "Counter": "0,1,2,3,4,5,6,7",
350 "Counter": "0,1,2,3,4,5,6,7",
358 "Counter": "0,1,2,3,4,5,6,7",
366 "Counter": "0,1,2,3,4,5,6,7",
374 "Counter": "0,1,2,3,4,5,6,7",
381 "Counter": "0,1,2,3,4,5,6,7",
388 "Counter": "0,1,2,3,4,5,6,7",
396 "Counter": "0,1,2,3,4,5,6,7",
404 "Counter": "0,1,2,3,4,5,6,7",
412 "Counter": "0,1,2,3,4,5,6,7",
420 "Counter": "0,1,2,3,4,5,6,7",
428 "Counter": "0,1,2,3,4,5,6,7",
436 "Counter": "0,1,2,3,4,5,6,7",
445 "Counter": "0,1,2,3,4,5,6,7",
453 "Counter": "0,1,2,3,4,5,6,7",
461 "Counter": "0,1,2,3,4,5,6,7",
469 "Counter": "0,1,2,3,4,5,6,7",
476 "Counter": "0,1,2,3,4,5,6,7",
483 "Counter": "0,1,2,3,4,5,6,7",
486 "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
491 "Counter": "0,1,2,3,4,5,6,7",
498 "Counter": "0,1,2,3,4,5,6,7",
505 "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
506 "Counter": "0,1,2,3,4,5,6,7",
514 "Counter": "0,1,2,3,4,5,6,7",